---------- Begin Simulation Statistics ----------
simSeconds 0.023471 # Number of seconds simulated (Second)
simTicks 23470778061 # Number of ticks simulated (Tick)
finalTick 23470778061 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 35.19 # Real time elapsed on the host (Second)
hostTickRate 666977933 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 489248 # Number of bytes of host memory used (Byte)
simInsts 26728147 # Number of instructions simulated (Count)
simOps 41096287 # Number of ops (including micro ops) simulated (Count)
hostInstRate 759541 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 1167845 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 23470778061 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 23470778061 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 23470778061 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 23470778061 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.demandHits::processor.cores.core.data 15281585 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.demandHits::total 15281585 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::processor.cores.core.data 15281585 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::total 15281585 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.demandMisses::processor.cores.core.data 126230 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.demandMisses::total 126230 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::processor.cores.core.data 126230 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::total 126230 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.demandMissLatency::processor.cores.core.data 6006902751 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMissLatency::total 6006902751 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::processor.cores.core.data 6006902751 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::total 6006902751 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandAccesses::processor.cores.core.data 15407815 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandAccesses::total 15407815 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::processor.cores.core.data 15407815 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::total 15407815 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandMissRate::processor.cores.core.data 0.008193 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMissRate::total 0.008193 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::processor.cores.core.data 0.008193 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::total 0.008193 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::processor.cores.core.data 47586.966260 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::total 47586.966260 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::processor.cores.core.data 47586.966260 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::total 47586.966260 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.writebacks::writebacks 5460 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.writebacks::total 5460 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::processor.cores.core.data 21 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::total 21 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::processor.cores.core.data 21 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::total 21 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::processor.cores.core.data 126209 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::total 126209 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::cache_hierarchy.l1dcaches.prefetcher 4905 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::processor.cores.core.data 126209 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::total 131114 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::processor.cores.core.data 5964719643 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::total 5964719643 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 296469125 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::processor.cores.core.data 5964719643 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::total 6261188768 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::processor.cores.core.data 0.008191 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::total 0.008191 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::cache_hierarchy.l1dcaches.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::processor.cores.core.data 0.008191 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::total 0.008510 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::processor.cores.core.data 47260.652117 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::total 47260.652117 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 60442.227319 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::processor.cores.core.data 47260.652117 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::total 47753.777385 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.replacements 130986 # number of replacements (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches.prefetcher 4905 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::total 4905 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 296469125 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::total 296469125 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 60442.227319 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::total 60442.227319 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.hits::processor.cores.core.data 13192619 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.hits::total 13192619 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::processor.cores.core.data 122081 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::total 122081 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::processor.cores.core.data 5913730350 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::total 5913730350 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::processor.cores.core.data 13314700 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::total 13314700 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::processor.cores.core.data 0.009169 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::total 0.009169 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::processor.cores.core.data 48441.037917 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::total 48441.037917 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.mshrHits::processor.cores.core.data 7 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrHits::total 7 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::processor.cores.core.data 122074 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::total 122074 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::processor.cores.core.data 5873038416 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::total 5873038416 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::processor.cores.core.data 0.009168 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::total 0.009168 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::processor.cores.core.data 48110.477383 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::total 48110.477383 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.hits::processor.cores.core.data 2088966 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.hits::total 2088966 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::processor.cores.core.data 4149 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::total 4149 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::processor.cores.core.data 93172401 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::total 93172401 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::processor.cores.core.data 2093115 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::total 2093115 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::processor.cores.core.data 0.001982 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::total 0.001982 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::processor.cores.core.data 22456.592191 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::total 22456.592191 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.mshrHits::processor.cores.core.data 14 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrHits::total 14 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::processor.cores.core.data 4135 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::total 4135 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::processor.cores.core.data 91681227 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::total 91681227 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::processor.cores.core.data 0.001976 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::total 0.001976 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::processor.cores.core.data 22172.001693 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::total 22172.001693 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.power_state.pwrStateResidencyTicks::UNDEFINED 23470778061 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.prefetcher.demandMshrMisses 126209 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIssued 11476 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUnused 2884 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUseful 1996 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches.prefetcher.accuracy 0.173928 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.coverage 0.015569 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInCache 6423 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInMSHR 148 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfLate 6571 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIdentified 11476 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfSpanPage 532 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulSpanPage 321 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 23470778061 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.tags.tagsInUse 127.957295 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches.tags.totalRefs 15412699 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.sampledRefs 131114 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.avgRefs 117.551894 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches.tags.warmupTick 127539 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches.tags.occupancies::cache_hierarchy.l1dcaches.prefetcher 3.590680 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.occupancies::processor.cores.core.data 124.366616 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::cache_hierarchy.l1dcaches.prefetcher 0.028052 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::processor.cores.core.data 0.971614 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::total 0.999666 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1022 67 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1024 61 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1022::0 2 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1022::1 65 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::0 58 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::1 1 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::4 2 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1022 0.523438 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1024 0.476562 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.tagAccesses 123393634 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches.tags.dataAccesses 123393634 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 23470778061 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.demandHits::processor.cores.core.inst 37073976 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.demandHits::total 37073976 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.overallHits::processor.cores.core.inst 37073976 # number of overall hits (Count)
board.cache_hierarchy.l1icaches.overallHits::total 37073976 # number of overall hits (Count)
board.cache_hierarchy.l1icaches.demandMisses::processor.cores.core.inst 568 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.demandMisses::total 568 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::processor.cores.core.inst 568 # number of overall misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::total 568 # number of overall misses (Count)
board.cache_hierarchy.l1icaches.demandMissLatency::processor.cores.core.inst 29475495 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMissLatency::total 29475495 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::processor.cores.core.inst 29475495 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::total 29475495 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandAccesses::processor.cores.core.inst 37074544 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandAccesses::total 37074544 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::processor.cores.core.inst 37074544 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::total 37074544 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandMissRate::processor.cores.core.inst 0.000015 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMissRate::total 0.000015 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::processor.cores.core.inst 0.000015 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::total 0.000015 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMissLatency::processor.cores.core.inst 51893.477113 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMissLatency::total 51893.477113 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::processor.cores.core.inst 51893.477113 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::total 51893.477113 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.writebacks::writebacks 312 # number of writebacks (Count)
board.cache_hierarchy.l1icaches.writebacks::total 312 # number of writebacks (Count)
board.cache_hierarchy.l1icaches.demandMshrMisses::processor.cores.core.inst 568 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMisses::total 568 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::processor.cores.core.inst 568 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::total 568 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::processor.cores.core.inst 29286351 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::total 29286351 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::processor.cores.core.inst 29286351 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::total 29286351 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissRate::processor.cores.core.inst 0.000015 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMshrMissRate::total 0.000015 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::processor.cores.core.inst 0.000015 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::total 0.000015 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::processor.cores.core.inst 51560.477113 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::total 51560.477113 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::processor.cores.core.inst 51560.477113 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::total 51560.477113 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.replacements 312 # number of replacements (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::processor.cores.core.inst 37073976 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::total 37073976 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::processor.cores.core.inst 568 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::total 568 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::processor.cores.core.inst 29475495 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::total 29475495 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.accesses::processor.cores.core.inst 37074544 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.accesses::total 37074544 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.missRate::processor.cores.core.inst 0.000015 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.missRate::total 0.000015 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::processor.cores.core.inst 51893.477113 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::total 51893.477113 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::processor.cores.core.inst 568 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::total 568 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::processor.cores.core.inst 29286351 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::total 29286351 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::processor.cores.core.inst 0.000015 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::total 0.000015 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::processor.cores.core.inst 51560.477113 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::total 51560.477113 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.power_state.pwrStateResidencyTicks::UNDEFINED 23470778061 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.prefetcher.demandMshrMisses 568 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 23470778061 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.tags.tagsInUse 255.861690 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches.tags.totalRefs 37074544 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.sampledRefs 568 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.avgRefs 65272.084507 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches.tags.warmupTick 69597 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches.tags.occupancies::processor.cores.core.inst 255.861690 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::processor.cores.core.inst 0.999460 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::total 0.999460 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.occupanciesTaskId::1024 256 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::0 106 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::2 4 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::4 146 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches.tags.tagAccesses 296596920 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches.tags.dataAccesses 296596920 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 23470778061 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.transDist::ReadResp 127547 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WritebackDirty 5460 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WritebackClean 312 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::CleanEvict 125526 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq 4135 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp 4135 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq 127547 # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::board.memory.mem_ctrl.port 1448 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::total 1448 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::board.memory.mem_ctrl.port 393214 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::total 393214 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total 394662 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::board.memory.mem_ctrl.port 56320 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::total 56320 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::board.memory.mem_ctrl.port 8740736 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::total 8740736 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total 8797056 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 131682 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 131682 100.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 131682 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 23470778061 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 23470778061 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy 90105251 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer1.occupancy 479930 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer2.occupancy 113319882 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer2.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests 262980 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 131298 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl.avgPriority_writebacks::samples 2405.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_cache_hierarchy.l1dcaches.prefetcher::samples 4894.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.inst::samples 566.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.data::samples 122813.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl.priorityMaxLatency 0.003578322780 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl.numReadWriteTurnArounds 136 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl.numWriteReadTurnArounds 137 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl.numStayReadState 267120 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl.numStayWriteState 2253 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl.readReqs 131682 # Number of read requests accepted (Count)
board.memory.mem_ctrl.writeReqs 5772 # Number of write requests accepted (Count)
board.memory.mem_ctrl.readBursts 131682 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl.writeBursts 5772 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl.servicedByWrQ 3409 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl.mergedWrBursts 3367 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl.avgRdQLen 1.03 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.avgWrQLen 24.78 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::6 131682 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::6 5772 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.rdQLenPdf::0 124631 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::1 1391 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::2 781 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::3 743 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::4 718 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::5 9 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::15 90 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::16 91 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::17 135 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::18 135 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::19 137 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::20 137 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::21 146 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::22 137 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::23 137 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::24 137 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::25 138 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::26 140 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::27 143 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::28 139 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::29 137 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::30 137 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::31 137 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::32 137 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdPerTurnAround::samples 137 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::mean 936.299270 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::gmean 81.831866 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::stdev 1515.760324 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::0-127 98 71.53% 71.53% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::256-383 1 0.73% 72.26% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::512-639 1 0.73% 72.99% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::1536-1663 1 0.73% 73.72% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::2560-2687 2 1.46% 75.18% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::2688-2815 1 0.73% 75.91% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::3072-3199 2 1.46% 77.37% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::3200-3327 6 4.38% 81.75% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::3328-3455 9 6.57% 88.32% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::3456-3583 4 2.92% 91.24% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::3584-3711 7 5.11% 96.35% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::3712-3839 2 1.46% 97.81% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::3840-3967 1 0.73% 98.54% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::3968-4095 2 1.46% 100.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::total 137 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.wrPerTurnAround::samples 136 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::mean 17.441176 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::gmean 17.404144 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::stdev 1.140271 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::16 46 33.82% 33.82% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::17 1 0.74% 34.56% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::18 80 58.82% 93.38% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::19 1 0.74% 94.12% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::20 8 5.88% 100.00% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::total 136 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.bytesReadWrQ 218176 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl.bytesReadSys 8427648 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl.bytesWrittenSys 369408 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl.avgRdBWSys 359069817.71531993 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.avgWrBWSys 15739060.67536054 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.totGap 23470774065 # Total gap between requests (Tick)
board.memory.mem_ctrl.avgGap 170753.66 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl.requestorReadBytes::cache_hierarchy.l1dcaches.prefetcher 313216 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.inst 36224 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.data 7860032 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorWriteBytes::writebacks 152256 # Per-requestor bytes write to memory (Byte)
board.memory.mem_ctrl.requestorReadRate::cache_hierarchy.l1dcaches.prefetcher 13344934.675193082541 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.inst 1543365.963661480462 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.data 334885872.959642052650 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorWriteRate::writebacks 6487045.278358059935 # Per-requestor bytes write to memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadAccesses::cache_hierarchy.l1dcaches.prefetcher 4905 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.inst 568 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.data 126209 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorWriteAccesses::writebacks 5772 # Per-requestor write serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadTotalLat::cache_hierarchy.l1dcaches.prefetcher 179756075 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.inst 15760795 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.data 2986951618 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorWriteTotalLat::writebacks 560270683528 # Per-requestor write total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadAvgLat::cache_hierarchy.l1dcaches.prefetcher 36647.52 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.inst 27747.88 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.data 23666.71 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorWriteAvgLat::writebacks 97066992.99 # Per-requestor write average memory access latency ((Tick/Count))
board.memory.mem_ctrl.dram.bytesRead::cache_hierarchy.l1dcaches.prefetcher 313920 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.inst 36352 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.data 8077376 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::total 8427648 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::processor.cores.core.inst 36352 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::total 36352 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesWritten::writebacks 349440 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl.dram.bytesWritten::total 349440 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl.dram.numReads::cache_hierarchy.l1dcaches.prefetcher 4905 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.inst 568 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.data 126209 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::total 131682 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numWrites::writebacks 5460 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numWrites::total 5460 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.bwRead::cache_hierarchy.l1dcaches.prefetcher 13374929 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.inst 1548820 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.data 344146069 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::total 359069818 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::processor.cores.core.inst 1548820 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::total 1548820 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwWrite::writebacks 14888301 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwWrite::total 14888301 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::writebacks 14888301 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::cache_hierarchy.l1dcaches.prefetcher 13374929 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.inst 1548820 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.data 344146069 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::total 373958118 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.readBursts 128273 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl.dram.writeBursts 2379 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::0 951 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::1 880 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::2 569 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::3 491 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::4 496 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::5 951 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::6 881 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::7 925 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::8 14539 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::9 25124 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::10 21909 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::11 22536 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::12 25083 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::13 11314 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::14 795 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::15 829 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::0 210 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::1 214 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::2 138 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::3 84 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::4 135 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::5 141 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::6 130 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::7 138 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::8 141 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::9 133 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::10 198 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::11 152 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::12 133 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::13 139 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::14 145 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::15 148 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.totQLat 777349738 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl.dram.totBusLat 641365000 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl.dram.totMemAccLat 3182468488 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl.dram.avgQLat 6060.12 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgBusLat 5000.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgMemAccLat 24810.12 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.readRowHits 108605 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl.dram.writeRowHits 2123 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl.dram.readRowHitRate 84.67 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl.dram.writeRowHitRate 89.24 # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl.dram.bytesPerActivate::samples 19915 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::mean 419.787296 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::gmean 359.985848 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::stdev 211.385711 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::0-127 596 2.99% 2.99% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::128-255 3471 17.43% 20.42% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::256-383 4553 22.86% 43.28% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::384-511 4124 20.71% 63.99% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::512-639 3368 16.91% 80.90% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::640-767 2171 10.90% 91.81% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::768-895 1079 5.42% 97.22% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::896-1023 291 1.46% 98.68% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::1024-1151 262 1.32% 100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::total 19915 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.dramBytesRead 8209472 # Total bytes read (Byte)
board.memory.mem_ctrl.dram.dramBytesWritten 152256 # Total bytes written (Byte)
board.memory.mem_ctrl.dram.avgRdBW 349.774174 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.avgWrBW 6.487045 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl.dram.busUtil 2.78 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl.dram.busUtilRead 2.73 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl.dram.busUtilWrite 0.05 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl.dram.pageHitRate 84.75 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl.dram.power_state.pwrStateResidencyTicks::UNDEFINED 23470778061 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl.dram.rank0.actEnergy 12080880 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preEnergy 6405960 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.readEnergy 43868160 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.writeEnergy 6211800 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.refreshEnergy 1852524960.000000 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actBackEnergy 3219457470 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preBackEnergy 6301656960 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.totalEnergy 11442206190 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.averagePower 487.508602 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::IDLE 16350957921 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::REF 783640000 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT 6336180140 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.actEnergy 130176480 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preEnergy 69167670 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.readEnergy 872001060 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.writeEnergy 6175260 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.refreshEnergy 1852524960.000000 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actBackEnergy 9952287780 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preBackEnergy 631905120 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.totalEnergy 13514238330 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.averagePower 575.789959 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::IDLE 1561773283 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::REF 783640000 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT 21125364778 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.power_state.pwrStateResidencyTicks::UNDEFINED 23470778061 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles 70482817 # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.cpi 2.637024 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores.core.ipc 0.379215 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores.core.commitStats0.numInsts 26728168 # Number of instructions committed (thread level) (Count)
board.processor.cores.core.commitStats0.numOps 41096338 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores.core.commitStats0.cpi 2.637024 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores.core.commitStats0.ipc 0.379215 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.cores.core.commitStats0.numFpInsts 1372 # Number of float instructions (Count)
board.processor.cores.core.commitStats0.numIntInsts 41095270 # Number of integer instructions (Count)
board.processor.cores.core.commitStats0.numLoadInsts 13314722 # Number of load instructions (Count)
board.processor.cores.core.commitStats0.numStoreInsts 2093120 # Number of store instructions (Count)
board.processor.cores.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores.core.commitStats0.committedInstType::No_OpClass 341 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntAlu 22647397 55.11% 55.11% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntMult 3040040 7.40% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntDiv 56 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatAdd 146 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCmp 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCvt 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMult 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatDiv 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMisc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAdd 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAlu 160 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCmp 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCvt 86 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMisc 270 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMult 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShift 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdDiv 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAes 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::Matrix 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixMov 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixOP 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemRead 13314634 32.40% 94.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemWrite 2092647 5.09% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemRead 88 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemWrite 473 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::total 41096338 # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedControl::IsControl 1054261 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsDirectControl 1053819 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsIndirectControl 442 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCondControl 1043154 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsUncondControl 11107 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCall 263 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsReturn 259 # Class of control type instructions committed (Count)
board.processor.cores.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.cores.core.exec_context.thread_0.numCallsReturns 522 # Number of times a function call or return occured (Count)
board.processor.cores.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.cores.core.exec_context.thread_0.numIdleCycles 0.003003 # Number of idle cycles (Cycle)
board.processor.cores.core.exec_context.thread_0.numBusyCycles 70482816.996997 # Number of busy cycles (Cycle)
board.processor.cores.core.exec_context.thread_0.notIdleFraction 1.000000 # Percentage of non-idle cycles (Ratio)
board.processor.cores.core.exec_context.thread_0.idleFraction 0.000000 # Percentage of idle cycles (Ratio)
board.processor.cores.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.cores.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.cores.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.cores.core.executeStats0.numStoreInsts 15407842 # Number of stores executed (Count)
board.processor.cores.core.executeStats0.instRate 0 # Inst execution rate ((Count/Cycle))
board.processor.cores.core.executeStats0.numFpAluAccesses 1372 # Number of float alu accesses (Count)
board.processor.cores.core.executeStats0.numFpRegReads 1683 # Number of times the floating registers were read (Count)
board.processor.cores.core.executeStats0.numFpRegWrites 817 # Number of times the floating registers were written (Count)
board.processor.cores.core.executeStats0.numIntAluAccesses 41095270 # Number of integer alu accesses (Count)
board.processor.cores.core.executeStats0.numIntRegReads 61498641 # Number of times the integer registers were read (Count)
board.processor.cores.core.executeStats0.numIntRegWrites 36904843 # Number of times the integer registers were written (Count)
board.processor.cores.core.executeStats0.numMemRefs 15407842 # Number of memory refs (Count)
board.processor.cores.core.executeStats0.numMiscRegReads 17516410 # Number of times the Misc registers were read (Count)
board.processor.cores.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores.core.fetchStats0.numInsts 26728168 # Number of instructions fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.numOps 41096338 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.fetchRate 0.379215 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores.core.fetchStats0.numBranches 1054261 # Number of branches fetched (Count)
board.processor.cores.core.fetchStats0.branchRate 0.014958 # Number of branch fetches per cycle (Ratio)
board.processor.cores.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.cores.core.mmu.dtb.rdAccesses 13314728 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrAccesses 2093120 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.dtb.rdMisses 68 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrMisses 15 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 23470778061 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.itb.wrAccesses 37074544 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.itb.wrMisses 49 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 23470778061 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON 23470778061 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.cores.core.workload.numSyscalls 18 # Number of system calls (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------