[board]
type=System
children=cache_hierarchy clk_domain dvfs_handler memory processor workload
auto_unlink_shared_backstore=false
cache_line_size=64
eventq_index=0
exit_on_work_items=true
external_memory_ranges=
init_param=0
m5ops_base=4294901760
mem_mode=timing
mem_ranges=0:3221225472 3221225472:3222274048
memories=board.memory.mem_ctrl.dram
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
readfile=
redirect_paths=
shadow_rom_ranges=
shared_backstore=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
workload=board.workload
system_port=board.cache_hierarchy.membus.cpu_side_ports[0]

[board.cache_hierarchy]
type=SubSystem
children=dptw_caches iptw_caches l1dcaches l1icaches l2bus l2cache membus
eventq_index=0
thermal_domain=Null

[board.cache_hierarchy.dptw_caches]
type=Cache
children=power_state replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=20
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.dptw_caches.power_state
prefetcher=Null
replace_expansions=true
replacement_policy=board.cache_hierarchy.dptw_caches.replacement_policy
response_latency=1
sequential_access=false
size=8192
system=board
tag_latency=1
tags=board.cache_hierarchy.dptw_caches.tags
tgts_per_mshr=12
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=false
cpu_side=board.processor.cores.core.mmu.dtb.walker.port
mem_side=board.cache_hierarchy.l2bus.cpu_side_ports[3]

[board.cache_hierarchy.dptw_caches.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.dptw_caches.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.dptw_caches.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=4
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.dptw_caches.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.dptw_caches.tags.power_state
replacement_policy=board.cache_hierarchy.dptw_caches.replacement_policy
sequential_access=false
size=8192
system=board
tag_latency=1
warmup_percentage=0

[board.cache_hierarchy.dptw_caches.tags.indexing_policy]
type=TaggedSetAssociative
assoc=4
entry_size=64
eventq_index=0
size=8192

[board.cache_hierarchy.dptw_caches.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.iptw_caches]
type=Cache
children=power_state replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=20
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.iptw_caches.power_state
prefetcher=Null
replace_expansions=true
replacement_policy=board.cache_hierarchy.iptw_caches.replacement_policy
response_latency=1
sequential_access=false
size=8192
system=board
tag_latency=1
tags=board.cache_hierarchy.iptw_caches.tags
tgts_per_mshr=12
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=false
cpu_side=board.processor.cores.core.mmu.itb.walker.port
mem_side=board.cache_hierarchy.l2bus.cpu_side_ports[2]

[board.cache_hierarchy.iptw_caches.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.iptw_caches.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.iptw_caches.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=4
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.iptw_caches.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.iptw_caches.tags.power_state
replacement_policy=board.cache_hierarchy.iptw_caches.replacement_policy
sequential_access=false
size=8192
system=board
tag_latency=1
warmup_percentage=0

[board.cache_hierarchy.iptw_caches.tags.indexing_policy]
type=TaggedSetAssociative
assoc=4
entry_size=64
eventq_index=0
size=8192

[board.cache_hierarchy.iptw_caches.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1dcaches]
type=Cache
children=power_state prefetcher replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=16
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1dcaches.power_state
prefetcher=board.cache_hierarchy.l1dcaches.prefetcher
replace_expansions=true
replacement_policy=board.cache_hierarchy.l1dcaches.replacement_policy
response_latency=1
sequential_access=false
size=16384
system=board
tag_latency=1
tags=board.cache_hierarchy.l1dcaches.tags
tgts_per_mshr=20
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=false
cpu_side=board.processor.cores.core.dcache_port
mem_side=board.cache_hierarchy.l2bus.cpu_side_ports[1]

[board.cache_hierarchy.l1dcaches.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1dcaches.prefetcher]
type=StridePrefetcher
children=power_state table_indexing_policy table_replacement_policy
block_size=64
cache_snoop=false
clk_domain=board.clk_domain
confidence_counter_bits=3
confidence_threshold=50
degree=4
distance=0
eventq_index=0
initial_confidence=4
latency=1
max_prefetch_requests_with_pending_translation=32
on_data=true
on_inst=false
on_miss=false
on_read=true
on_write=true
page_bytes=4096
power_model=
power_state=board.cache_hierarchy.l1dcaches.prefetcher.power_state
prefetch_on_access=false
prefetch_on_pf_hit=true
queue_filter=true
queue_size=32
queue_squash=true
sys=board
table_assoc=4
table_entries=64
table_indexing_policy=board.cache_hierarchy.l1dcaches.prefetcher.table_indexing_policy
table_replacement_policy=board.cache_hierarchy.l1dcaches.prefetcher.table_replacement_policy
tag_prefetch=true
throttle_control_percentage=0
use_cache_line_address=true
use_requestor_id=true
use_virtual_addresses=false

[board.cache_hierarchy.l1dcaches.prefetcher.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1dcaches.prefetcher.table_indexing_policy]
type=StridePrefetcherHashedSetAssociative
assoc=4
entry_size=1
eventq_index=0
size=64

[board.cache_hierarchy.l1dcaches.prefetcher.table_replacement_policy]
type=RandomRP
eventq_index=0

[board.cache_hierarchy.l1dcaches.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.l1dcaches.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=8
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.l1dcaches.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1dcaches.tags.power_state
replacement_policy=board.cache_hierarchy.l1dcaches.replacement_policy
sequential_access=false
size=16384
system=board
tag_latency=1
warmup_percentage=0

[board.cache_hierarchy.l1dcaches.tags.indexing_policy]
type=TaggedSetAssociative
assoc=8
entry_size=64
eventq_index=0
size=16384

[board.cache_hierarchy.l1dcaches.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1icaches]
type=Cache
children=power_state prefetcher replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=16
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1icaches.power_state
prefetcher=board.cache_hierarchy.l1icaches.prefetcher
replace_expansions=true
replacement_policy=board.cache_hierarchy.l1icaches.replacement_policy
response_latency=1
sequential_access=false
size=16384
system=board
tag_latency=1
tags=board.cache_hierarchy.l1icaches.tags
tgts_per_mshr=20
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=false
cpu_side=board.processor.cores.core.icache_port
mem_side=board.cache_hierarchy.l2bus.cpu_side_ports[0]

[board.cache_hierarchy.l1icaches.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1icaches.prefetcher]
type=StridePrefetcher
children=power_state table_indexing_policy table_replacement_policy
block_size=64
cache_snoop=false
clk_domain=board.clk_domain
confidence_counter_bits=3
confidence_threshold=50
degree=4
distance=0
eventq_index=0
initial_confidence=4
latency=1
max_prefetch_requests_with_pending_translation=32
on_data=true
on_inst=false
on_miss=false
on_read=true
on_write=true
page_bytes=4096
power_model=
power_state=board.cache_hierarchy.l1icaches.prefetcher.power_state
prefetch_on_access=false
prefetch_on_pf_hit=true
queue_filter=true
queue_size=32
queue_squash=true
sys=board
table_assoc=4
table_entries=64
table_indexing_policy=board.cache_hierarchy.l1icaches.prefetcher.table_indexing_policy
table_replacement_policy=board.cache_hierarchy.l1icaches.prefetcher.table_replacement_policy
tag_prefetch=true
throttle_control_percentage=0
use_cache_line_address=true
use_requestor_id=true
use_virtual_addresses=false

[board.cache_hierarchy.l1icaches.prefetcher.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1icaches.prefetcher.table_indexing_policy]
type=StridePrefetcherHashedSetAssociative
assoc=4
entry_size=1
eventq_index=0
size=64

[board.cache_hierarchy.l1icaches.prefetcher.table_replacement_policy]
type=RandomRP
eventq_index=0

[board.cache_hierarchy.l1icaches.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.l1icaches.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=8
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.l1icaches.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1icaches.tags.power_state
replacement_policy=board.cache_hierarchy.l1icaches.replacement_policy
sequential_access=false
size=16384
system=board
tag_latency=1
warmup_percentage=0

[board.cache_hierarchy.l1icaches.tags.indexing_policy]
type=TaggedSetAssociative
assoc=8
entry_size=64
eventq_index=0
size=16384

[board.cache_hierarchy.l1icaches.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l2bus]
type=CoherentXBar
children=power_state snoop_filter
clk_domain=board.clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
header_latency=1
max_outstanding_snoops=512
max_routing_table_size=512
point_of_coherency=false
point_of_unification=true
power_model=
power_state=board.cache_hierarchy.l2bus.power_state
response_latency=1
snoop_filter=board.cache_hierarchy.l2bus.snoop_filter
snoop_response_latency=1
system=board
use_default_range=false
width=32
cpu_side_ports=board.cache_hierarchy.l1icaches.mem_side board.cache_hierarchy.l1dcaches.mem_side board.cache_hierarchy.iptw_caches.mem_side board.cache_hierarchy.dptw_caches.mem_side
mem_side_ports=board.cache_hierarchy.l2cache.cpu_side

[board.cache_hierarchy.l2bus.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l2bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=board

[board.cache_hierarchy.l2cache]
type=Cache
children=power_state prefetcher replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=10
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=20
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l2cache.power_state
prefetcher=board.cache_hierarchy.l2cache.prefetcher
replace_expansions=true
replacement_policy=board.cache_hierarchy.l2cache.replacement_policy
response_latency=1
sequential_access=false
size=262144
system=board
tag_latency=10
tags=board.cache_hierarchy.l2cache.tags
tgts_per_mshr=12
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=false
cpu_side=board.cache_hierarchy.l2bus.mem_side_ports[0]
mem_side=board.cache_hierarchy.membus.cpu_side_ports[2]

[board.cache_hierarchy.l2cache.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l2cache.prefetcher]
type=StridePrefetcher
children=power_state table_indexing_policy table_replacement_policy
block_size=64
cache_snoop=false
clk_domain=board.clk_domain
confidence_counter_bits=3
confidence_threshold=50
degree=4
distance=0
eventq_index=0
initial_confidence=4
latency=1
max_prefetch_requests_with_pending_translation=32
on_data=true
on_inst=false
on_miss=false
on_read=true
on_write=true
page_bytes=4096
power_model=
power_state=board.cache_hierarchy.l2cache.prefetcher.power_state
prefetch_on_access=false
prefetch_on_pf_hit=true
queue_filter=true
queue_size=32
queue_squash=true
sys=board
table_assoc=4
table_entries=64
table_indexing_policy=board.cache_hierarchy.l2cache.prefetcher.table_indexing_policy
table_replacement_policy=board.cache_hierarchy.l2cache.prefetcher.table_replacement_policy
tag_prefetch=true
throttle_control_percentage=0
use_cache_line_address=true
use_requestor_id=true
use_virtual_addresses=false

[board.cache_hierarchy.l2cache.prefetcher.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l2cache.prefetcher.table_indexing_policy]
type=StridePrefetcherHashedSetAssociative
assoc=4
entry_size=1
eventq_index=0
size=64

[board.cache_hierarchy.l2cache.prefetcher.table_replacement_policy]
type=RandomRP
eventq_index=0

[board.cache_hierarchy.l2cache.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.l2cache.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=16
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.l2cache.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l2cache.tags.power_state
replacement_policy=board.cache_hierarchy.l2cache.replacement_policy
sequential_access=false
size=262144
system=board
tag_latency=10
warmup_percentage=0

[board.cache_hierarchy.l2cache.tags.indexing_policy]
type=TaggedSetAssociative
assoc=16
entry_size=64
eventq_index=0
size=262144

[board.cache_hierarchy.l2cache.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.membus]
type=CoherentXBar
children=badaddr_responder power_state snoop_filter
clk_domain=board.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
header_latency=1
max_outstanding_snoops=512
max_routing_table_size=512
point_of_coherency=true
point_of_unification=true
power_model=
power_state=board.cache_hierarchy.membus.power_state
response_latency=2
snoop_filter=board.cache_hierarchy.membus.snoop_filter
snoop_response_latency=4
system=board
use_default_range=false
width=64
cpu_side_ports=board.system_port board.processor.cores.core.interrupts.int_requestor board.cache_hierarchy.l2cache.mem_side
default=board.cache_hierarchy.membus.badaddr_responder.pio
mem_side_ports=board.memory.mem_ctrl.port board.processor.cores.core.interrupts.pio board.processor.cores.core.interrupts.int_responder

[board.cache_hierarchy.membus.badaddr_responder]
type=IsaFake
children=power_state
clk_domain=board.clk_domain
eventq_index=0
fake_mem=false
pio_addr=0
pio_latency=100000
pio_size=8
power_model=
power_state=board.cache_hierarchy.membus.badaddr_responder.power_state
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=board
update_data=false
warn_access=
pio=board.cache_hierarchy.membus.default

[board.cache_hierarchy.membus.badaddr_responder.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.membus.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=board

[board.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=333
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=board.clk_domain.voltage_domain

[board.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0

[board.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=board.clk_domain
transition_latency=100000000

[board.memory]
type=SubSystem
children=mem_ctrl
eventq_index=0
thermal_domain=Null

[board.memory.mem_ctrl]
type=MemCtrl
children=dram power_state
clk_domain=board.clk_domain
command_window=10000
disable_sanity_check=false
dram=board.memory.mem_ctrl.dram
eventq_index=0
mem_sched_policy=frfcfs
min_reads_per_switch=16
min_writes_per_switch=16
power_model=
power_state=board.memory.mem_ctrl.power_state
qos_policy=Null
qos_priorities=1
qos_priority_escalation=false
qos_q_policy=fifo
qos_requestors=               
qos_syncro_scheduler=false
qos_turnaround_policy=Null
static_backend_latency=10000
static_frontend_latency=10000
system=board
write_high_thresh_perc=85
write_low_thresh_perc=50
port=board.cache_hierarchy.membus.mem_side_ports[0]

[board.memory.mem_ctrl.dram]
type=DRAMInterface
children=power_state
IDD0=0.048
IDD02=0.003
IDD2N=0.034
IDD2N2=0.0
IDD2P0=0.0
IDD2P02=0.0
IDD2P1=0.025
IDD2P12=0.0
IDD3N=0.043000000000000003
IDD3N2=0.003
IDD3P0=0.0
IDD3P02=0.0
IDD3P1=0.037
IDD3P12=0.0
IDD4R=0.135
IDD4R2=0.0
IDD4W=0.123
IDD4W2=0.0
IDD5=0.25
IDD52=0.0
IDD6=0.03
IDD62=0.0
VDD=1.2
VDD2=2.5
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=4
banks_per_rank=16
beats_per_clock=2
burst_length=8
clk_domain=board.clk_domain
collect_stats=true
conf_table_reported=true
data_clock_sync=false
device_bus_width=8
device_rowbuffer_size=1024
device_size=1073741824
devices_per_rank=8
dll=true
enable_dram_powerdown=false
eventq_index=0
image_file=
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
null=false
page_policy=open_adaptive
power_model=
power_state=board.memory.mem_ctrl.dram.power_state
range=0:3221225472
ranks_per_channel=2
read_buffer_size=64
tAAD=833
tBURST=3332
tBURST_MAX=3332
tBURST_MIN=3332
tCCD_L=5000
tCCD_L_WR=5000
tCK=833
tCL=14160
tCS=1666
tCWL=14160
tPPD=0
tRAS=32000
tRCD=14160
tRCD_WR=14160
tREFI=7800000
tRFC=350000
tRP=14160
tRRD=3332
tRRD_L=4900
tRTP=7500
tRTW=1666
tWR=15000
tWTR=5000
tWTR_L=5000
tXAW=21000
tXP=6000
tXPDLL=0
tXS=340000
tXSDLL=0
two_cycle_activate=false
write_buffer_size=128
writeable=true

[board.memory.mem_ctrl.dram.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.memory.mem_ctrl.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.processor]
type=SubSystem
children=cores
eventq_index=0
thermal_domain=Null

[board.processor.cores]
type=SubSystem
children=core
eventq_index=0
thermal_domain=Null

[board.processor.cores.core]
type=BaseO3CPU
children=SSITIndexingPolicy SSITReplPolicy branchPred decoder fuPool interrupts isa mmu power_state tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITAssoc=1
SSITIndexingPolicy=board.processor.cores.core.SSITIndexingPolicy
SSITReplPolicy=board.processor.cores.core.SSITReplPolicy
SSITSize=1024
activity=0
backComSize=5
branchPred=board.processor.cores.core.branchPred
cacheLoadPorts=200
cacheStorePorts=200
checker=Null
clk_domain=board.clk_domain
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=2
cpu_id=-1
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=2
decoder=board.processor.cores.core.decoder
dispatchWidth=2
do_checkpoint_insts=true
do_statistics_insts=true
eventq_index=0
fetchBufferSize=64
fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=2
forwardComSize=5
fuPool=board.processor.cores.core.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=board.processor.cores.core.interrupts
isa=board.processor.cores.core.isa
issueToExecuteDelay=1
issueWidth=2
max_insts_all_threads=0
max_insts_any_thread=0
mmu=board.processor.cores.core.mmu
needsTSO=true
numIQEntries=64
numPhysCCRegs=400
numPhysFloatRegs=80
numPhysIntRegs=80
numPhysMatRegs=2
numPhysVecPredRegs=32
numPhysVecRegs=256
numROBEntries=30
numRobs=1
numThreads=1
power_gating_on_idle=false
power_model=
power_state=board.processor.cores.core.power_state
progress_interval=0
pwr_gating_latency=300
recvRespBufferSize=64
recvRespMaxCachelines=1
recvRespThrottling=false
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=2
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=RoundRobin
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
syscallRetryLatency=10000
system=board
tracer=board.processor.cores.core.tracer
trapLatency=13
wbWidth=2
workload=board.processor.cores.core.workload
dcache_port=board.cache_hierarchy.l1dcaches.cpu_side
icache_port=board.cache_hierarchy.l1icaches.cpu_side

[board.processor.cores.core.SSITIndexingPolicy]
type=SetAssociative
assoc=1
entry_size=4
eventq_index=0
size=4096

[board.processor.cores.core.SSITReplPolicy]
type=LRURP
eventq_index=0

[board.processor.cores.core.branchPred]
type=TournamentBP
children=btb indirectBranchPred ras
btb=board.processor.cores.core.branchPred.btb
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectBranchPred=board.processor.cores.core.branchPred.indirectBranchPred
instShiftAmt=0
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
ras=board.processor.cores.core.branchPred.ras
requiresBTBHit=false
speculativeHistUpdate=true
takenOnlyHistory=false

[board.processor.cores.core.branchPred.btb]
type=SimpleBTB
children=btbIndexingPolicy btbReplPolicy power_state
associativity=1
btbIndexingPolicy=board.processor.cores.core.branchPred.btb.btbIndexingPolicy
btbReplPolicy=board.processor.cores.core.branchPred.btb.btbReplPolicy
clk_domain=board.clk_domain
eventq_index=0
instShiftAmt=0
numEntries=4096
numThreads=1
power_model=
power_state=board.processor.cores.core.branchPred.btb.power_state
tagBits=16

[board.processor.cores.core.branchPred.btb.btbIndexingPolicy]
type=BTBSetAssociative
assoc=1
eventq_index=0
numThreads=1
num_entries=4096
set_shift=0
tag_bits=64

[board.processor.cores.core.branchPred.btb.btbReplPolicy]
type=LRURP
eventq_index=0

[board.processor.cores.core.branchPred.btb.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.processor.cores.core.branchPred.indirectBranchPred]
type=SimpleIndirectPredictor
eventq_index=0
indirectGHRBits=13
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=0
numThreads=1
speculativePathLength=256

[board.processor.cores.core.branchPred.ras]
type=ReturnAddrStack
eventq_index=0
numEntries=16
numThreads=1

[board.processor.cores.core.decoder]
type=X86Decoder
eventq_index=0
isa=board.processor.cores.core.isa

[board.processor.cores.core.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList9
FUList=board.processor.cores.core.fuPool.FUList0 board.processor.cores.core.fuPool.FUList1 board.processor.cores.core.fuPool.FUList2 board.processor.cores.core.fuPool.FUList3 board.processor.cores.core.fuPool.FUList4 board.processor.cores.core.fuPool.FUList5 board.processor.cores.core.fuPool.FUList6 board.processor.cores.core.fuPool.FUList7 board.processor.cores.core.fuPool.FUList8 board.processor.cores.core.fuPool.FUList9
eventq_index=0

[board.processor.cores.core.fuPool.FUList0]
type=FUDesc
children=opList
count=6
eventq_index=0
opList=board.processor.cores.core.fuPool.FUList0.opList

[board.processor.cores.core.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
opClass=IntAlu
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
eventq_index=0
opList=board.processor.cores.core.fuPool.FUList1.opList0 board.processor.cores.core.fuPool.FUList1.opList1

[board.processor.cores.core.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
opClass=IntMult
opLat=3
pipelined=true

[board.processor.cores.core.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
opClass=IntDiv
opLat=1
pipelined=false

[board.processor.cores.core.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
eventq_index=0
opList=board.processor.cores.core.fuPool.FUList2.opList0 board.processor.cores.core.fuPool.FUList2.opList1 board.processor.cores.core.fuPool.FUList2.opList2

[board.processor.cores.core.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=FloatAdd
opLat=2
pipelined=true

[board.processor.cores.core.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
opClass=FloatCmp
opLat=2
pipelined=true

[board.processor.cores.core.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
opClass=FloatCvt
opLat=2
pipelined=true

[board.processor.cores.core.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2 opList3 opList4
count=2
eventq_index=0
opList=board.processor.cores.core.fuPool.FUList3.opList0 board.processor.cores.core.fuPool.FUList3.opList1 board.processor.cores.core.fuPool.FUList3.opList2 board.processor.cores.core.fuPool.FUList3.opList3 board.processor.cores.core.fuPool.FUList3.opList4

[board.processor.cores.core.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=FloatMult
opLat=4
pipelined=true

[board.processor.cores.core.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMultAcc
opLat=5
pipelined=true

[board.processor.cores.core.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
opClass=FloatMisc
opLat=3
pipelined=true

[board.processor.cores.core.fuPool.FUList3.opList3]
type=OpDesc
eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false

[board.processor.cores.core.fuPool.FUList3.opList4]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
opLat=24
pipelined=false

[board.processor.cores.core.fuPool.FUList4]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10
count=0
eventq_index=0
opList=board.processor.cores.core.fuPool.FUList4.opList00 board.processor.cores.core.fuPool.FUList4.opList01 board.processor.cores.core.fuPool.FUList4.opList02 board.processor.cores.core.fuPool.FUList4.opList03 board.processor.cores.core.fuPool.FUList4.opList04 board.processor.cores.core.fuPool.FUList4.opList05 board.processor.cores.core.fuPool.FUList4.opList06 board.processor.cores.core.fuPool.FUList4.opList07 board.processor.cores.core.fuPool.FUList4.opList08 board.processor.cores.core.fuPool.FUList4.opList09 board.processor.cores.core.fuPool.FUList4.opList10

[board.processor.cores.core.fuPool.FUList4.opList00]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList4.opList01]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList4.opList02]
type=OpDesc
eventq_index=0
opClass=SimdUnitStrideLoad
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList4.opList03]
type=OpDesc
eventq_index=0
opClass=SimdUnitStrideMaskLoad
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList4.opList04]
type=OpDesc
eventq_index=0
opClass=SimdUnitStrideSegmentedLoad
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList4.opList05]
type=OpDesc
eventq_index=0
opClass=SimdStridedLoad
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList4.opList06]
type=OpDesc
eventq_index=0
opClass=SimdIndexedLoad
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList4.opList07]
type=OpDesc
eventq_index=0
opClass=SimdUnitStrideFaultOnlyFirstLoad
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList4.opList08]
type=OpDesc
eventq_index=0
opClass=SimdUnitStrideSegmentedFaultOnlyFirstLoad
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList4.opList09]
type=OpDesc
eventq_index=0
opClass=SimdWholeRegisterLoad
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList4.opList10]
type=OpDesc
eventq_index=0
opClass=SimdStrideSegmentedLoad
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 opList28 opList29 opList30 opList31 opList32 opList33 opList34 opList35 opList36 opList37 opList38
count=4
eventq_index=0
opList=board.processor.cores.core.fuPool.FUList5.opList00 board.processor.cores.core.fuPool.FUList5.opList01 board.processor.cores.core.fuPool.FUList5.opList02 board.processor.cores.core.fuPool.FUList5.opList03 board.processor.cores.core.fuPool.FUList5.opList04 board.processor.cores.core.fuPool.FUList5.opList05 board.processor.cores.core.fuPool.FUList5.opList06 board.processor.cores.core.fuPool.FUList5.opList07 board.processor.cores.core.fuPool.FUList5.opList08 board.processor.cores.core.fuPool.FUList5.opList09 board.processor.cores.core.fuPool.FUList5.opList10 board.processor.cores.core.fuPool.FUList5.opList11 board.processor.cores.core.fuPool.FUList5.opList12 board.processor.cores.core.fuPool.FUList5.opList13 board.processor.cores.core.fuPool.FUList5.opList14 board.processor.cores.core.fuPool.FUList5.opList15 board.processor.cores.core.fuPool.FUList5.opList16 board.processor.cores.core.fuPool.FUList5.opList17 board.processor.cores.core.fuPool.FUList5.opList18 board.processor.cores.core.fuPool.FUList5.opList19 board.processor.cores.core.fuPool.FUList5.opList20 board.processor.cores.core.fuPool.FUList5.opList21 board.processor.cores.core.fuPool.FUList5.opList22 board.processor.cores.core.fuPool.FUList5.opList23 board.processor.cores.core.fuPool.FUList5.opList24 board.processor.cores.core.fuPool.FUList5.opList25 board.processor.cores.core.fuPool.FUList5.opList26 board.processor.cores.core.fuPool.FUList5.opList27 board.processor.cores.core.fuPool.FUList5.opList28 board.processor.cores.core.fuPool.FUList5.opList29 board.processor.cores.core.fuPool.FUList5.opList30 board.processor.cores.core.fuPool.FUList5.opList31 board.processor.cores.core.fuPool.FUList5.opList32 board.processor.cores.core.fuPool.FUList5.opList33 board.processor.cores.core.fuPool.FUList5.opList34 board.processor.cores.core.fuPool.FUList5.opList35 board.processor.cores.core.fuPool.FUList5.opList36 board.processor.cores.core.fuPool.FUList5.opList37 board.processor.cores.core.fuPool.FUList5.opList38

[board.processor.cores.core.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
opClass=SimdAdd
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
opClass=SimdAddAcc
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
opClass=SimdAlu
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
opClass=SimdCmp
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
opClass=SimdCvt
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
opClass=SimdMisc
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
opClass=SimdMult
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
opClass=SimdMultAcc
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
opClass=SimdMatMultAcc
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
opClass=SimdShift
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
opClass=SimdShiftAcc
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
opClass=SimdDiv
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
opClass=SimdSqrt
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
opClass=SimdFloatAdd
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
opClass=SimdFloatAlu
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
opClass=SimdFloatCmp
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
opClass=SimdFloatCvt
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
opClass=SimdFloatDiv
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
opClass=SimdFloatMisc
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
opClass=SimdFloatMult
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList20]
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList21]
type=OpDesc
eventq_index=0
opClass=SimdFloatMatMultAcc
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList22]
type=OpDesc
eventq_index=0
opClass=SimdFloatSqrt
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList23]
type=OpDesc
eventq_index=0
opClass=SimdReduceAdd
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList24]
type=OpDesc
eventq_index=0
opClass=SimdReduceAlu
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList25]
type=OpDesc
eventq_index=0
opClass=SimdReduceCmp
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList26]
type=OpDesc
eventq_index=0
opClass=SimdFloatReduceAdd
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList27]
type=OpDesc
eventq_index=0
opClass=SimdFloatReduceCmp
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList28]
type=OpDesc
eventq_index=0
opClass=SimdExt
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList29]
type=OpDesc
eventq_index=0
opClass=SimdFloatExt
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList30]
type=OpDesc
eventq_index=0
opClass=SimdConfig
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList31]
type=OpDesc
eventq_index=0
opClass=SimdAes
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList32]
type=OpDesc
eventq_index=0
opClass=SimdAesMix
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList33]
type=OpDesc
eventq_index=0
opClass=SimdSha1Hash
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList34]
type=OpDesc
eventq_index=0
opClass=SimdSha1Hash2
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList35]
type=OpDesc
eventq_index=0
opClass=SimdSha256Hash
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList36]
type=OpDesc
eventq_index=0
opClass=SimdSha256Hash2
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList37]
type=OpDesc
eventq_index=0
opClass=SimdShaSigma2
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList5.opList38]
type=OpDesc
eventq_index=0
opClass=SimdShaSigma3
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList6]
type=FUDesc
children=opList
count=1
eventq_index=0
opList=board.processor.cores.core.fuPool.FUList6.opList

[board.processor.cores.core.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
opClass=SimdPredAlu
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList7]
type=FUDesc
children=opList0 opList1 opList2 opList3 opList4 opList5 opList6 opList7 opList8
count=0
eventq_index=0
opList=board.processor.cores.core.fuPool.FUList7.opList0 board.processor.cores.core.fuPool.FUList7.opList1 board.processor.cores.core.fuPool.FUList7.opList2 board.processor.cores.core.fuPool.FUList7.opList3 board.processor.cores.core.fuPool.FUList7.opList4 board.processor.cores.core.fuPool.FUList7.opList5 board.processor.cores.core.fuPool.FUList7.opList6 board.processor.cores.core.fuPool.FUList7.opList7 board.processor.cores.core.fuPool.FUList7.opList8

[board.processor.cores.core.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList7.opList2]
type=OpDesc
eventq_index=0
opClass=SimdUnitStrideStore
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList7.opList3]
type=OpDesc
eventq_index=0
opClass=SimdUnitStrideMaskStore
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList7.opList4]
type=OpDesc
eventq_index=0
opClass=SimdUnitStrideSegmentedStore
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList7.opList5]
type=OpDesc
eventq_index=0
opClass=SimdStridedStore
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList7.opList6]
type=OpDesc
eventq_index=0
opClass=SimdIndexedStore
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList7.opList7]
type=OpDesc
eventq_index=0
opClass=SimdWholeRegisterStore
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList7.opList8]
type=OpDesc
eventq_index=0
opClass=SimdStrideSegmentedStore
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList8]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
eventq_index=0
opList=board.processor.cores.core.fuPool.FUList8.opList00 board.processor.cores.core.fuPool.FUList8.opList01 board.processor.cores.core.fuPool.FUList8.opList02 board.processor.cores.core.fuPool.FUList8.opList03 board.processor.cores.core.fuPool.FUList8.opList04 board.processor.cores.core.fuPool.FUList8.opList05 board.processor.cores.core.fuPool.FUList8.opList06 board.processor.cores.core.fuPool.FUList8.opList07 board.processor.cores.core.fuPool.FUList8.opList08 board.processor.cores.core.fuPool.FUList8.opList09 board.processor.cores.core.fuPool.FUList8.opList10 board.processor.cores.core.fuPool.FUList8.opList11 board.processor.cores.core.fuPool.FUList8.opList12 board.processor.cores.core.fuPool.FUList8.opList13 board.processor.cores.core.fuPool.FUList8.opList14 board.processor.cores.core.fuPool.FUList8.opList15 board.processor.cores.core.fuPool.FUList8.opList16 board.processor.cores.core.fuPool.FUList8.opList17 board.processor.cores.core.fuPool.FUList8.opList18 board.processor.cores.core.fuPool.FUList8.opList19

[board.processor.cores.core.fuPool.FUList8.opList00]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList8.opList01]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList8.opList02]
type=OpDesc
eventq_index=0
opClass=FloatMemRead
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList8.opList03]
type=OpDesc
eventq_index=0
opClass=FloatMemWrite
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList8.opList04]
type=OpDesc
eventq_index=0
opClass=SimdUnitStrideLoad
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList8.opList05]
type=OpDesc
eventq_index=0
opClass=SimdUnitStrideStore
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList8.opList06]
type=OpDesc
eventq_index=0
opClass=SimdUnitStrideMaskLoad
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList8.opList07]
type=OpDesc
eventq_index=0
opClass=SimdUnitStrideMaskStore
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList8.opList08]
type=OpDesc
eventq_index=0
opClass=SimdUnitStrideSegmentedLoad
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList8.opList09]
type=OpDesc
eventq_index=0
opClass=SimdUnitStrideSegmentedStore
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList8.opList10]
type=OpDesc
eventq_index=0
opClass=SimdStridedLoad
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList8.opList11]
type=OpDesc
eventq_index=0
opClass=SimdStridedStore
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList8.opList12]
type=OpDesc
eventq_index=0
opClass=SimdIndexedLoad
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList8.opList13]
type=OpDesc
eventq_index=0
opClass=SimdIndexedStore
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList8.opList14]
type=OpDesc
eventq_index=0
opClass=SimdUnitStrideFaultOnlyFirstLoad
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList8.opList15]
type=OpDesc
eventq_index=0
opClass=SimdUnitStrideSegmentedFaultOnlyFirstLoad
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList8.opList16]
type=OpDesc
eventq_index=0
opClass=SimdWholeRegisterLoad
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList8.opList17]
type=OpDesc
eventq_index=0
opClass=SimdWholeRegisterStore
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList8.opList18]
type=OpDesc
eventq_index=0
opClass=SimdStrideSegmentedLoad
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList8.opList19]
type=OpDesc
eventq_index=0
opClass=SimdStrideSegmentedStore
opLat=1
pipelined=true

[board.processor.cores.core.fuPool.FUList9]
type=FUDesc
children=opList
count=1
eventq_index=0
opList=board.processor.cores.core.fuPool.FUList9.opList

[board.processor.cores.core.fuPool.FUList9.opList]
type=OpDesc
eventq_index=0
opClass=IprAccess
opLat=3
pipelined=false

[board.processor.cores.core.interrupts]
type=X86LocalApic
children=clk_domain
clk_domain=board.processor.cores.core.interrupts.clk_domain
eventq_index=0
int_latency=1000
pio_latency=100000
system=board
int_requestor=board.cache_hierarchy.membus.cpu_side_ports[1]
int_responder=board.cache_hierarchy.membus.mem_side_ports[2]
pio=board.cache_hierarchy.membus.mem_side_ports[1]

[board.processor.cores.core.interrupts.clk_domain]
type=DerivedClockDomain
clk_divider=16
clk_domain=board.clk_domain
eventq_index=0

[board.processor.cores.core.isa]
type=X86ISA
APMInfo=2147483672 1752462657 1769238117 1145913699
CacheParams=0 0 0 0
ExtendedFeatures=0 25165824 0 0
ExtendedState=0 0 0 0 0 0 0 0
FamilyModelStepping=134993 2053 4024171519 521
FamilyModelSteppingBrandFeatures=134993 1029 3956538367 131073
L1CacheAndTLB=4278779656 4280352544 1073873216 1073873216
L2L3CacheAndL2TLB=0 1107313152 0 67141952
LongModeAddressSize=12336 0 0 0
eventq_index=0
name_string=Fake gem5 x86_64 CPU
vendor_string=HygonGenuine

[board.processor.cores.core.mmu]
type=X86MMU
children=dtb itb
dtb=board.processor.cores.core.mmu.dtb
eventq_index=0
itb=board.processor.cores.core.mmu.itb

[board.processor.cores.core.mmu.dtb]
type=X86TLB
children=walker
entry_type=data
eventq_index=0
next_level=Null
size=64
system=board
walker=board.processor.cores.core.mmu.dtb.walker

[board.processor.cores.core.mmu.dtb.walker]
type=X86PagetableWalker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
num_squash_per_cycle=4
power_model=
power_state=board.processor.cores.core.mmu.dtb.walker.power_state
system=board
port=board.cache_hierarchy.dptw_caches.cpu_side

[board.processor.cores.core.mmu.dtb.walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.processor.cores.core.mmu.itb]
type=X86TLB
children=walker
entry_type=instruction
eventq_index=0
next_level=Null
size=64
system=board
walker=board.processor.cores.core.mmu.itb.walker

[board.processor.cores.core.mmu.itb.walker]
type=X86PagetableWalker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
num_squash_per_cycle=4
power_model=
power_state=board.processor.cores.core.mmu.itb.walker.power_state
system=board
port=board.cache_hierarchy.iptw_caches.cpu_side

[board.processor.cores.core.mmu.itb.walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.processor.cores.core.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=ON CLK_GATED OFF

[board.processor.cores.core.tracer]
type=ExeTracer
children=disassembler
disassembler=board.processor.cores.core.tracer.disassembler
eventq_index=0

[board.processor.cores.core.tracer.disassembler]
type=InstDisassembler
eventq_index=0

[board.processor.cores.core.workload]
type=Process
cmd=gem5/x86-matrix-multiply
cwd=learn-you-a-gem5
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=gem5/x86-matrix-multiply
gid=100
input=cin
kvmInSE=false
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=0
release=5.1.0
simpoint=0
system=board
uid=100
useArchPT=false
zeroPages=true

[board.workload]
type=X86EmuLinux
eventq_index=0
remote_gdb_port=#7000
wait_for_remote_gdb=false

[root]
type=Root
children=board
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000