---------- Begin Simulation Statistics ----------
simSeconds 17.010966 # Number of seconds simulated (Second)
simTicks 17010966056950 # Number of ticks simulated (Tick)
finalTick 17010966056950 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 18.98 # Real time elapsed on the host (Second)
hostTickRate 896030072504 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3711724 # Number of bytes of host memory used (Byte)
simInsts 19570309527 # Number of instructions simulated (Count)
simOps 19570309527 # Number of ops (including micro ops) simulated (Count)
hostInstRate 1030832493 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 1030832330 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.apicbridge.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.bridge.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iocache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iocache.blockedCycles::no_wbuffers 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iocache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iocache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iocache.blockedCauses::no_wbuffers 0 # number of times access was blocked (Count)
board.cache_hierarchy.iocache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iocache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iocache.avgBlocked::no_wbuffers nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iocache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iocache.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iocache.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iocache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iocache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iocache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iocache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iocache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iocache.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iocache.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iocache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches0.blockedCycles::no_wbuffers 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches0.blockedCauses::no_wbuffers 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches0.avgBlocked::no_wbuffers nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1dcaches0.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches0.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches1.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches1.blockedCycles::no_wbuffers 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches1.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches1.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches1.blockedCauses::no_wbuffers 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches1.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches1.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches1.avgBlocked::no_wbuffers nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches1.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches1.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1dcaches1.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches1.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches1.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches1.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches1.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches1.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches1.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches1.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches1.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches1.tags.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches0.blockedCycles::no_wbuffers 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches0.blockedCauses::no_wbuffers 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches0.avgBlocked::no_wbuffers nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1icaches0.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches0.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches0.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches0.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches1.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches1.blockedCycles::no_wbuffers 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches1.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches1.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches1.blockedCauses::no_wbuffers 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches1.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches1.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches1.avgBlocked::no_wbuffers nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches1.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches1.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l1icaches1.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches1.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches1.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches1.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches1.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches1.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches1.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches1.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches1.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches1.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches1.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches1.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches1.tags.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.transDist::ReadReq 234664 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadResp 234664 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WriteReq 2175289 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WriteResp 2175289 # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.apicbridge.mem_side_port::board.processor.start0.core.interrupts.int_responder 63338 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.apicbridge.mem_side_port::board.processor.start1.core.interrupts.int_responder 6776 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.apicbridge.mem_side_port::total 70114 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.iocache.mem_side_port::board.memory.mem_ctrl0.port 2028474 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.iocache.mem_side_port::board.memory.mem_ctrl1.port 2016570 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.iocache.mem_side_port::total 4045044 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches0.mem_side_port::board.bridge.cpu_side_port 275788 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches0.mem_side_port::board.processor.start0.core.interrupts.pio 171618 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches0.mem_side_port::total 447406 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.processor.start0.core.interrupts.int_requestor::board.processor.start1.core.interrupts.int_responder 35388 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.processor.start0.core.interrupts.int_requestor::total 35388 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches1.mem_side_port::board.bridge.cpu_side_port 173770 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches1.mem_side_port::board.processor.start1.core.interrupts.pio 46654 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches1.mem_side_port::total 220424 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.processor.start1.core.interrupts.int_requestor::board.processor.start0.core.interrupts.int_responder 1530 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.processor.start1.core.interrupts.int_requestor::total 1530 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total 4819906 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.apicbridge.mem_side_port::board.processor.start0.core.interrupts.int_responder 126676 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.apicbridge.mem_side_port::board.processor.start1.core.interrupts.int_responder 13552 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.apicbridge.mem_side_port::total 140228 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.iocache.mem_side_port::board.memory.mem_ctrl0.port 64376872 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.iocache.mem_side_port::board.memory.mem_ctrl1.port 64329256 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.iocache.mem_side_port::total 128706128 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches0.mem_side_port::board.bridge.cpu_side_port 145180 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches0.mem_side_port::board.processor.start0.core.interrupts.pio 343236 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches0.mem_side_port::total 488416 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.processor.start0.core.interrupts.int_requestor::board.processor.start1.core.interrupts.int_responder 70776 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.processor.start0.core.interrupts.int_requestor::total 70776 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches1.mem_side_port::board.bridge.cpu_side_port 91908 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches1.mem_side_port::board.processor.start1.core.interrupts.pio 93308 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches1.mem_side_port::total 185216 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.processor.start1.core.interrupts.int_requestor::board.processor.start0.core.interrupts.int_responder 3060 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.processor.start1.core.interrupts.int_requestor::total 3060 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total 129593824 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev nan # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::2 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::3 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::4 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::5 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 0 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.iobus.transDist::ReadReq 215934 # Transaction distribution (Count)
board.iobus.transDist::ReadResp 215934 # Transaction distribution (Count)
board.iobus.transDist::WriteReq 2066424 # Transaction distribution (Count)
board.iobus.transDist::WriteResp 2066424 # Transaction distribution (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.south_bridge.cmos.pio 348 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.south_bridge.keyboard.pio 1880 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.south_bridge.pic1.pio 54 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.south_bridge.pic2.pio 58 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.south_bridge.pit.pio 150 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.south_bridge.speaker.pio 10522 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.south_bridge.io_apic.pio 966 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.com_1.pio 266184 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.fake_com_2.pio 12 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.fake_com_3.pio 12 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.fake_com_4.pio 12 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.pci_host.up_to_down.cpu_side_port 169194 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.default_bus.cpu_side_ports[0] 166 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::total 449558 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.pc.south_bridge.io_apic.int_request::board.apicbridge.cpu_side_port 70114 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.pc.south_bridge.io_apic.int_request::total 70114 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.pc.pci_host.down_to_up.mem_side_port::board.cache_hierarchy.iocache.cpu_side_port 4045044 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.pc.pci_host.down_to_up.mem_side_port::total 4045044 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount::total 4564716 # Packet count per connected requestor and responder (Count)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.south_bridge.cmos.pio 174 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.south_bridge.keyboard.pio 940 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.south_bridge.pic1.pio 27 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.south_bridge.pic2.pio 29 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.south_bridge.pit.pio 75 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.south_bridge.speaker.pio 5261 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.south_bridge.io_apic.pio 1932 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.com_1.pio 133092 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.fake_com_2.pio 6 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.fake_com_3.pio 6 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.fake_com_4.pio 6 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.pci_host.up_to_down.cpu_side_port 95457 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.default_bus.cpu_side_ports[0] 83 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::total 237088 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.pc.south_bridge.io_apic.int_request::board.apicbridge.cpu_side_port 140228 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.pc.south_bridge.io_apic.int_request::total 140228 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.pc.pci_host.down_to_up.mem_side_port::board.cache_hierarchy.iocache.cpu_side_port 128706128 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.pc.pci_host.down_to_up.mem_side_port::total 128706128 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize::total 129083444 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 0.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.dram.bytesRead::pc.south_bridge.ide 2169384 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::total 2169384 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesWritten::pc.south_bridge.ide 62207488 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl0.dram.bytesWritten::total 62207488 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl0.dram.numReads::pc.south_bridge.ide 42245 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::total 42245 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numWrites::pc.south_bridge.ide 971992 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numWrites::total 971992 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.bwRead::pc.south_bridge.ide 127529 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::total 127529 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwWrite::pc.south_bridge.ide 3656905 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwWrite::total 3656905 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::pc.south_bridge.ide 3784434 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::total 3784434 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 5552379321135.359375 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 5552379321135.359375 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 326.400000 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 17010966056950 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 5552379321135.359375 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 5552379321135.359375 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 326.400000 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 17010966056950 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 0.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.dram.bytesRead::pc.south_bridge.ide 2121768 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::total 2121768 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesWritten::pc.south_bridge.ide 62207488 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl1.dram.bytesWritten::total 62207488 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl1.dram.numReads::pc.south_bridge.ide 36293 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::total 36293 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numWrites::pc.south_bridge.ide 971992 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numWrites::total 971992 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.bwRead::pc.south_bridge.ide 124729 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::total 124729 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwWrite::pc.south_bridge.ide 3656905 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwWrite::total 3656905 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::pc.south_bridge.ide 3781634 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::total 3781634 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 5552379321135.359375 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 5552379321135.359375 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 326.400000 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 17010966056950 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 5552379321135.359375 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 5552379321135.359375 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 326.400000 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 17010966056950 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.bad_addr.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.com_1.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.default_bus.transDist::ReadReq 41 # Transaction distribution (Count)
board.pc.default_bus.transDist::ReadResp 41 # Transaction distribution (Count)
board.pc.default_bus.transDist::WriteReq 42 # Transaction distribution (Count)
board.pc.default_bus.transDist::WriteResp 42 # Transaction distribution (Count)
board.pc.default_bus.pktCount_board.iobus.default::board.pc.empty_isa.pio 166 # Packet count per connected requestor and responder (Count)
board.pc.default_bus.pktCount_board.iobus.default::total 166 # Packet count per connected requestor and responder (Count)
board.pc.default_bus.pktSize_board.iobus.default::board.pc.empty_isa.pio 83 # Cumulative packet size per connected requestor and responder (Byte)
board.pc.default_bus.pktSize_board.iobus.default::total 83 # Cumulative packet size per connected requestor and responder (Byte)
board.pc.default_bus.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.empty_isa.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.fake_com_2.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.fake_com_3.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.fake_com_4.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.fake_floppy.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.pci_bus.transDist::ReadReq 121056 # Transaction distribution (Count)
board.pc.pci_bus.transDist::ReadResp 121056 # Transaction distribution (Count)
board.pc.pci_bus.transDist::WriteReq 1986063 # Transaction distribution (Count)
board.pc.pci_bus.transDist::WriteResp 1986063 # Transaction distribution (Count)
board.pc.pci_bus.pktCount_board.pc.south_bridge.ide.dma::board.pc.pci_host.down_to_up.cpu_side_port 4045044 # Packet count per connected requestor and responder (Count)
board.pc.pci_bus.pktCount_board.pc.south_bridge.ide.dma::total 4045044 # Packet count per connected requestor and responder (Count)
board.pc.pci_bus.pktCount_board.pc.pci_host.up_to_down.mem_side_port::board.pc.south_bridge.ide.pio 168974 # Packet count per connected requestor and responder (Count)
board.pc.pci_bus.pktCount_board.pc.pci_host.up_to_down.mem_side_port::board.pc.pci_host.config_error.pio 220 # Packet count per connected requestor and responder (Count)
board.pc.pci_bus.pktCount_board.pc.pci_host.up_to_down.mem_side_port::total 169194 # Packet count per connected requestor and responder (Count)
board.pc.pci_bus.pktCount::total 4214238 # Packet count per connected requestor and responder (Count)
board.pc.pci_bus.pktSize_board.pc.south_bridge.ide.dma::board.pc.pci_host.down_to_up.cpu_side_port 128706128 # Cumulative packet size per connected requestor and responder (Byte)
board.pc.pci_bus.pktSize_board.pc.south_bridge.ide.dma::total 128706128 # Cumulative packet size per connected requestor and responder (Byte)
board.pc.pci_bus.pktSize_board.pc.pci_host.up_to_down.mem_side_port::board.pc.south_bridge.ide.pio 95083 # Cumulative packet size per connected requestor and responder (Byte)
board.pc.pci_bus.pktSize_board.pc.pci_host.up_to_down.mem_side_port::board.pc.pci_host.config_error.pio 374 # Cumulative packet size per connected requestor and responder (Byte)
board.pc.pci_bus.pktSize_board.pc.pci_host.up_to_down.mem_side_port::total 95457 # Cumulative packet size per connected requestor and responder (Byte)
board.pc.pci_bus.pktSize::total 128801585 # Cumulative packet size per connected requestor and responder (Byte)
board.pc.pci_bus.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.pci_host.config_error.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.pci_host.down_to_up.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.pci_host.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.pci_host.up_to_down.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.cmos.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.dma1.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.ide.disks.IdeDisk.dmaReadFullPages 1022 # Number of full page size DMA reads (not PRD). (Count)
board.pc.south_bridge.ide.disks.IdeDisk.dmaReadBytes 4186112 # Number of bytes transfered via DMA reads (not PRD). (Byte)
board.pc.south_bridge.ide.disks.IdeDisk.dmaReadTxs 1022 # Number of DMA read transactions (not PRD). (Count)
board.pc.south_bridge.ide.disks.IdeDisk.dmaWriteFullPages 30374 # Number of full page size DMA writes. (Count)
board.pc.south_bridge.ide.disks.IdeDisk.dmaWriteBytes 124414976 # Number of bytes transfered via DMA writes. (Byte)
board.pc.south_bridge.ide.disks.IdeDisk.dmaWriteTxs 30377 # Number of DMA write transactions. (Count)
board.pc.south_bridge.ide.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.io_apic.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.keyboard.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.pic1.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.pic2.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.pit.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.speaker.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start0.core.numCycles 34067223835 # Number of cpu cycles simulated (Cycle)
board.processor.start0.core.cpi 3.125619 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start0.core.ipc 0.319937 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start0.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start0.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start0.core.numVMExits 296505 # total number of KVM exits (Count)
board.processor.start0.core.numVMHalfEntries 0 # number of KVM entries to finalize pending operations (Count)
board.processor.start0.core.numExitSignal 49220 # exits due to signal delivery (Count)
board.processor.start0.core.numMMIO 86216 # number of VM exits due to memory mapped IO (Count)
board.processor.start0.core.numCoalescedMMIO 0 # number of coalesced memory mapped IO requests (Count)
board.processor.start0.core.numIO 137352 # number of VM exits due to legacy IO (Count)
board.processor.start0.core.numHalt 0 # number of VM exits due to wait for interrupt instructions (Count)
board.processor.start0.core.numInterrupts 32458 # number of interrupts delivered (Count)
board.processor.start0.core.numHypercalls 0 # number of hypercalls (Count)
board.processor.start0.core.commitStats0.numInsts 10899350953 # Number of instructions committed (thread level) (Count)
board.processor.start0.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start0.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start0.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start0.core.commitStats0.numUserInsts 9945247 # Numbrer of instructions committed in user mode (Count)
board.processor.start0.core.commitStats0.numUserOps 0 # Number of ops committed in user mode (Count)
board.processor.start0.core.commitStats0.ratioUserInsts 0.000912 # Ratio of instructions committed in user mode (Ratio)
board.processor.start0.core.commitStats0.ratioUserOps nan # Ratio of ops committed in user mode (Ratio)
board.processor.start0.core.commitStats0.cpi 3.125619 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start0.core.commitStats0.ipc 0.319937 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start0.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start0.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start0.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start0.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start0.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start0.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start0.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdSha3 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdSm4e 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdCrc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdDotProd 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdBf16Add 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdBf16Cmp 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdBf16Cvt 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdBf16DotProd 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdBf16MatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdBf16Mult 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdBf16MultAcc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::Bf16Cvt 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::System 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.functionCalls 0 # Number of function calls committed (Count)
board.processor.start0.core.commitStats0.numCallsReturns 0 # Number of function calls and returns committed (Count)
board.processor.start0.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start0.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start0.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start0.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start0.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start0.core.executeStats0.instRate 0 # Inst execution rate ((Count/Cycle))
board.processor.start0.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start0.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start0.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start0.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start0.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start0.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start0.core.fetchStats0.fetchRate 0 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start0.core.fetchStats0.branchRate 0 # Number of branch fetches per cycle (Ratio)
board.processor.start0.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start0.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start0.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start0.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start0.core.mmu.dtb.exAccesses 0 # TLB accesses on execute (instr) requests (Count)
board.processor.start0.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start0.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start0.core.mmu.dtb.exMisses 0 # TLB misses on execute (instr) requests (Count)
board.processor.start0.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start0.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start0.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start0.core.mmu.itb.exAccesses 0 # TLB accesses on execute (instr) requests (Count)
board.processor.start0.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start0.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start0.core.mmu.itb.exMisses 0 # TLB misses on execute (instr) requests (Count)
board.processor.start0.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start0.core.power_state.pwrStateResidencyTicks::ON 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start0.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start0.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start0.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start1.core.numCycles 34585459094 # Number of cpu cycles simulated (Cycle)
board.processor.start1.core.cpi 3.988655 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start1.core.ipc 0.250711 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start1.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start1.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start1.core.numVMExits 158621 # total number of KVM exits (Count)
board.processor.start1.core.numVMHalfEntries 0 # number of KVM entries to finalize pending operations (Count)
board.processor.start1.core.numExitSignal 36238 # exits due to signal delivery (Count)
board.processor.start1.core.numMMIO 23408 # number of VM exits due to memory mapped IO (Count)
board.processor.start1.core.numCoalescedMMIO 0 # number of coalesced memory mapped IO requests (Count)
board.processor.start1.core.numIO 86914 # number of VM exits due to legacy IO (Count)
board.processor.start1.core.numHalt 0 # number of VM exits due to wait for interrupt instructions (Count)
board.processor.start1.core.numInterrupts 20995 # number of interrupts delivered (Count)
board.processor.start1.core.numHypercalls 0 # number of hypercalls (Count)
board.processor.start1.core.commitStats0.numInsts 8670958574 # Number of instructions committed (thread level) (Count)
board.processor.start1.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start1.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start1.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start1.core.commitStats0.numUserInsts 49501 # Numbrer of instructions committed in user mode (Count)
board.processor.start1.core.commitStats0.numUserOps 0 # Number of ops committed in user mode (Count)
board.processor.start1.core.commitStats0.ratioUserInsts 0.000006 # Ratio of instructions committed in user mode (Ratio)
board.processor.start1.core.commitStats0.ratioUserOps nan # Ratio of ops committed in user mode (Ratio)
board.processor.start1.core.commitStats0.cpi 3.988655 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start1.core.commitStats0.ipc 0.250711 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start1.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start1.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start1.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start1.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start1.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start1.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start1.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdSha3 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdSm4e 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdCrc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdDotProd 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdBf16Add 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdBf16Cmp 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdBf16Cvt 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdBf16DotProd 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdBf16MatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdBf16Mult 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdBf16MultAcc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::Bf16Cvt 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::System 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.functionCalls 0 # Number of function calls committed (Count)
board.processor.start1.core.commitStats0.numCallsReturns 0 # Number of function calls and returns committed (Count)
board.processor.start1.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start1.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start1.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start1.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start1.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start1.core.executeStats0.instRate 0 # Inst execution rate ((Count/Cycle))
board.processor.start1.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start1.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start1.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start1.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start1.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start1.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start1.core.fetchStats0.fetchRate 0 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start1.core.fetchStats0.branchRate 0 # Number of branch fetches per cycle (Ratio)
board.processor.start1.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start1.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start1.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start1.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start1.core.mmu.dtb.exAccesses 0 # TLB accesses on execute (instr) requests (Count)
board.processor.start1.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start1.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start1.core.mmu.dtb.exMisses 0 # TLB misses on execute (instr) requests (Count)
board.processor.start1.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start1.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start1.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start1.core.mmu.itb.exAccesses 0 # TLB accesses on execute (instr) requests (Count)
board.processor.start1.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start1.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start1.core.mmu.itb.exMisses 0 # TLB misses on execute (instr) requests (Count)
board.processor.start1.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start1.core.power_state.pwrStateResidencyTicks::ON 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start1.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start1.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start1.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.switch0.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.switch0.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch0.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch0.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch0.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch0.core.issuedInstType_0::No_OpClass 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::IntAlu 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::IntMult 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::IntDiv 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::FloatAdd 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::FloatCmp 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::FloatCvt 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::FloatMult 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::FloatMultAcc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::FloatDiv 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::FloatMisc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::FloatSqrt 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdAdd 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdAddAcc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdAlu 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdCmp 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdCvt 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdMisc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdMult 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdMultAcc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdMatMultAcc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdShift 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdShiftAcc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdDiv 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdSqrt 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatAdd 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatAlu 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatCmp 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatCvt 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatDiv 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatMisc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatMult 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatMultAcc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatMatMultAcc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatSqrt 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdReduceAdd 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdReduceAlu 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdReduceCmp 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatReduceAdd 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatReduceCmp 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdAes 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdAesMix 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdSha1Hash 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdSha1Hash2 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdSha256Hash 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdSha256Hash2 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdShaSigma2 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdShaSigma3 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdSha3 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdSm4e 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdCrc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdPredAlu 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdDotProd 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::Matrix 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::MatrixMov 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::MatrixOP 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::MemRead 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::MemWrite 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::FloatMemRead 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::FloatMemWrite 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::InstPrefetch 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdUnitStrideLoad 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdUnitStrideStore 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdUnitStrideMaskLoad 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdUnitStrideMaskStore 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdStridedLoad 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdStridedStore 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdIndexedLoad 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdIndexedStore 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdWholeRegisterLoad 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdWholeRegisterStore 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdUnitStrideSegmentedLoad 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdUnitStrideSegmentedStore 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdStrideSegmentedLoad 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdStrideSegmentedStore 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdExt 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatExt 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdConfig 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdBf16Add 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdBf16Cmp 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdBf16Cvt 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdBf16DotProd 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdBf16MatMultAcc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdBf16Mult 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdBf16MultAcc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::Bf16Cvt 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::System 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::total 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch0.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch0.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch0.core.commitStats0.numUserInsts 0 # Numbrer of instructions committed in user mode (Count)
board.processor.switch0.core.commitStats0.numUserOps 0 # Number of ops committed in user mode (Count)
board.processor.switch0.core.commitStats0.ratioUserInsts nan # Ratio of instructions committed in user mode (Ratio)
board.processor.switch0.core.commitStats0.ratioUserOps nan # Ratio of ops committed in user mode (Ratio)
board.processor.switch0.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch0.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch0.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.switch0.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch0.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.switch0.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.switch0.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.switch0.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch0.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdSha3 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdSm4e 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdCrc 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdDotProd 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdBf16Add 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdBf16Cmp 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdBf16Cvt 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdBf16DotProd 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdBf16MatMultAcc 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdBf16Mult 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdBf16MultAcc 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::Bf16Cvt 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::System 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.functionCalls 0 # Number of function calls committed (Count)
board.processor.switch0.core.commitStats0.numCallsReturns 0 # Number of function calls and returns committed (Count)
board.processor.switch0.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.switch0.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.switch0.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.switch0.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.switch0.core.exec_context.thread_0.notIdleFraction 0 # Percentage of non-idle cycles (Ratio)
board.processor.switch0.core.exec_context.thread_0.idleFraction 1 # Percentage of idle cycles (Ratio)
board.processor.switch0.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.switch0.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch0.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.switch0.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.switch0.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.switch0.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.switch0.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch0.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.switch0.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch0.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch0.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.switch0.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch0.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch0.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.switch0.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch0.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch0.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch0.core.mmu.dtb.exAccesses 0 # TLB accesses on execute (instr) requests (Count)
board.processor.switch0.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch0.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch0.core.mmu.dtb.exMisses 0 # TLB misses on execute (instr) requests (Count)
board.processor.switch0.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch0.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch0.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch0.core.mmu.itb.exAccesses 0 # TLB accesses on execute (instr) requests (Count)
board.processor.switch0.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch0.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch0.core.mmu.itb.exMisses 0 # TLB misses on execute (instr) requests (Count)
board.processor.switch0.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch0.core.power_state.pwrStateResidencyTicks::OFF 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch0.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.switch0.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.switch0.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.switch1.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.switch1.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch1.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch1.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch1.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch1.core.issuedInstType_0::No_OpClass 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::IntAlu 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::IntMult 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::IntDiv 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::FloatAdd 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::FloatCmp 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::FloatCvt 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::FloatMult 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::FloatMultAcc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::FloatDiv 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::FloatMisc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::FloatSqrt 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdAdd 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdAddAcc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdAlu 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdCmp 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdCvt 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdMisc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdMult 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdMultAcc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdMatMultAcc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdShift 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdShiftAcc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdDiv 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdSqrt 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatAdd 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatAlu 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatCmp 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatCvt 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatDiv 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatMisc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatMult 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatMultAcc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatMatMultAcc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatSqrt 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdReduceAdd 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdReduceAlu 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdReduceCmp 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatReduceAdd 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatReduceCmp 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdAes 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdAesMix 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdSha1Hash 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdSha1Hash2 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdSha256Hash 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdSha256Hash2 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdShaSigma2 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdShaSigma3 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdSha3 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdSm4e 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdCrc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdPredAlu 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdDotProd 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::Matrix 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::MatrixMov 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::MatrixOP 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::MemRead 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::MemWrite 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::FloatMemRead 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::FloatMemWrite 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::InstPrefetch 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdUnitStrideLoad 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdUnitStrideStore 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdUnitStrideMaskLoad 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdUnitStrideMaskStore 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdStridedLoad 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdStridedStore 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdIndexedLoad 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdIndexedStore 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdWholeRegisterLoad 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdWholeRegisterStore 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdUnitStrideSegmentedLoad 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdUnitStrideSegmentedStore 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdStrideSegmentedLoad 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdStrideSegmentedStore 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdExt 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatExt 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdConfig 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdBf16Add 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdBf16Cmp 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdBf16Cvt 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdBf16DotProd 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdBf16MatMultAcc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdBf16Mult 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdBf16MultAcc 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::Bf16Cvt 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::System 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::total 0 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch1.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch1.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch1.core.commitStats0.numUserInsts 0 # Numbrer of instructions committed in user mode (Count)
board.processor.switch1.core.commitStats0.numUserOps 0 # Number of ops committed in user mode (Count)
board.processor.switch1.core.commitStats0.ratioUserInsts nan # Ratio of instructions committed in user mode (Ratio)
board.processor.switch1.core.commitStats0.ratioUserOps nan # Ratio of ops committed in user mode (Ratio)
board.processor.switch1.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch1.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch1.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.switch1.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.switch1.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.switch1.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.switch1.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.switch1.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch1.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdSha3 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdSm4e 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdCrc 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdDotProd 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdBf16Add 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdBf16Cmp 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdBf16Cvt 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdBf16DotProd 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdBf16MatMultAcc 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdBf16Mult 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdBf16MultAcc 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::Bf16Cvt 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::System 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.functionCalls 0 # Number of function calls committed (Count)
board.processor.switch1.core.commitStats0.numCallsReturns 0 # Number of function calls and returns committed (Count)
board.processor.switch1.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.switch1.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.switch1.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.switch1.core.exec_context.thread_0.numBusyCycles 0 # Number of busy cycles (Cycle)
board.processor.switch1.core.exec_context.thread_0.notIdleFraction 0 # Percentage of non-idle cycles (Ratio)
board.processor.switch1.core.exec_context.thread_0.idleFraction 1 # Percentage of idle cycles (Ratio)
board.processor.switch1.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.switch1.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch1.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.switch1.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.switch1.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.switch1.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.switch1.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.switch1.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.switch1.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch1.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch1.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.switch1.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch1.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch1.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.switch1.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch1.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch1.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch1.core.mmu.dtb.exAccesses 0 # TLB accesses on execute (instr) requests (Count)
board.processor.switch1.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch1.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch1.core.mmu.dtb.exMisses 0 # TLB misses on execute (instr) requests (Count)
board.processor.switch1.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch1.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch1.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch1.core.mmu.itb.exAccesses 0 # TLB accesses on execute (instr) requests (Count)
board.processor.switch1.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch1.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch1.core.mmu.itb.exMisses 0 # TLB misses on execute (instr) requests (Count)
board.processor.switch1.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch1.core.power_state.pwrStateResidencyTicks::OFF 17010966056950 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch1.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.switch1.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.switch1.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
simSeconds 0.001000 # Number of seconds simulated (Second)
simTicks 1000000000 # Number of ticks simulated (Tick)
finalTick 17011966056950 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 2.03 # Real time elapsed on the host (Second)
hostTickRate 493070389 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3715820 # Number of bytes of host memory used (Byte)
simInsts 2690086 # Number of instructions simulated (Count)
simOps 4849661 # Number of ops (including micro ops) simulated (Count)
hostInstRate 1326359 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 2391143 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.apicbridge.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.bridge.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iocache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iocache.blockedCycles::no_wbuffers 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iocache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iocache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iocache.blockedCauses::no_wbuffers 0 # number of times access was blocked (Count)
board.cache_hierarchy.iocache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iocache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iocache.avgBlocked::no_wbuffers nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iocache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iocache.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iocache.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iocache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iocache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iocache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iocache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iocache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iocache.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iocache.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iocache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches0.demandHits::processor.switch0.core.data 354816 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches0.demandHits::total 354816 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches0.overallHits::processor.switch0.core.data 354816 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches0.overallHits::total 354816 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches0.demandMisses::processor.switch0.core.data 373 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches0.demandMisses::total 373 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches0.overallMisses::processor.switch0.core.data 373 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches0.overallMisses::total 373 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches0.demandMissLatency::processor.switch0.core.data 19474173 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.demandMissLatency::total 19474173 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.overallMissLatency::processor.switch0.core.data 19474173 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.overallMissLatency::total 19474173 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.demandAccesses::processor.switch0.core.data 355189 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches0.demandAccesses::total 355189 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches0.overallAccesses::processor.switch0.core.data 355189 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches0.overallAccesses::total 355189 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches0.demandMissRate::processor.switch0.core.data 0.001050 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches0.demandMissRate::total 0.001050 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches0.overallMissRate::processor.switch0.core.data 0.001050 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches0.overallMissRate::total 0.001050 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches0.demandAvgMissLatency::processor.switch0.core.data 52209.579088 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches0.demandAvgMissLatency::total 52209.579088 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches0.overallAvgMissLatency::processor.switch0.core.data 52209.579088 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.overallAvgMissLatency::total 52209.579088 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches0.blockedCycles::no_wbuffers 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches0.blockedCauses::no_wbuffers 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches0.avgBlocked::no_wbuffers nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches0.writebacks::writebacks 129 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches0.writebacks::total 129 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches0.demandMshrMisses::processor.switch0.core.data 373 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.demandMshrMisses::total 373 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.overallMshrMisses::cache_hierarchy.l1dcaches0.prefetcher 2138 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.overallMshrMisses::processor.switch0.core.data 373 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.overallMshrMisses::total 2511 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.overallMshrUncacheable::processor.switch0.core.data 1701 # number of overall MSHR uncacheable misses (Count)
board.cache_hierarchy.l1dcaches0.overallMshrUncacheable::total 1701 # number of overall MSHR uncacheable misses (Count)
board.cache_hierarchy.l1dcaches0.demandMshrMissLatency::processor.switch0.core.data 19349964 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.demandMshrMissLatency::total 19349964 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.overallMshrMissLatency::cache_hierarchy.l1dcaches0.prefetcher 112297092 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.overallMshrMissLatency::processor.switch0.core.data 19349964 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.overallMshrMissLatency::total 131647056 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.overallMshrUncacheableLatency::processor.switch0.core.data 262514556 # number of overall MSHR uncacheable ticks (Tick)
board.cache_hierarchy.l1dcaches0.overallMshrUncacheableLatency::total 262514556 # number of overall MSHR uncacheable ticks (Tick)
board.cache_hierarchy.l1dcaches0.demandMshrMissRate::processor.switch0.core.data 0.001050 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches0.demandMshrMissRate::total 0.001050 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches0.overallMshrMissRate::cache_hierarchy.l1dcaches0.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches0.overallMshrMissRate::processor.switch0.core.data 0.001050 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches0.overallMshrMissRate::total 0.007069 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches0.demandAvgMshrMissLatency::processor.switch0.core.data 51876.579088 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.demandAvgMshrMissLatency::total 51876.579088 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches0.prefetcher 52524.364827 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.overallAvgMshrMissLatency::processor.switch0.core.data 51876.579088 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.overallAvgMshrMissLatency::total 52428.138590 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.overallAvgMshrUncacheableLatency::processor.switch0.core.data 154329.544974 # average overall mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.overallAvgMshrUncacheableLatency::total 154329.544974 # average overall mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.replacements 2010 # number of replacements (Count)
board.cache_hierarchy.l1dcaches0.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches0.prefetcher 2138 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.HardPFReq.mshrMisses::total 2138 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches0.prefetcher 112297092 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.HardPFReq.mshrMissLatency::total 112297092 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches0.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches0.prefetcher 52524.364827 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.HardPFReq.avgMshrMissLatency::total 52524.364827 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.hits::processor.switch0.core.data 1457 # number of LockedRMWReadReq hits (Count)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.hits::total 1457 # number of LockedRMWReadReq hits (Count)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.misses::processor.switch0.core.data 11 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.misses::total 11 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.missLatency::processor.switch0.core.data 700965 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.missLatency::total 700965 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.accesses::processor.switch0.core.data 1468 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.accesses::total 1468 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.missRate::processor.switch0.core.data 0.007493 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.missRate::total 0.007493 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.avgMissLatency::processor.switch0.core.data 63724.090909 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.avgMissLatency::total 63724.090909 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.mshrMisses::processor.switch0.core.data 11 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.mshrMisses::total 11 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.mshrMissLatency::processor.switch0.core.data 1883448 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.mshrMissLatency::total 1883448 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.mshrMissRate::processor.switch0.core.data 0.007493 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.mshrMissRate::total 0.007493 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.avgMshrMissLatency::processor.switch0.core.data 171222.545455 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.avgMshrMissLatency::total 171222.545455 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.LockedRMWWriteReq.hits::processor.switch0.core.data 1468 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1dcaches0.LockedRMWWriteReq.hits::total 1468 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1dcaches0.LockedRMWWriteReq.accesses::processor.switch0.core.data 1468 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches0.LockedRMWWriteReq.accesses::total 1468 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.hits::processor.switch0.core.data 263752 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.hits::total 263752 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.misses::processor.switch0.core.data 327 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.misses::total 327 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.missLatency::processor.switch0.core.data 17718930 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.ReadReq.missLatency::total 17718930 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.ReadReq.accesses::processor.switch0.core.data 264079 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.accesses::total 264079 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.missRate::processor.switch0.core.data 0.001238 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.ReadReq.missRate::total 0.001238 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.ReadReq.avgMissLatency::processor.switch0.core.data 54186.330275 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.ReadReq.avgMissLatency::total 54186.330275 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.ReadReq.mshrMisses::processor.switch0.core.data 327 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrMisses::total 327 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrUncacheable::processor.switch0.core.data 1272 # number of ReadReq MSHR uncacheable (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrUncacheable::total 1272 # number of ReadReq MSHR uncacheable (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrMissLatency::processor.switch0.core.data 17610039 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrMissLatency::total 17610039 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrUncacheableLatency::processor.switch0.core.data 262514556 # number of ReadReq MSHR uncacheable ticks (Tick)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrUncacheableLatency::total 262514556 # number of ReadReq MSHR uncacheable ticks (Tick)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrMissRate::processor.switch0.core.data 0.001238 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrMissRate::total 0.001238 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.ReadReq.avgMshrMissLatency::processor.switch0.core.data 53853.330275 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.ReadReq.avgMshrMissLatency::total 53853.330275 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.ReadReq.avgMshrUncacheableLatency::processor.switch0.core.data 206379.367925 # average ReadReq mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.ReadReq.avgMshrUncacheableLatency::total 206379.367925 # average ReadReq mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.WriteReq.hits::processor.switch0.core.data 91064 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches0.WriteReq.hits::total 91064 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches0.WriteReq.misses::processor.switch0.core.data 46 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches0.WriteReq.misses::total 46 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches0.WriteReq.missLatency::processor.switch0.core.data 1755243 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.WriteReq.missLatency::total 1755243 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.WriteReq.accesses::processor.switch0.core.data 91110 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches0.WriteReq.accesses::total 91110 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches0.WriteReq.missRate::processor.switch0.core.data 0.000505 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.WriteReq.missRate::total 0.000505 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.WriteReq.avgMissLatency::processor.switch0.core.data 38157.456522 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.WriteReq.avgMissLatency::total 38157.456522 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.WriteReq.mshrMisses::processor.switch0.core.data 46 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.WriteReq.mshrMisses::total 46 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.WriteReq.mshrUncacheable::processor.switch0.core.data 429 # number of WriteReq MSHR uncacheable (Count)
board.cache_hierarchy.l1dcaches0.WriteReq.mshrUncacheable::total 429 # number of WriteReq MSHR uncacheable (Count)
board.cache_hierarchy.l1dcaches0.WriteReq.mshrMissLatency::processor.switch0.core.data 1739925 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.WriteReq.mshrMissLatency::total 1739925 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.WriteReq.mshrMissRate::processor.switch0.core.data 0.000505 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.WriteReq.mshrMissRate::total 0.000505 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.WriteReq.avgMshrMissLatency::processor.switch0.core.data 37824.456522 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.WriteReq.avgMshrMissLatency::total 37824.456522 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches0.prefetcher.demandMshrMisses 373 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfIssued 8316 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfUnused 4 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfUseful 2130 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.accuracy 0.256133 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.coverage 0.850979 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfHitInCache 6105 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfHitInMSHR 73 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfLate 6178 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfIdentified 8316 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfSpanPage 344 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfUsefulSpanPage 340 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches0.tags.tagsInUse 265.708168 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches0.tags.totalRefs 360263 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches0.tags.sampledRefs 2522 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches0.tags.avgRefs 142.848136 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches0.tags.warmupTick 17010966633372 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches0.tags.occupancies::cache_hierarchy.l1dcaches0.prefetcher 177.803503 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches0.tags.occupancies::processor.switch0.core.data 87.904666 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches0.tags.avgOccs::cache_hierarchy.l1dcaches0.prefetcher 0.347272 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches0.tags.avgOccs::processor.switch0.core.data 0.171689 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches0.tags.avgOccs::total 0.518961 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches0.tags.occupanciesTaskId::1022 428 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches0.tags.occupanciesTaskId::1024 84 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches0.tags.ageTaskId_1022::0 46 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches0.tags.ageTaskId_1022::1 382 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches0.tags.ageTaskId_1024::0 1 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches0.tags.ageTaskId_1024::1 6 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches0.tags.ageTaskId_1024::2 77 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches0.tags.ratioOccsTaskId::1022 0.835938 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches0.tags.ratioOccsTaskId::1024 0.164062 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches0.tags.tagAccesses 2867522 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches0.tags.dataAccesses 2867522 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches1.demandHits::processor.switch1.core.data 526108 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches1.demandHits::total 526108 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches1.overallHits::processor.switch1.core.data 526108 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches1.overallHits::total 526108 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches1.demandMisses::processor.switch1.core.data 313 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches1.demandMisses::total 313 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches1.overallMisses::processor.switch1.core.data 313 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches1.overallMisses::total 313 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches1.demandMissLatency::processor.switch1.core.data 16922061 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.demandMissLatency::total 16922061 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.overallMissLatency::processor.switch1.core.data 16922061 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.overallMissLatency::total 16922061 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.demandAccesses::processor.switch1.core.data 526421 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches1.demandAccesses::total 526421 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches1.overallAccesses::processor.switch1.core.data 526421 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches1.overallAccesses::total 526421 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches1.demandMissRate::processor.switch1.core.data 0.000595 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches1.demandMissRate::total 0.000595 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches1.overallMissRate::processor.switch1.core.data 0.000595 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches1.overallMissRate::total 0.000595 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches1.demandAvgMissLatency::processor.switch1.core.data 54064.092652 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches1.demandAvgMissLatency::total 54064.092652 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches1.overallAvgMissLatency::processor.switch1.core.data 54064.092652 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.overallAvgMissLatency::total 54064.092652 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches1.blockedCycles::no_wbuffers 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches1.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches1.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches1.blockedCauses::no_wbuffers 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches1.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches1.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches1.avgBlocked::no_wbuffers nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches1.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches1.writebacks::writebacks 58 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches1.writebacks::total 58 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches1.demandMshrMisses::processor.switch1.core.data 313 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.demandMshrMisses::total 313 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.overallMshrMisses::cache_hierarchy.l1dcaches1.prefetcher 4429 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.overallMshrMisses::processor.switch1.core.data 313 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.overallMshrMisses::total 4742 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.overallMshrUncacheable::processor.switch1.core.data 1 # number of overall MSHR uncacheable misses (Count)
board.cache_hierarchy.l1dcaches1.overallMshrUncacheable::total 1 # number of overall MSHR uncacheable misses (Count)
board.cache_hierarchy.l1dcaches1.demandMshrMissLatency::processor.switch1.core.data 16817832 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.demandMshrMissLatency::total 16817832 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.overallMshrMissLatency::cache_hierarchy.l1dcaches1.prefetcher 230882085 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.overallMshrMissLatency::processor.switch1.core.data 16817832 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.overallMshrMissLatency::total 247699917 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.demandMshrMissRate::processor.switch1.core.data 0.000595 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches1.demandMshrMissRate::total 0.000595 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches1.overallMshrMissRate::cache_hierarchy.l1dcaches1.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches1.overallMshrMissRate::processor.switch1.core.data 0.000595 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches1.overallMshrMissRate::total 0.009008 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches1.demandAvgMshrMissLatency::processor.switch1.core.data 53731.092652 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.demandAvgMshrMissLatency::total 53731.092652 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches1.prefetcher 52129.619553 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.overallAvgMshrMissLatency::processor.switch1.core.data 53731.092652 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.overallAvgMshrMissLatency::total 52235.326234 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.replacements 4231 # number of replacements (Count)
board.cache_hierarchy.l1dcaches1.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches1.prefetcher 4429 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.HardPFReq.mshrMisses::total 4429 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches1.prefetcher 230882085 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.HardPFReq.mshrMissLatency::total 230882085 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches1.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches1.prefetcher 52129.619553 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.HardPFReq.avgMshrMissLatency::total 52129.619553 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.hits::processor.switch1.core.data 6 # number of LockedRMWReadReq hits (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.hits::total 6 # number of LockedRMWReadReq hits (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.misses::processor.switch1.core.data 2 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.misses::total 2 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.missLatency::processor.switch1.core.data 111555 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.missLatency::total 111555 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.accesses::processor.switch1.core.data 8 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.accesses::total 8 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.missRate::processor.switch1.core.data 0.250000 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.missRate::total 0.250000 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.avgMissLatency::processor.switch1.core.data 55777.500000 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.avgMissLatency::total 55777.500000 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.mshrMisses::processor.switch1.core.data 2 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.mshrMisses::total 2 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.mshrMissLatency::processor.switch1.core.data 224442 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.mshrMissLatency::total 224442 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.mshrMissRate::processor.switch1.core.data 0.250000 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.mshrMissRate::total 0.250000 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.avgMshrMissLatency::processor.switch1.core.data 112221 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.avgMshrMissLatency::total 112221 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.LockedRMWWriteReq.hits::processor.switch1.core.data 8 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWWriteReq.hits::total 8 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWWriteReq.accesses::processor.switch1.core.data 8 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWWriteReq.accesses::total 8 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.hits::processor.switch1.core.data 426757 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.hits::total 426757 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.misses::processor.switch1.core.data 294 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.misses::total 294 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.missLatency::processor.switch1.core.data 15762555 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.ReadReq.missLatency::total 15762555 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.ReadReq.accesses::processor.switch1.core.data 427051 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.accesses::total 427051 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.missRate::processor.switch1.core.data 0.000688 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.ReadReq.missRate::total 0.000688 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.ReadReq.avgMissLatency::processor.switch1.core.data 53614.132653 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.ReadReq.avgMissLatency::total 53614.132653 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.ReadReq.mshrMisses::processor.switch1.core.data 294 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.mshrMisses::total 294 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.mshrMissLatency::processor.switch1.core.data 15664653 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.ReadReq.mshrMissLatency::total 15664653 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.ReadReq.mshrMissRate::processor.switch1.core.data 0.000688 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.ReadReq.mshrMissRate::total 0.000688 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.ReadReq.avgMshrMissLatency::processor.switch1.core.data 53281.132653 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.ReadReq.avgMshrMissLatency::total 53281.132653 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.WriteReq.hits::processor.switch1.core.data 99351 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches1.WriteReq.hits::total 99351 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches1.WriteReq.misses::processor.switch1.core.data 19 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches1.WriteReq.misses::total 19 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches1.WriteReq.missLatency::processor.switch1.core.data 1159506 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.WriteReq.missLatency::total 1159506 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.WriteReq.accesses::processor.switch1.core.data 99370 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches1.WriteReq.accesses::total 99370 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches1.WriteReq.missRate::processor.switch1.core.data 0.000191 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.WriteReq.missRate::total 0.000191 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.WriteReq.avgMissLatency::processor.switch1.core.data 61026.631579 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.WriteReq.avgMissLatency::total 61026.631579 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.WriteReq.mshrMisses::processor.switch1.core.data 19 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.WriteReq.mshrMisses::total 19 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.WriteReq.mshrUncacheable::processor.switch1.core.data 1 # number of WriteReq MSHR uncacheable (Count)
board.cache_hierarchy.l1dcaches1.WriteReq.mshrUncacheable::total 1 # number of WriteReq MSHR uncacheable (Count)
board.cache_hierarchy.l1dcaches1.WriteReq.mshrMissLatency::processor.switch1.core.data 1153179 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.WriteReq.mshrMissLatency::total 1153179 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.WriteReq.mshrMissRate::processor.switch1.core.data 0.000191 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.WriteReq.mshrMissRate::total 0.000191 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.WriteReq.avgMshrMissLatency::processor.switch1.core.data 60693.631579 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.WriteReq.avgMshrMissLatency::total 60693.631579 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches1.prefetcher.demandMshrMisses 313 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfIssued 17284 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfUnused 1 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfUseful 4424 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.accuracy 0.255959 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.coverage 0.933924 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfHitInCache 12710 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfHitInMSHR 145 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfLate 12855 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfIdentified 17284 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfSpanPage 704 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfUsefulSpanPage 700 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches1.tags.tagsInUse 488.449493 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches1.tags.totalRefs 530865 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches1.tags.sampledRefs 4743 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches1.tags.avgRefs 111.925996 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches1.tags.warmupTick 17010966638367 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches1.tags.occupancies::cache_hierarchy.l1dcaches1.prefetcher 391.181447 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches1.tags.occupancies::processor.switch1.core.data 97.268046 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches1.tags.avgOccs::cache_hierarchy.l1dcaches1.prefetcher 0.764026 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches1.tags.avgOccs::processor.switch1.core.data 0.189977 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches1.tags.avgOccs::total 0.954003 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches1.tags.occupanciesTaskId::1022 427 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches1.tags.occupanciesTaskId::1024 85 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches1.tags.ageTaskId_1022::0 47 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches1.tags.ageTaskId_1022::1 380 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches1.tags.ageTaskId_1024::1 7 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches1.tags.ageTaskId_1024::2 78 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches1.tags.ratioOccsTaskId::1022 0.833984 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches1.tags.ratioOccsTaskId::1024 0.166016 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches1.tags.tagAccesses 4216239 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches1.tags.dataAccesses 4216239 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches1.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches0.demandHits::processor.switch0.core.inst 1405577 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches0.demandHits::total 1405577 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches0.overallHits::processor.switch0.core.inst 1405577 # number of overall hits (Count)
board.cache_hierarchy.l1icaches0.overallHits::total 1405577 # number of overall hits (Count)
board.cache_hierarchy.l1icaches0.demandMisses::processor.switch0.core.inst 424 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches0.demandMisses::total 424 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches0.overallMisses::processor.switch0.core.inst 424 # number of overall misses (Count)
board.cache_hierarchy.l1icaches0.overallMisses::total 424 # number of overall misses (Count)
board.cache_hierarchy.l1icaches0.demandMissLatency::processor.switch0.core.inst 22718925 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches0.demandMissLatency::total 22718925 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches0.overallMissLatency::processor.switch0.core.inst 22718925 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches0.overallMissLatency::total 22718925 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches0.demandAccesses::processor.switch0.core.inst 1406001 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches0.demandAccesses::total 1406001 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches0.overallAccesses::processor.switch0.core.inst 1406001 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches0.overallAccesses::total 1406001 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches0.demandMissRate::processor.switch0.core.inst 0.000302 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches0.demandMissRate::total 0.000302 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches0.overallMissRate::processor.switch0.core.inst 0.000302 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches0.overallMissRate::total 0.000302 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches0.demandAvgMissLatency::processor.switch0.core.inst 53582.370283 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches0.demandAvgMissLatency::total 53582.370283 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches0.overallAvgMissLatency::processor.switch0.core.inst 53582.370283 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches0.overallAvgMissLatency::total 53582.370283 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches0.blockedCycles::no_wbuffers 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches0.blockedCauses::no_wbuffers 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches0.avgBlocked::no_wbuffers nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches0.writebacks::writebacks 46 # number of writebacks (Count)
board.cache_hierarchy.l1icaches0.writebacks::total 46 # number of writebacks (Count)
board.cache_hierarchy.l1icaches0.demandMshrMisses::processor.switch0.core.inst 424 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches0.demandMshrMisses::total 424 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches0.overallMshrMisses::processor.switch0.core.inst 424 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches0.overallMshrMisses::total 424 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches0.demandMshrMissLatency::processor.switch0.core.inst 22577733 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches0.demandMshrMissLatency::total 22577733 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches0.overallMshrMissLatency::processor.switch0.core.inst 22577733 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches0.overallMshrMissLatency::total 22577733 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches0.demandMshrMissRate::processor.switch0.core.inst 0.000302 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches0.demandMshrMissRate::total 0.000302 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches0.overallMshrMissRate::processor.switch0.core.inst 0.000302 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches0.overallMshrMissRate::total 0.000302 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches0.demandAvgMshrMissLatency::processor.switch0.core.inst 53249.370283 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches0.demandAvgMshrMissLatency::total 53249.370283 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches0.overallAvgMshrMissLatency::processor.switch0.core.inst 53249.370283 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches0.overallAvgMshrMissLatency::total 53249.370283 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches0.replacements 46 # number of replacements (Count)
board.cache_hierarchy.l1icaches0.ReadReq.hits::processor.switch0.core.inst 1405577 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches0.ReadReq.hits::total 1405577 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches0.ReadReq.misses::processor.switch0.core.inst 424 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches0.ReadReq.misses::total 424 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches0.ReadReq.missLatency::processor.switch0.core.inst 22718925 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches0.ReadReq.missLatency::total 22718925 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches0.ReadReq.accesses::processor.switch0.core.inst 1406001 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches0.ReadReq.accesses::total 1406001 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches0.ReadReq.missRate::processor.switch0.core.inst 0.000302 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches0.ReadReq.missRate::total 0.000302 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches0.ReadReq.avgMissLatency::processor.switch0.core.inst 53582.370283 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches0.ReadReq.avgMissLatency::total 53582.370283 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches0.ReadReq.mshrMisses::processor.switch0.core.inst 424 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches0.ReadReq.mshrMisses::total 424 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches0.ReadReq.mshrMissLatency::processor.switch0.core.inst 22577733 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches0.ReadReq.mshrMissLatency::total 22577733 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches0.ReadReq.mshrMissRate::processor.switch0.core.inst 0.000302 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches0.ReadReq.mshrMissRate::total 0.000302 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches0.ReadReq.avgMshrMissLatency::processor.switch0.core.inst 53249.370283 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches0.ReadReq.avgMshrMissLatency::total 53249.370283 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches0.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches0.prefetcher.demandMshrMisses 424 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches0.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches0.tags.tagsInUse 194.936630 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches0.tags.totalRefs 1406001 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches0.tags.sampledRefs 424 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches0.tags.avgRefs 3316.040094 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches0.tags.warmupTick 17010966366639 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches0.tags.occupancies::processor.switch0.core.inst 194.936630 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches0.tags.avgOccs::processor.switch0.core.inst 0.380736 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches0.tags.avgOccs::total 0.380736 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches0.tags.occupanciesTaskId::1024 378 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches0.tags.ageTaskId_1024::2 378 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches0.tags.ratioOccsTaskId::1024 0.738281 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches0.tags.tagAccesses 11248432 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches0.tags.dataAccesses 11248432 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches1.demandHits::processor.switch1.core.inst 2308375 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches1.demandHits::total 2308375 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches1.overallHits::processor.switch1.core.inst 2308375 # number of overall hits (Count)
board.cache_hierarchy.l1icaches1.overallHits::total 2308375 # number of overall hits (Count)
board.cache_hierarchy.l1icaches1.demandMisses::processor.switch1.core.inst 272 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches1.demandMisses::total 272 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches1.overallMisses::processor.switch1.core.inst 272 # number of overall misses (Count)
board.cache_hierarchy.l1icaches1.overallMisses::total 272 # number of overall misses (Count)
board.cache_hierarchy.l1icaches1.demandMissLatency::processor.switch1.core.inst 14305014 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches1.demandMissLatency::total 14305014 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches1.overallMissLatency::processor.switch1.core.inst 14305014 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches1.overallMissLatency::total 14305014 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches1.demandAccesses::processor.switch1.core.inst 2308647 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches1.demandAccesses::total 2308647 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches1.overallAccesses::processor.switch1.core.inst 2308647 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches1.overallAccesses::total 2308647 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches1.demandMissRate::processor.switch1.core.inst 0.000118 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches1.demandMissRate::total 0.000118 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches1.overallMissRate::processor.switch1.core.inst 0.000118 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches1.overallMissRate::total 0.000118 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches1.demandAvgMissLatency::processor.switch1.core.inst 52591.963235 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches1.demandAvgMissLatency::total 52591.963235 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches1.overallAvgMissLatency::processor.switch1.core.inst 52591.963235 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches1.overallAvgMissLatency::total 52591.963235 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches1.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches1.blockedCycles::no_wbuffers 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches1.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches1.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches1.blockedCauses::no_wbuffers 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches1.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches1.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches1.avgBlocked::no_wbuffers nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches1.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches1.writebacks::writebacks 6 # number of writebacks (Count)
board.cache_hierarchy.l1icaches1.writebacks::total 6 # number of writebacks (Count)
board.cache_hierarchy.l1icaches1.demandMshrMisses::processor.switch1.core.inst 272 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches1.demandMshrMisses::total 272 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches1.overallMshrMisses::processor.switch1.core.inst 272 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches1.overallMshrMisses::total 272 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches1.demandMshrMissLatency::processor.switch1.core.inst 14214438 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches1.demandMshrMissLatency::total 14214438 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches1.overallMshrMissLatency::processor.switch1.core.inst 14214438 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches1.overallMshrMissLatency::total 14214438 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches1.demandMshrMissRate::processor.switch1.core.inst 0.000118 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches1.demandMshrMissRate::total 0.000118 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches1.overallMshrMissRate::processor.switch1.core.inst 0.000118 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches1.overallMshrMissRate::total 0.000118 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches1.demandAvgMshrMissLatency::processor.switch1.core.inst 52258.963235 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches1.demandAvgMshrMissLatency::total 52258.963235 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches1.overallAvgMshrMissLatency::processor.switch1.core.inst 52258.963235 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches1.overallAvgMshrMissLatency::total 52258.963235 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches1.replacements 6 # number of replacements (Count)
board.cache_hierarchy.l1icaches1.ReadReq.hits::processor.switch1.core.inst 2308375 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches1.ReadReq.hits::total 2308375 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches1.ReadReq.misses::processor.switch1.core.inst 272 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches1.ReadReq.misses::total 272 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches1.ReadReq.missLatency::processor.switch1.core.inst 14305014 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches1.ReadReq.missLatency::total 14305014 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches1.ReadReq.accesses::processor.switch1.core.inst 2308647 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches1.ReadReq.accesses::total 2308647 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches1.ReadReq.missRate::processor.switch1.core.inst 0.000118 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches1.ReadReq.missRate::total 0.000118 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches1.ReadReq.avgMissLatency::processor.switch1.core.inst 52591.963235 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches1.ReadReq.avgMissLatency::total 52591.963235 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches1.ReadReq.mshrMisses::processor.switch1.core.inst 272 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches1.ReadReq.mshrMisses::total 272 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches1.ReadReq.mshrMissLatency::processor.switch1.core.inst 14214438 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches1.ReadReq.mshrMissLatency::total 14214438 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches1.ReadReq.mshrMissRate::processor.switch1.core.inst 0.000118 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches1.ReadReq.mshrMissRate::total 0.000118 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches1.ReadReq.avgMshrMissLatency::processor.switch1.core.inst 52258.963235 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches1.ReadReq.avgMshrMissLatency::total 52258.963235 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches1.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches1.prefetcher.demandMshrMisses 272 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches1.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches1.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches1.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches1.tags.tagsInUse 107.698154 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches1.tags.totalRefs 2308647 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches1.tags.sampledRefs 272 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches1.tags.avgRefs 8487.672794 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches1.tags.warmupTick 17010966361644 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches1.tags.occupancies::processor.switch1.core.inst 107.698154 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches1.tags.avgOccs::processor.switch1.core.inst 0.210348 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches1.tags.avgOccs::total 0.210348 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches1.tags.occupanciesTaskId::1024 266 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches1.tags.ageTaskId_1024::2 266 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches1.tags.ratioOccsTaskId::1024 0.519531 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches1.tags.tagAccesses 18469448 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches1.tags.dataAccesses 18469448 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches1.tags.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.transDist::ReadReq 2047 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadResp 9930 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WriteReq 856 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WriteResp 856 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WritebackDirty 187 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WritebackClean 52 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::CleanEvict 6054 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq 78 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp 78 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq 7884 # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.apicbridge.mem_side_port::board.processor.start0.core.interrupts.int_responder 850 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.apicbridge.mem_side_port::total 850 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches0.mem_side_port::board.memory.mem_ctrl0.port 424 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches0.mem_side_port::board.memory.mem_ctrl1.port 470 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches0.mem_side_port::total 894 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches0.mem_side_port::board.bridge.cpu_side_port 3390 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches0.mem_side_port::board.memory.mem_ctrl0.port 3596 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches0.mem_side_port::board.memory.mem_ctrl1.port 3458 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches0.mem_side_port::board.processor.start0.core.interrupts.pio 12 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches0.mem_side_port::total 10456 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.processor.start0.core.mmu.itb.walker.port::board.memory.mem_ctrl0.port 30 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.processor.start0.core.mmu.itb.walker.port::board.memory.mem_ctrl1.port 38 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.processor.start0.core.mmu.itb.walker.port::total 68 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.processor.start0.core.mmu.dtb.walker.port::board.memory.mem_ctrl0.port 352 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.processor.start0.core.mmu.dtb.walker.port::board.memory.mem_ctrl1.port 246 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.processor.start0.core.mmu.dtb.walker.port::total 598 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.processor.start0.core.interrupts.int_requestor::board.processor.start1.core.interrupts.int_responder 2 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.processor.start0.core.interrupts.int_requestor::total 2 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches1.mem_side_port::board.memory.mem_ctrl0.port 264 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches1.mem_side_port::board.memory.mem_ctrl1.port 286 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches1.mem_side_port::total 550 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches1.mem_side_port::board.memory.mem_ctrl0.port 6897 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches1.mem_side_port::board.memory.mem_ctrl1.port 6816 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches1.mem_side_port::board.processor.start1.core.interrupts.pio 2 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches1.mem_side_port::total 13715 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.processor.start1.core.mmu.itb.walker.port::board.memory.mem_ctrl0.port 30 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.processor.start1.core.mmu.itb.walker.port::board.memory.mem_ctrl1.port 26 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.processor.start1.core.mmu.itb.walker.port::total 56 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.processor.start1.core.mmu.dtb.walker.port::board.memory.mem_ctrl0.port 348 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.processor.start1.core.mmu.dtb.walker.port::board.memory.mem_ctrl1.port 480 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.processor.start1.core.mmu.dtb.walker.port::total 828 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total 28017 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.apicbridge.mem_side_port::board.processor.start0.core.interrupts.int_responder 1700 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.apicbridge.mem_side_port::total 1700 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches0.mem_side_port::board.memory.mem_ctrl0.port 14080 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches0.mem_side_port::board.memory.mem_ctrl1.port 16000 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches0.mem_side_port::total 30080 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches0.mem_side_port::board.bridge.cpu_side_port 1695 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches0.mem_side_port::board.memory.mem_ctrl0.port 86912 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches0.mem_side_port::board.memory.mem_ctrl1.port 82752 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches0.mem_side_port::board.processor.start0.core.interrupts.pio 24 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches0.mem_side_port::total 171383 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.processor.start0.core.mmu.itb.walker.port::board.memory.mem_ctrl0.port 120 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.processor.start0.core.mmu.itb.walker.port::board.memory.mem_ctrl1.port 152 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.processor.start0.core.mmu.itb.walker.port::total 272 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.processor.start0.core.mmu.dtb.walker.port::board.memory.mem_ctrl0.port 1408 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.processor.start0.core.mmu.dtb.walker.port::board.memory.mem_ctrl1.port 984 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.processor.start0.core.mmu.dtb.walker.port::total 2392 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.processor.start0.core.interrupts.int_requestor::board.processor.start1.core.interrupts.int_responder 4 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.processor.start0.core.interrupts.int_requestor::total 4 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches1.mem_side_port::board.memory.mem_ctrl0.port 8512 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches1.mem_side_port::board.memory.mem_ctrl1.port 9280 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches1.mem_side_port::total 17792 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches1.mem_side_port::board.memory.mem_ctrl0.port 154688 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches1.mem_side_port::board.memory.mem_ctrl1.port 152256 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches1.mem_side_port::board.processor.start1.core.interrupts.pio 4 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches1.mem_side_port::total 306948 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.processor.start1.core.mmu.itb.walker.port::board.memory.mem_ctrl0.port 120 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.processor.start1.core.mmu.itb.walker.port::board.memory.mem_ctrl1.port 104 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.processor.start1.core.mmu.itb.walker.port::total 224 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.processor.start1.core.mmu.dtb.walker.port::board.memory.mem_ctrl0.port 1392 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.processor.start1.core.mmu.dtb.walker.port::board.memory.mem_ctrl1.port 1920 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.processor.start1.core.mmu.dtb.walker.port::total 3312 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total 534107 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops 5 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 320 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 10865 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean 0.035159 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev 0.184189 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 10483 96.48% 96.48% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 382 3.52% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::5 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 1 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 10865 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy 705627 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.reqLayer1.occupancy 3588926 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.reqLayer2.occupancy 3588612 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer2.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.reqLayer3.occupancy 3663 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer3.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.reqLayer4.occupancy 378876 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer4.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.reqLayer5.occupancy 666 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer5.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.reqLayer6.occupancy 998 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer6.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer0.occupancy 195184 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer10.occupancy 23155 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer10.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer11.occupancy 376288 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer11.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer3.occupancy 358299 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer3.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer4.occupancy 3053899 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer4.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer5.occupancy 28395 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer5.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer6.occupancy 257490 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer6.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer7.occupancy 565 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer7.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer8.occupancy 225137 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer8.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer9.occupancy 3847328 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer9.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests 14255 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 6616 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 59 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.iobus.transDist::ReadReq 1271 # Transaction distribution (Count)
board.iobus.transDist::ReadResp 1271 # Transaction distribution (Count)
board.iobus.transDist::WriteReq 849 # Transaction distribution (Count)
board.iobus.transDist::WriteResp 849 # Transaction distribution (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.com_1.pio 3390 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::total 3390 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.pc.south_bridge.io_apic.int_request::board.apicbridge.cpu_side_port 850 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.pc.south_bridge.io_apic.int_request::total 850 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount::total 4240 # Packet count per connected requestor and responder (Count)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.com_1.pio 1695 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::total 1695 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.pc.south_bridge.io_apic.int_request::board.apicbridge.cpu_side_port 1700 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.pc.south_bridge.io_apic.int_request::total 1700 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize::total 3395 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.iobus.reqLayer0.occupancy 328749 # Layer occupancy (ticks) (Tick)
board.iobus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.iobus.reqLayer9.occupancy 705627 # Layer occupancy (ticks) (Tick)
board.iobus.reqLayer9.utilization 0.0 # Layer utilization (Ratio)
board.iobus.respLayer0.occupancy 1382613 # Layer occupancy (ticks) (Tick)
board.iobus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
board.iobus.respLayer1.occupancy 141525 # Layer occupancy (ticks) (Tick)
board.iobus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
board.memory.mem_ctrl0.avgPriority_writebacks::samples 115.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_cache_hierarchy.l1dcaches0.prefetcher::samples 1052.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_cache_hierarchy.l1dcaches1.prefetcher::samples 2180.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.switch0.core.mmu.dtb.walker::samples 176.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.switch0.core.mmu.itb.walker::samples 15.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.switch0.core.inst::samples 201.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.switch0.core.data::samples 220.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.switch1.core.mmu.dtb.walker::samples 174.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.switch1.core.mmu.itb.walker::samples 15.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.switch1.core.inst::samples 129.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.switch1.core.data::samples 203.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.priorityMinLatency 0.000000017492 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000332083268 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 3 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 3 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 9079 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 50 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 4382 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 119 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 4382 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 119 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 17 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 4 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 1.13 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 21.72 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 380 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 4002 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 119 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 3811 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 434 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 112 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 8 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 3 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 3 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 4 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 4 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 4 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 4 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 4 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 4 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 4 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 5 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 4 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 4 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 4 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 4 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 4 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 3 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 3 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 3 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdPerTurnAround::samples 3 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl0.rdPerTurnAround::mean 1019 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl0.rdPerTurnAround::gmean 213.330132 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl0.rdPerTurnAround::stdev 1665.368728 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl0.rdPerTurnAround::0-63 2 66.67% 66.67% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl0.rdPerTurnAround::2880-2943 1 33.33% 100.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl0.rdPerTurnAround::total 3 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl0.wrPerTurnAround::samples 3 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::mean 17.666667 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::gmean 17.621736 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::stdev 1.527525 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::16 1 33.33% 33.33% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::18 1 33.33% 66.67% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::19 1 33.33% 100.00% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::total 3 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.bytesReadWrQ 1088 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 259168 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 7616 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 259168000.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 7616000.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 999971697 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap 222166.56 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.requestorReadBytes::cache_hierarchy.l1dcaches0.prefetcher 67328 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::cache_hierarchy.l1dcaches1.prefetcher 139520 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.switch0.core.mmu.dtb.walker 1408 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.switch0.core.mmu.itb.walker 120 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.switch0.core.inst 12864 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.switch0.core.data 14080 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.switch1.core.mmu.dtb.walker 1392 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.switch1.core.mmu.itb.walker 120 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.switch1.core.inst 8256 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.switch1.core.data 12992 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorWriteBytes::writebacks 3392 # Per-requestor bytes write to memory (Byte)
board.memory.mem_ctrl0.requestorReadRate::cache_hierarchy.l1dcaches0.prefetcher 67328000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::cache_hierarchy.l1dcaches1.prefetcher 139520000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.switch0.core.mmu.dtb.walker 1408000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.switch0.core.mmu.itb.walker 120000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.switch0.core.inst 12864000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.switch0.core.data 14080000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.switch1.core.mmu.dtb.walker 1392000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.switch1.core.mmu.itb.walker 120000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.switch1.core.inst 8256000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.switch1.core.data 12992000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorWriteRate::writebacks 3392000.000000000000 # Per-requestor bytes write to memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadAccesses::cache_hierarchy.l1dcaches0.prefetcher 1052 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::cache_hierarchy.l1dcaches1.prefetcher 2180 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.switch0.core.mmu.dtb.walker 176 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.switch0.core.mmu.itb.walker 15 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.switch0.core.inst 204 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.switch0.core.data 232 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.switch1.core.mmu.dtb.walker 174 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.switch1.core.mmu.itb.walker 15 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.switch1.core.inst 131 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.switch1.core.data 203 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorWriteAccesses::writebacks 119 # Per-requestor write serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadTotalLat::cache_hierarchy.l1dcaches0.prefetcher 30134834 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::cache_hierarchy.l1dcaches1.prefetcher 61289681 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.switch0.core.mmu.dtb.walker 5981049 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.switch0.core.mmu.itb.walker 524782 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.switch0.core.inst 6167601 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.switch0.core.data 6765957 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.switch1.core.mmu.dtb.walker 5797994 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.switch1.core.mmu.itb.walker 488275 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.switch1.core.inst 3369911 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.switch1.core.data 5970330 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorWriteTotalLat::writebacks 4075595800 # Per-requestor write total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadAvgLat::cache_hierarchy.l1dcaches0.prefetcher 28645.28 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::cache_hierarchy.l1dcaches1.prefetcher 28114.53 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.switch0.core.mmu.dtb.walker 33983.23 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.switch0.core.mmu.itb.walker 34985.47 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.switch0.core.inst 30233.34 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.switch0.core.data 29163.61 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.switch1.core.mmu.dtb.walker 33321.80 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.switch1.core.mmu.itb.walker 32551.67 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.switch1.core.inst 25724.51 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.switch1.core.data 29410.49 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorWriteAvgLat::writebacks 34248704.20 # Per-requestor write average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.dram.bytesRead::cache_hierarchy.l1dcaches0.prefetcher 67328 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::cache_hierarchy.l1dcaches1.prefetcher 139520 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.switch0.core.mmu.dtb.walker 1408 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.switch0.core.mmu.itb.walker 120 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.switch0.core.inst 13056 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.switch0.core.data 14848 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.switch1.core.mmu.dtb.walker 1392 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.switch1.core.mmu.itb.walker 120 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.switch1.core.inst 8384 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.switch1.core.data 12992 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::total 259168 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesInstRead::processor.switch0.core.inst 13056 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesInstRead::processor.switch1.core.inst 8384 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesInstRead::total 21440 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesWritten::writebacks 6976 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl0.dram.bytesWritten::total 6976 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl0.dram.numReads::cache_hierarchy.l1dcaches0.prefetcher 1052 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::cache_hierarchy.l1dcaches1.prefetcher 2180 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.switch0.core.mmu.dtb.walker 176 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.switch0.core.mmu.itb.walker 15 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.switch0.core.inst 204 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.switch0.core.data 232 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.switch1.core.mmu.dtb.walker 174 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.switch1.core.mmu.itb.walker 15 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.switch1.core.inst 131 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.switch1.core.data 203 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::total 4382 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numWrites::writebacks 109 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numWrites::total 109 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.bwRead::cache_hierarchy.l1dcaches0.prefetcher 67328000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::cache_hierarchy.l1dcaches1.prefetcher 139520000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.switch0.core.mmu.dtb.walker 1408000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.switch0.core.mmu.itb.walker 120000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.switch0.core.inst 13056000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.switch0.core.data 14848000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.switch1.core.mmu.dtb.walker 1392000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.switch1.core.mmu.itb.walker 120000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.switch1.core.inst 8384000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.switch1.core.data 12992000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::total 259168000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwInstRead::processor.switch0.core.inst 13056000 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwInstRead::processor.switch1.core.inst 8384000 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwInstRead::total 21440000 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwWrite::writebacks 6976000 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwWrite::total 6976000 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::writebacks 6976000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::cache_hierarchy.l1dcaches0.prefetcher 67328000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::cache_hierarchy.l1dcaches1.prefetcher 139520000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.switch0.core.mmu.dtb.walker 1408000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.switch0.core.mmu.itb.walker 120000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.switch0.core.inst 13056000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.switch0.core.data 14848000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.switch1.core.mmu.dtb.walker 1392000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.switch1.core.mmu.itb.walker 120000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.switch1.core.inst 8384000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.switch1.core.data 12992000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::total 266144000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.readBursts 4365 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 53 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 225 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 86 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 51 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 9 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 5 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 20 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 26 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 24 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 27 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 29 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 20 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 18 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 8 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 307 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 154 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 146 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 145 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 141 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 162 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 135 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 140 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 198 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 162 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 165 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 248 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 285 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 260 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 277 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 269 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 267 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 226 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 130 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 6 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 2 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 2 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 7 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 2 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 3 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 4 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 2 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 3 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 1 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 5 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 3 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 1 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 2 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 3 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 1 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 3 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 1 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 1 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 1 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 50137834 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 14544180 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 126490414 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat 11486.33 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat 3332.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat 28978.33 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 3453 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 26 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate 79.11 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate 49.06 # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.bytesPerActivate::samples 937 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::mean 300.601921 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::gmean 161.485521 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::stdev 361.348561 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::0-127 413 44.08% 44.08% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::128-255 250 26.68% 70.76% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::256-383 49 5.23% 75.99% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::384-511 22 2.35% 78.34% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::512-639 11 1.17% 79.51% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::640-767 15 1.60% 81.11% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::768-895 5 0.53% 81.64% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::896-1023 9 0.96% 82.60% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::1024-1151 163 17.40% 100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::total 937 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.dramBytesRead 279360 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 3392 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 279.360000 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 3.392000 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 1.47 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 1.45 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.02 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate 78.75 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 614394.144000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 1081889.071200 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 3168052.272000 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 96721.296000 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 86509510.348800 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 295811875.900800 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 122184370.694400 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 509466813.727200 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 509.466814 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 370804169 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 44800000 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 584395831 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 849859.920000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 1497576.729600 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 8804716.704000 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 28308.672000 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 86509510.348800 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 402213520.212000 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 48689188.531200 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 548592681.117600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 548.592681 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 145470233 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 44800000 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 809729767 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.avgPriority_writebacks::samples 96.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_cache_hierarchy.l1dcaches0.prefetcher::samples 1086.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_cache_hierarchy.l1dcaches1.prefetcher::samples 2249.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.switch0.core.mmu.dtb.walker::samples 123.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.switch0.core.mmu.itb.walker::samples 19.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.switch0.core.inst::samples 212.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.switch0.core.data::samples 141.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.switch1.core.mmu.dtb.walker::samples 240.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.switch1.core.mmu.itb.walker::samples 13.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.switch1.core.inst::samples 137.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.switch1.core.data::samples 107.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.priorityMinLatency 0.000000017492 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000385159472 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 2 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 2 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 8990 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 34 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 4350 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 100 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 4350 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 100 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 23 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 4 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 1.08 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 20.72 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 395 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 3955 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 100 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 3912 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 401 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 13 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 1 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::22 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::23 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::24 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::25 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::26 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::27 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::28 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::29 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::34 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::35 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::36 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::37 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::38 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::39 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::40 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::41 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::42 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::43 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::44 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::45 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::46 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::47 3 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::48 3 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 3 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::50 3 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::51 3 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::52 3 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::53 3 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::54 3 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::55 3 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::56 3 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::57 3 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::58 3 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::59 3 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::60 2 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::61 2 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::62 2 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::63 2 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::64 2 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdPerTurnAround::samples 2 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.rdPerTurnAround::mean 1517 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.rdPerTurnAround::gmean 415.461190 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.rdPerTurnAround::stdev 2063.337588 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.rdPerTurnAround::0-63 1 50.00% 50.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.rdPerTurnAround::2944-3007 1 50.00% 100.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.rdPerTurnAround::total 2 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.wrPerTurnAround::samples 2 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::18 2 100.00% 100.00% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::total 2 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.bytesReadWrQ 1472 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 256280 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 6400 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 256280000.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 6400000.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 999813189 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap 224677.12 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.requestorReadBytes::cache_hierarchy.l1dcaches0.prefetcher 69504 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::cache_hierarchy.l1dcaches1.prefetcher 143936 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.switch0.core.mmu.dtb.walker 984 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.switch0.core.mmu.itb.walker 152 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.switch0.core.inst 13568 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.switch0.core.data 9024 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.switch1.core.mmu.dtb.walker 1920 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.switch1.core.mmu.itb.walker 104 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.switch1.core.inst 8768 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.switch1.core.data 6848 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorWriteBytes::writebacks 2304 # Per-requestor bytes write to memory (Byte)
board.memory.mem_ctrl1.requestorReadRate::cache_hierarchy.l1dcaches0.prefetcher 69504000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::cache_hierarchy.l1dcaches1.prefetcher 143936000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.switch0.core.mmu.dtb.walker 984000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.switch0.core.mmu.itb.walker 152000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.switch0.core.inst 13568000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.switch0.core.data 9024000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.switch1.core.mmu.dtb.walker 1920000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.switch1.core.mmu.itb.walker 104000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.switch1.core.inst 8768000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.switch1.core.data 6848000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorWriteRate::writebacks 2304000.000000000000 # Per-requestor bytes write to memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadAccesses::cache_hierarchy.l1dcaches0.prefetcher 1086 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::cache_hierarchy.l1dcaches1.prefetcher 2249 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.switch0.core.mmu.dtb.walker 123 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.switch0.core.mmu.itb.walker 19 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.switch0.core.inst 220 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.switch0.core.data 152 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.switch1.core.mmu.dtb.walker 240 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.switch1.core.mmu.itb.walker 13 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.switch1.core.inst 141 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.switch1.core.data 107 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorWriteAccesses::writebacks 100 # Per-requestor write serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadTotalLat::cache_hierarchy.l1dcaches0.prefetcher 31208304 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::cache_hierarchy.l1dcaches1.prefetcher 64095340 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.switch0.core.mmu.dtb.walker 3417143 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.switch0.core.mmu.itb.walker 458463 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.switch0.core.inst 6400116 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.switch0.core.data 4325631 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.switch1.core.mmu.dtb.walker 7686555 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.switch1.core.mmu.itb.walker 279218 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.switch1.core.inst 4345618 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.switch1.core.data 3540213 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorWriteTotalLat::writebacks 3424996617 # Per-requestor write total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadAvgLat::cache_hierarchy.l1dcaches0.prefetcher 28736.93 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::cache_hierarchy.l1dcaches1.prefetcher 28499.48 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.switch0.core.mmu.dtb.walker 27781.65 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.switch0.core.mmu.itb.walker 24129.63 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.switch0.core.inst 29091.44 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.switch0.core.data 28458.10 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.switch1.core.mmu.dtb.walker 32027.31 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.switch1.core.mmu.itb.walker 21478.31 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.switch1.core.inst 30819.99 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.switch1.core.data 33086.10 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorWriteAvgLat::writebacks 34249966.17 # Per-requestor write average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.dram.bytesRead::cache_hierarchy.l1dcaches0.prefetcher 69504 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::cache_hierarchy.l1dcaches1.prefetcher 143936 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.switch0.core.mmu.dtb.walker 984 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.switch0.core.mmu.itb.walker 152 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.switch0.core.inst 14080 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.switch0.core.data 9728 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.switch1.core.mmu.dtb.walker 1920 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.switch1.core.mmu.itb.walker 104 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.switch1.core.inst 9024 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.switch1.core.data 6848 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::total 256280 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::processor.switch0.core.inst 14080 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::processor.switch1.core.inst 9024 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::total 23104 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesWritten::writebacks 4992 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl1.dram.bytesWritten::total 4992 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl1.dram.numReads::cache_hierarchy.l1dcaches0.prefetcher 1086 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::cache_hierarchy.l1dcaches1.prefetcher 2249 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.switch0.core.mmu.dtb.walker 123 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.switch0.core.mmu.itb.walker 19 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.switch0.core.inst 220 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.switch0.core.data 152 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.switch1.core.mmu.dtb.walker 240 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.switch1.core.mmu.itb.walker 13 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.switch1.core.inst 141 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.switch1.core.data 107 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::total 4350 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numWrites::writebacks 78 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numWrites::total 78 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.bwRead::cache_hierarchy.l1dcaches0.prefetcher 69504000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::cache_hierarchy.l1dcaches1.prefetcher 143936000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.switch0.core.mmu.dtb.walker 984000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.switch0.core.mmu.itb.walker 152000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.switch0.core.inst 14080000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.switch0.core.data 9728000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.switch1.core.mmu.dtb.walker 1920000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.switch1.core.mmu.itb.walker 104000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.switch1.core.inst 9024000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.switch1.core.data 6848000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::total 256280000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::processor.switch0.core.inst 14080000 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::processor.switch1.core.inst 9024000 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::total 23104000 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwWrite::writebacks 4992000 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwWrite::total 4992000 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::writebacks 4992000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::cache_hierarchy.l1dcaches0.prefetcher 69504000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::cache_hierarchy.l1dcaches1.prefetcher 143936000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.switch0.core.mmu.dtb.walker 984000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.switch0.core.mmu.itb.walker 152000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.switch0.core.inst 14080000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.switch0.core.data 9728000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.switch1.core.mmu.dtb.walker 1920000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.switch1.core.mmu.itb.walker 104000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.switch1.core.inst 9024000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.switch1.core.data 6848000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::total 261272000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.readBursts 4327 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 36 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 187 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 84 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 32 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 13 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 6 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 17 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 20 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 25 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 12 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 154 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 11 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 12 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 9 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 183 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 144 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 147 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 198 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 135 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 233 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 132 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 140 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 199 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 162 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 165 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 190 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 282 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 261 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 282 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 266 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 270 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 225 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 131 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 1 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 9 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 2 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 3 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 1 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 4 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 3 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 2 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 1 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 2 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 1 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 1 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 3 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 2 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 1 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 50068717 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 14417564 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 125756601 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat 11571.23 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat 3332.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat 29063.23 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 3415 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 18 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate 78.92 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate 50.00 # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.bytesPerActivate::samples 928 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::mean 299.724138 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::gmean 159.826704 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::stdev 362.690166 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::0-127 415 44.72% 44.72% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::128-255 248 26.72% 71.44% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::256-383 42 4.53% 75.97% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::384-511 22 2.37% 78.34% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::512-639 9 0.97% 79.31% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::640-767 14 1.51% 80.82% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::768-895 7 0.75% 81.57% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::896-1023 11 1.19% 82.76% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::1024-1151 160 17.24% 100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::total 928 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.dramBytesRead 276928 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 2304 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 276.928000 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 2.304000 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 1.45 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 1.44 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.01 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate 78.68 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 547340.976000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 963514.440000 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 2896504.934400 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 58976.400000 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 86509510.348800 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 295646068.250400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 122276541.811200 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 508898457.160800 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 508.898457 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 371224520 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 44800000 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 583975480 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 902878.704000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 1591175.275200 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 8972033.750400 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 25949.616000 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 86509510.348800 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 419855296.677600 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 36469310.438400 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 554326154.810400 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 554.326155 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 108077750 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 44800000 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 847122250 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.bad_addr.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.com_1.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.default_bus.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.empty_isa.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.fake_com_2.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.fake_com_3.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.fake_com_4.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.fake_floppy.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.pci_bus.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.pci_host.config_error.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.pci_host.down_to_up.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.pci_host.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.pci_host.up_to_down.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.cmos.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.dma1.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.ide.disks.IdeDisk.dmaReadFullPages 0 # Number of full page size DMA reads (not PRD). (Count)
board.pc.south_bridge.ide.disks.IdeDisk.dmaReadBytes 0 # Number of bytes transfered via DMA reads (not PRD). (Byte)
board.pc.south_bridge.ide.disks.IdeDisk.dmaReadTxs 0 # Number of DMA read transactions (not PRD). (Count)
board.pc.south_bridge.ide.disks.IdeDisk.dmaWriteFullPages 0 # Number of full page size DMA writes. (Count)
board.pc.south_bridge.ide.disks.IdeDisk.dmaWriteBytes 0 # Number of bytes transfered via DMA writes. (Byte)
board.pc.south_bridge.ide.disks.IdeDisk.dmaWriteTxs 0 # Number of DMA write transactions. (Count)
board.pc.south_bridge.ide.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.io_apic.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.keyboard.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.pic1.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.pic2.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.pit.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.speaker.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start0.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start0.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start0.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start0.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start0.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start0.core.numVMExits 0 # total number of KVM exits (Count)
board.processor.start0.core.numVMHalfEntries 0 # number of KVM entries to finalize pending operations (Count)
board.processor.start0.core.numExitSignal 0 # exits due to signal delivery (Count)
board.processor.start0.core.numMMIO 0 # number of VM exits due to memory mapped IO (Count)
board.processor.start0.core.numCoalescedMMIO 0 # number of coalesced memory mapped IO requests (Count)
board.processor.start0.core.numIO 0 # number of VM exits due to legacy IO (Count)
board.processor.start0.core.numHalt 0 # number of VM exits due to wait for interrupt instructions (Count)
board.processor.start0.core.numInterrupts 0 # number of interrupts delivered (Count)
board.processor.start0.core.numHypercalls 0 # number of hypercalls (Count)
board.processor.start0.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start0.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start0.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start0.core.commitStats0.numUserInsts 0 # Numbrer of instructions committed in user mode (Count)
board.processor.start0.core.commitStats0.numUserOps 0 # Number of ops committed in user mode (Count)
board.processor.start0.core.commitStats0.ratioUserInsts nan # Ratio of instructions committed in user mode (Ratio)
board.processor.start0.core.commitStats0.ratioUserOps nan # Ratio of ops committed in user mode (Ratio)
board.processor.start0.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start0.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start0.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start0.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start0.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start0.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start0.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start0.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start0.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdSha3 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdSm4e 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdCrc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdDotProd 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdBf16Add 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdBf16Cmp 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdBf16Cvt 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdBf16DotProd 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdBf16MatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdBf16Mult 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::SimdBf16MultAcc 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::Bf16Cvt 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::System 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start0.core.commitStats0.functionCalls 0 # Number of function calls committed (Count)
board.processor.start0.core.commitStats0.numCallsReturns 0 # Number of function calls and returns committed (Count)
board.processor.start0.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start0.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start0.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start0.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start0.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start0.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start0.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start0.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start0.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start0.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start0.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start0.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start0.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start0.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start0.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start0.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start0.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start0.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start0.core.mmu.dtb.exAccesses 0 # TLB accesses on execute (instr) requests (Count)
board.processor.start0.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start0.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start0.core.mmu.dtb.exMisses 0 # TLB misses on execute (instr) requests (Count)
board.processor.start0.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start0.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start0.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start0.core.mmu.itb.exAccesses 0 # TLB accesses on execute (instr) requests (Count)
board.processor.start0.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start0.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start0.core.mmu.itb.exMisses 0 # TLB misses on execute (instr) requests (Count)
board.processor.start0.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start0.core.power_state.pwrStateResidencyTicks::OFF 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start0.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start0.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start0.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.start1.core.numCycles 0 # Number of cpu cycles simulated (Cycle)
board.processor.start1.core.cpi nan # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.start1.core.ipc nan # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.start1.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.start1.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.start1.core.numVMExits 0 # total number of KVM exits (Count)
board.processor.start1.core.numVMHalfEntries 0 # number of KVM entries to finalize pending operations (Count)
board.processor.start1.core.numExitSignal 0 # exits due to signal delivery (Count)
board.processor.start1.core.numMMIO 0 # number of VM exits due to memory mapped IO (Count)
board.processor.start1.core.numCoalescedMMIO 0 # number of coalesced memory mapped IO requests (Count)
board.processor.start1.core.numIO 0 # number of VM exits due to legacy IO (Count)
board.processor.start1.core.numHalt 0 # number of VM exits due to wait for interrupt instructions (Count)
board.processor.start1.core.numInterrupts 0 # number of interrupts delivered (Count)
board.processor.start1.core.numHypercalls 0 # number of hypercalls (Count)
board.processor.start1.core.commitStats0.numOps 0 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.start1.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.start1.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.start1.core.commitStats0.numUserInsts 0 # Numbrer of instructions committed in user mode (Count)
board.processor.start1.core.commitStats0.numUserOps 0 # Number of ops committed in user mode (Count)
board.processor.start1.core.commitStats0.ratioUserInsts nan # Ratio of instructions committed in user mode (Ratio)
board.processor.start1.core.commitStats0.ratioUserOps nan # Ratio of ops committed in user mode (Ratio)
board.processor.start1.core.commitStats0.cpi nan # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.start1.core.commitStats0.ipc nan # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.start1.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.start1.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.start1.core.commitStats0.numIntInsts 0 # Number of integer instructions (Count)
board.processor.start1.core.commitStats0.numLoadInsts 0 # Number of load instructions (Count)
board.processor.start1.core.commitStats0.numStoreInsts 0 # Number of store instructions (Count)
board.processor.start1.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.start1.core.commitStats0.committedInstType::No_OpClass 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::IntAlu 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::IntMult 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::IntDiv 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::FloatAdd 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::FloatCmp 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::FloatCvt 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::FloatMult 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::FloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::FloatDiv 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::FloatMisc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::FloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdAdd 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdAddAcc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdAlu 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdCmp 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdCvt 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdMisc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdMult 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdMultAcc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdShift 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdShiftAcc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdDiv 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdSqrt 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatAdd 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatAlu 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatCmp 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatCvt 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatDiv 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatMisc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatMult 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatSqrt 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdReduceAlu 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdAes 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdAesMix 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdSha1Hash 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdSha1Hash2 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdSha256Hash 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdSha256Hash2 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdShaSigma2 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdShaSigma3 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdSha3 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdSm4e 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdCrc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdPredAlu 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdDotProd 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::Matrix 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::MatrixMov 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::MatrixOP 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::MemRead 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::MemWrite 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::FloatMemRead 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::FloatMemWrite 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::InstPrefetch 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdUnitStrideStore 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdStridedLoad 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdStridedStore 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdIndexedLoad 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdIndexedStore 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdStrideSegmentedLoad 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdStrideSegmentedStore 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdExt 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdFloatExt 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdConfig 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdBf16Add 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdBf16Cmp 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdBf16Cvt 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdBf16DotProd 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdBf16MatMultAcc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdBf16Mult 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::SimdBf16MultAcc 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::Bf16Cvt 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::System 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.committedInstType::total 0 # Class of committed instruction. (Count)
board.processor.start1.core.commitStats0.functionCalls 0 # Number of function calls committed (Count)
board.processor.start1.core.commitStats0.numCallsReturns 0 # Number of function calls and returns committed (Count)
board.processor.start1.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.start1.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.start1.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.start1.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.start1.core.executeStats0.numStoreInsts 0 # Number of stores executed (Count)
board.processor.start1.core.executeStats0.instRate nan # Inst execution rate ((Count/Cycle))
board.processor.start1.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.start1.core.executeStats0.numMemRefs 0 # Number of memory refs (Count)
board.processor.start1.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.start1.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.start1.core.fetchStats0.numInsts 0 # Number of instructions fetched (thread level) (Count)
board.processor.start1.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.start1.core.fetchStats0.fetchRate nan # Number of inst fetches per cycle ((Count/Cycle))
board.processor.start1.core.fetchStats0.branchRate nan # Number of branch fetches per cycle (Ratio)
board.processor.start1.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.start1.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.start1.core.mmu.dtb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start1.core.mmu.dtb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start1.core.mmu.dtb.exAccesses 0 # TLB accesses on execute (instr) requests (Count)
board.processor.start1.core.mmu.dtb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start1.core.mmu.dtb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start1.core.mmu.dtb.exMisses 0 # TLB misses on execute (instr) requests (Count)
board.processor.start1.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start1.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.start1.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.start1.core.mmu.itb.exAccesses 0 # TLB accesses on execute (instr) requests (Count)
board.processor.start1.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.start1.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.start1.core.mmu.itb.exMisses 0 # TLB misses on execute (instr) requests (Count)
board.processor.start1.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start1.core.power_state.pwrStateResidencyTicks::OFF 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.start1.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.start1.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.start1.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.switch0.core.numCycles 3003002 # Number of cpu cycles simulated (Cycle)
board.processor.switch0.core.cpi 2.908369 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch0.core.ipc 0.343835 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch0.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch0.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch0.core.issuedInstType_0::No_OpClass 30597 1.61% 1.61% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::IntAlu 1069095 56.31% 57.92% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::IntMult 99 0.01% 57.92% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::IntDiv 353 0.02% 57.94% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::FloatAdd 48954 2.58% 60.52% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::FloatCmp 0 0.00% 60.52% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::FloatCvt 0 0.00% 60.52% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::FloatMult 0 0.00% 60.52% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::FloatMultAcc 0 0.00% 60.52% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::FloatDiv 0 0.00% 60.52% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::FloatMisc 0 0.00% 60.52% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::FloatSqrt 0 0.00% 60.52% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdAdd 0 0.00% 60.52% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdAddAcc 0 0.00% 60.52% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdAlu 52990 2.79% 63.31% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdCmp 0 0.00% 63.31% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdCvt 0 0.00% 63.31% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdMisc 26044 1.37% 64.68% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdMult 0 0.00% 64.68% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdMultAcc 0 0.00% 64.68% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdMatMultAcc 0 0.00% 64.68% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdShift 0 0.00% 64.68% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdShiftAcc 0 0.00% 64.68% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdDiv 0 0.00% 64.68% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdSqrt 0 0.00% 64.68% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatAdd 160899 8.47% 73.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatAlu 0 0.00% 73.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatCmp 6736 0.35% 73.51% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatCvt 28403 1.50% 75.01% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatDiv 6737 0.35% 75.36% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatMisc 0 0.00% 75.36% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatMult 101280 5.33% 80.69% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatMultAcc 0 0.00% 80.69% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatMatMultAcc 0 0.00% 80.69% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatSqrt 6737 0.35% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdReduceAdd 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdReduceAlu 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdReduceCmp 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatReduceAdd 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatReduceCmp 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdAes 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdAesMix 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdSha1Hash 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdSha1Hash2 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdSha256Hash 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdSha256Hash2 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdShaSigma2 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdShaSigma3 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdSha3 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdSm4e 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdCrc 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdPredAlu 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdDotProd 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::Matrix 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::MatrixMov 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::MatrixOP 0 0.00% 81.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::MemRead 83134 4.38% 85.43% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::MemWrite 52591 2.77% 88.20% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::FloatMemRead 183685 9.67% 97.87% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::FloatMemWrite 40416 2.13% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdStrideSegmentedLoad 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdStrideSegmentedStore 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdExt 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdBf16Add 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdBf16Cmp 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdBf16Cvt 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdBf16DotProd 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdBf16MatMultAcc 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdBf16Mult 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::SimdBf16MultAcc 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::Bf16Cvt 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::System 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.issuedInstType_0::total 1898750 # Number of insts issued per FU, per thread (Count)
board.processor.switch0.core.commitStats0.numInsts 1032538 # Number of instructions committed (thread level) (Count)
board.processor.switch0.core.commitStats0.numOps 1898750 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch0.core.commitStats0.numInstsNotNOP 1032538 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch0.core.commitStats0.numOpsNotNOP 1898750 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch0.core.commitStats0.numUserInsts 791188 # Numbrer of instructions committed in user mode (Count)
board.processor.switch0.core.commitStats0.numUserOps 1408240 # Number of ops committed in user mode (Count)
board.processor.switch0.core.commitStats0.ratioUserInsts 0.766256 # Ratio of instructions committed in user mode (Ratio)
board.processor.switch0.core.commitStats0.ratioUserOps 0.741667 # Ratio of ops committed in user mode (Ratio)
board.processor.switch0.core.commitStats0.cpi 2.908369 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch0.core.commitStats0.ipc 0.343835 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch0.core.commitStats0.numMemRefs 359826 # Number of memory references committed (Count)
board.processor.switch0.core.commitStats0.numFpInsts 850161 # Number of float instructions (Count)
board.processor.switch0.core.commitStats0.numIntInsts 1260607 # Number of integer instructions (Count)
board.processor.switch0.core.commitStats0.numLoadInsts 266819 # Number of load instructions (Count)
board.processor.switch0.core.commitStats0.numStoreInsts 93007 # Number of store instructions (Count)
board.processor.switch0.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch0.core.commitStats0.committedInstType::No_OpClass 30597 1.61% 1.61% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::IntAlu 1069095 56.31% 57.92% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::IntMult 99 0.01% 57.92% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::IntDiv 353 0.02% 57.94% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::FloatAdd 48954 2.58% 60.52% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::FloatCmp 0 0.00% 60.52% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::FloatCvt 0 0.00% 60.52% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::FloatMult 0 0.00% 60.52% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 60.52% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::FloatDiv 0 0.00% 60.52% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::FloatMisc 0 0.00% 60.52% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 60.52% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdAdd 0 0.00% 60.52% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 60.52% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdAlu 52990 2.79% 63.31% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdCmp 0 0.00% 63.31% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdCvt 0 0.00% 63.31% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdMisc 26044 1.37% 64.68% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdMult 0 0.00% 64.68% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 64.68% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 64.68% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdShift 0 0.00% 64.68% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 64.68% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdDiv 0 0.00% 64.68% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 64.68% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatAdd 160899 8.47% 73.16% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 73.16% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatCmp 6736 0.35% 73.51% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatCvt 28403 1.50% 75.01% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatDiv 6737 0.35% 75.36% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 75.36% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatMult 101280 5.33% 80.69% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 80.69% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 80.69% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatSqrt 6737 0.35% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdAes 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdSha3 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdSm4e 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdCrc 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdDotProd 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::Matrix 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::MatrixMov 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::MatrixOP 0 0.00% 81.05% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::MemRead 83134 4.38% 85.43% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::MemWrite 52591 2.77% 88.20% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::FloatMemRead 183685 9.67% 97.87% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::FloatMemWrite 40416 2.13% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdBf16Add 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdBf16Cmp 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdBf16Cvt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdBf16DotProd 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdBf16MatMultAcc 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdBf16Mult 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::SimdBf16MultAcc 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::Bf16Cvt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::System 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedInstType::total 1898750 # Class of committed instruction. (Count)
board.processor.switch0.core.commitStats0.committedControl::IsControl 116233 # Class of control type instructions committed (Count)
board.processor.switch0.core.commitStats0.committedControl::IsDirectControl 85148 # Class of control type instructions committed (Count)
board.processor.switch0.core.commitStats0.committedControl::IsIndirectControl 31079 # Class of control type instructions committed (Count)
board.processor.switch0.core.commitStats0.committedControl::IsCondControl 59190 # Class of control type instructions committed (Count)
board.processor.switch0.core.commitStats0.committedControl::IsUncondControl 57043 # Class of control type instructions committed (Count)
board.processor.switch0.core.commitStats0.committedControl::IsCall 17606 # Class of control type instructions committed (Count)
board.processor.switch0.core.commitStats0.committedControl::IsReturn 17607 # Class of control type instructions committed (Count)
board.processor.switch0.core.commitStats0.functionCalls 17606 # Number of function calls committed (Count)
board.processor.switch0.core.commitStats0.numCallsReturns 35213 # Number of function calls and returns committed (Count)
board.processor.switch0.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.switch0.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.switch0.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.switch0.core.exec_context.thread_0.numBusyCycles 3003002 # Number of busy cycles (Cycle)
board.processor.switch0.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.switch0.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.switch0.core.executeStats0.numInsts 1032538 # Number of executed instructions (Count)
board.processor.switch0.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch0.core.executeStats0.numBranches 116233 # Number of branches executed (Count)
board.processor.switch0.core.executeStats0.numLoadInsts 266819 # Number of load instructions executed (Count)
board.processor.switch0.core.executeStats0.numStoreInsts 93007 # Number of stores executed (Count)
board.processor.switch0.core.executeStats0.instRate 0.343835 # Inst execution rate ((Count/Cycle))
board.processor.switch0.core.executeStats0.numCCRegReads 383660 # Number of times the CC registers were read (Count)
board.processor.switch0.core.executeStats0.numCCRegWrites 407212 # Number of times the CC registers were written (Count)
board.processor.switch0.core.executeStats0.numFpAluAccesses 850161 # Number of float alu accesses (Count)
board.processor.switch0.core.executeStats0.numFpRegReads 1294454 # Number of times the floating registers were read (Count)
board.processor.switch0.core.executeStats0.numFpRegWrites 780892 # Number of times the floating registers were written (Count)
board.processor.switch0.core.executeStats0.numIntAluAccesses 1260607 # Number of integer alu accesses (Count)
board.processor.switch0.core.executeStats0.numIntRegReads 1306329 # Number of times the integer registers were read (Count)
board.processor.switch0.core.executeStats0.numIntRegWrites 815234 # Number of times the integer registers were written (Count)
board.processor.switch0.core.executeStats0.numMemRefs 359826 # Number of memory refs (Count)
board.processor.switch0.core.executeStats0.numMiscRegReads 662464 # Number of times the Misc registers were read (Count)
board.processor.switch0.core.executeStats0.numMiscRegWrites 1007 # Number of times the Misc registers were written (Count)
board.processor.switch0.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch0.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch0.core.fetchStats0.numInsts 1032538 # Number of instructions fetched (thread level) (Count)
board.processor.switch0.core.fetchStats0.numOps 1898750 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch0.core.fetchStats0.fetchRate 0.343835 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch0.core.fetchStats0.numBranches 116233 # Number of branches fetched (Count)
board.processor.switch0.core.fetchStats0.branchRate 0.038706 # Number of branch fetches per cycle (Ratio)
board.processor.switch0.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch0.core.mmu.dtb.rdAccesses 265624 # TLB accesses on read requests (Count)
board.processor.switch0.core.mmu.dtb.wrAccesses 92585 # TLB accesses on write requests (Count)
board.processor.switch0.core.mmu.dtb.exAccesses 0 # TLB accesses on execute (instr) requests (Count)
board.processor.switch0.core.mmu.dtb.rdMisses 76 # TLB misses on read requests (Count)
board.processor.switch0.core.mmu.dtb.wrMisses 2 # TLB misses on write requests (Count)
board.processor.switch0.core.mmu.dtb.exMisses 0 # TLB misses on execute (instr) requests (Count)
board.processor.switch0.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch0.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch0.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch0.core.mmu.itb.exAccesses 1406011 # TLB accesses on execute (instr) requests (Count)
board.processor.switch0.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch0.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch0.core.mmu.itb.exMisses 10 # TLB misses on execute (instr) requests (Count)
board.processor.switch0.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch0.core.power_state.pwrStateResidencyTicks::OFF 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch0.core.thread_0.numInsts 1032538 # Number of Instructions committed (Count)
board.processor.switch0.core.thread_0.numOps 1898750 # Number of Ops committed (Count)
board.processor.switch0.core.thread_0.numMemRefs 359826 # Number of Memory References (Count)
board.processor.switch1.core.numCycles 3003002 # Number of cpu cycles simulated (Cycle)
board.processor.switch1.core.cpi 1.811713 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.switch1.core.ipc 0.551964 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.switch1.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.switch1.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.switch1.core.issuedInstType_0::No_OpClass 42376 1.44% 1.44% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::IntAlu 1466209 49.69% 51.12% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::IntMult 92 0.00% 51.13% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::IntDiv 328 0.01% 51.14% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::FloatAdd 102051 3.46% 54.60% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::FloatCmp 0 0.00% 54.60% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::FloatCvt 0 0.00% 54.60% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::FloatMult 0 0.00% 54.60% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::FloatMultAcc 0 0.00% 54.60% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::FloatDiv 0 0.00% 54.60% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::FloatMisc 0 0.00% 54.60% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::FloatSqrt 0 0.00% 54.60% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdAdd 0 0.00% 54.60% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdAddAcc 0 0.00% 54.60% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdAlu 110860 3.76% 58.35% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdCmp 0 0.00% 58.35% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdCvt 0 0.00% 58.35% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdMisc 54552 1.85% 60.20% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdMult 0 0.00% 60.20% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdMultAcc 0 0.00% 60.20% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdMatMultAcc 0 0.00% 60.20% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdShift 0 0.00% 60.20% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdShiftAcc 0 0.00% 60.20% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdDiv 0 0.00% 60.20% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdSqrt 0 0.00% 60.20% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatAdd 335390 11.37% 71.57% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatAlu 0 0.00% 71.57% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatCmp 14077 0.48% 72.04% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatCvt 59340 2.01% 74.05% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatDiv 14077 0.48% 74.53% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatMisc 0 0.00% 74.53% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatMult 211044 7.15% 81.68% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatMultAcc 0 0.00% 81.68% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatMatMultAcc 0 0.00% 81.68% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatSqrt 14077 0.48% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdReduceAdd 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdReduceAlu 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdReduceCmp 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatReduceAdd 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatReduceCmp 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdAes 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdAesMix 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdSha1Hash 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdSha1Hash2 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdSha256Hash 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdSha256Hash2 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdShaSigma2 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdShaSigma3 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdSha3 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdSm4e 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdCrc 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdPredAlu 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdDotProd 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::Matrix 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::MatrixMov 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::MatrixOP 0 0.00% 82.16% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::MemRead 43661 1.48% 83.64% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::MemWrite 14917 0.51% 84.15% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::FloatMemRead 383398 12.99% 97.14% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::FloatMemWrite 84462 2.86% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdStrideSegmentedLoad 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdStrideSegmentedStore 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdExt 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdBf16Add 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdBf16Cmp 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdBf16Cvt 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdBf16DotProd 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdBf16MatMultAcc 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdBf16Mult 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::SimdBf16MultAcc 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::Bf16Cvt 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::System 0 0.00% 100.00% # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.issuedInstType_0::total 2950911 # Number of insts issued per FU, per thread (Count)
board.processor.switch1.core.commitStats0.numInsts 1657548 # Number of instructions committed (thread level) (Count)
board.processor.switch1.core.commitStats0.numOps 2950911 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.switch1.core.commitStats0.numInstsNotNOP 1657548 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.switch1.core.commitStats0.numOpsNotNOP 2950911 # Number of Ops (including micro ops) Simulated (Count)
board.processor.switch1.core.commitStats0.numUserInsts 1651986 # Numbrer of instructions committed in user mode (Count)
board.processor.switch1.core.commitStats0.numUserOps 2939762 # Number of ops committed in user mode (Count)
board.processor.switch1.core.commitStats0.ratioUserInsts 0.996644 # Ratio of instructions committed in user mode (Ratio)
board.processor.switch1.core.commitStats0.ratioUserOps 0.996222 # Ratio of ops committed in user mode (Ratio)
board.processor.switch1.core.commitStats0.cpi 1.811713 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.switch1.core.commitStats0.ipc 0.551964 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.switch1.core.commitStats0.numMemRefs 526438 # Number of memory references committed (Count)
board.processor.switch1.core.commitStats0.numFpInsts 1773557 # Number of float instructions (Count)
board.processor.switch1.core.commitStats0.numIntInsts 1657237 # Number of integer instructions (Count)
board.processor.switch1.core.commitStats0.numLoadInsts 427059 # Number of load instructions (Count)
board.processor.switch1.core.commitStats0.numStoreInsts 99379 # Number of store instructions (Count)
board.processor.switch1.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.switch1.core.commitStats0.committedInstType::No_OpClass 42376 1.44% 1.44% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::IntAlu 1466209 49.69% 51.12% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::IntMult 92 0.00% 51.13% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::IntDiv 328 0.01% 51.14% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::FloatAdd 102051 3.46% 54.60% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::FloatCmp 0 0.00% 54.60% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::FloatCvt 0 0.00% 54.60% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::FloatMult 0 0.00% 54.60% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 54.60% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::FloatDiv 0 0.00% 54.60% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::FloatMisc 0 0.00% 54.60% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 54.60% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdAdd 0 0.00% 54.60% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 54.60% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdAlu 110860 3.76% 58.35% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdCmp 0 0.00% 58.35% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdCvt 0 0.00% 58.35% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdMisc 54552 1.85% 60.20% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdMult 0 0.00% 60.20% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 60.20% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 60.20% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdShift 0 0.00% 60.20% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 60.20% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdDiv 0 0.00% 60.20% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 60.20% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatAdd 335390 11.37% 71.57% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 71.57% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatCmp 14077 0.48% 72.04% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatCvt 59340 2.01% 74.05% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatDiv 14077 0.48% 74.53% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 74.53% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatMult 211044 7.15% 81.68% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 81.68% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 81.68% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatSqrt 14077 0.48% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdAes 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdSha3 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdSm4e 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdCrc 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdDotProd 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::Matrix 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::MatrixMov 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::MatrixOP 0 0.00% 82.16% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::MemRead 43661 1.48% 83.64% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::MemWrite 14917 0.51% 84.15% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::FloatMemRead 383398 12.99% 97.14% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::FloatMemWrite 84462 2.86% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdBf16Add 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdBf16Cmp 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdBf16Cvt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdBf16DotProd 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdBf16MatMultAcc 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdBf16Mult 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::SimdBf16MultAcc 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::Bf16Cvt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::System 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedInstType::total 2950911 # Class of committed instruction. (Count)
board.processor.switch1.core.commitStats0.committedControl::IsControl 149582 # Class of control type instructions committed (Count)
board.processor.switch1.core.commitStats0.committedControl::IsDirectControl 107219 # Class of control type instructions committed (Count)
board.processor.switch1.core.commitStats0.committedControl::IsIndirectControl 42361 # Class of control type instructions committed (Count)
board.processor.switch1.core.commitStats0.committedControl::IsCondControl 78881 # Class of control type instructions committed (Count)
board.processor.switch1.core.commitStats0.committedControl::IsUncondControl 70701 # Class of control type instructions committed (Count)
board.processor.switch1.core.commitStats0.committedControl::IsCall 14207 # Class of control type instructions committed (Count)
board.processor.switch1.core.commitStats0.committedControl::IsReturn 14207 # Class of control type instructions committed (Count)
board.processor.switch1.core.commitStats0.functionCalls 14207 # Number of function calls committed (Count)
board.processor.switch1.core.commitStats0.numCallsReturns 28414 # Number of function calls and returns committed (Count)
board.processor.switch1.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.switch1.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.switch1.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.switch1.core.exec_context.thread_0.numBusyCycles 3003002 # Number of busy cycles (Cycle)
board.processor.switch1.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.switch1.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.switch1.core.executeStats0.numInsts 1657548 # Number of executed instructions (Count)
board.processor.switch1.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.switch1.core.executeStats0.numBranches 149582 # Number of branches executed (Count)
board.processor.switch1.core.executeStats0.numLoadInsts 427059 # Number of load instructions executed (Count)
board.processor.switch1.core.executeStats0.numStoreInsts 99379 # Number of stores executed (Count)
board.processor.switch1.core.executeStats0.instRate 0.551964 # Inst execution rate ((Count/Cycle))
board.processor.switch1.core.executeStats0.numCCRegReads 527449 # Number of times the CC registers were read (Count)
board.processor.switch1.core.executeStats0.numCCRegWrites 543069 # Number of times the CC registers were written (Count)
board.processor.switch1.core.executeStats0.numFpAluAccesses 1773557 # Number of float alu accesses (Count)
board.processor.switch1.core.executeStats0.numFpRegReads 2699766 # Number of times the floating registers were read (Count)
board.processor.switch1.core.executeStats0.numFpRegWrites 1628877 # Number of times the floating registers were written (Count)
board.processor.switch1.core.executeStats0.numIntAluAccesses 1657237 # Number of integer alu accesses (Count)
board.processor.switch1.core.executeStats0.numIntRegReads 1568771 # Number of times the integer registers were read (Count)
board.processor.switch1.core.executeStats0.numIntRegWrites 952522 # Number of times the integer registers were written (Count)
board.processor.switch1.core.executeStats0.numMemRefs 526438 # Number of memory refs (Count)
board.processor.switch1.core.executeStats0.numMiscRegReads 988603 # Number of times the Misc registers were read (Count)
board.processor.switch1.core.executeStats0.numMiscRegWrites 24 # Number of times the Misc registers were written (Count)
board.processor.switch1.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.switch1.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.switch1.core.fetchStats0.numInsts 1657548 # Number of instructions fetched (thread level) (Count)
board.processor.switch1.core.fetchStats0.numOps 2950911 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.switch1.core.fetchStats0.fetchRate 0.551964 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.switch1.core.fetchStats0.numBranches 149582 # Number of branches fetched (Count)
board.processor.switch1.core.fetchStats0.branchRate 0.049811 # Number of branch fetches per cycle (Ratio)
board.processor.switch1.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.switch1.core.mmu.dtb.rdAccesses 427163 # TLB accesses on read requests (Count)
board.processor.switch1.core.mmu.dtb.wrAccesses 99381 # TLB accesses on write requests (Count)
board.processor.switch1.core.mmu.dtb.exAccesses 0 # TLB accesses on execute (instr) requests (Count)
board.processor.switch1.core.mmu.dtb.rdMisses 104 # TLB misses on read requests (Count)
board.processor.switch1.core.mmu.dtb.wrMisses 2 # TLB misses on write requests (Count)
board.processor.switch1.core.mmu.dtb.exMisses 0 # TLB misses on execute (instr) requests (Count)
board.processor.switch1.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch1.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.switch1.core.mmu.itb.wrAccesses 0 # TLB accesses on write requests (Count)
board.processor.switch1.core.mmu.itb.exAccesses 2308655 # TLB accesses on execute (instr) requests (Count)
board.processor.switch1.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.switch1.core.mmu.itb.wrMisses 0 # TLB misses on write requests (Count)
board.processor.switch1.core.mmu.itb.exMisses 8 # TLB misses on execute (instr) requests (Count)
board.processor.switch1.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch1.core.power_state.pwrStateResidencyTicks::OFF 1000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.switch1.core.thread_0.numInsts 1657548 # Number of Instructions committed (Count)
board.processor.switch1.core.thread_0.numOps 2950911 # Number of Ops committed (Count)
board.processor.switch1.core.thread_0.numMemRefs 526438 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------