---------- Begin Simulation Statistics ----------
simSeconds 0.009471 # Number of seconds simulated (Second)
simTicks 9470742444 # Number of ticks simulated (Tick)
finalTick 9470742444 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 128.78 # Real time elapsed on the host (Second)
hostTickRate 73539519 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3610172 # Number of bytes of host memory used (Byte)
simInsts 26728147 # Number of instructions simulated (Count)
simOps 41096287 # Number of ops (including micro ops) simulated (Count)
hostInstRate 207542 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 319109 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.demandHits::processor.cores.core.data 12306108 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.demandHits::total 12306108 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::processor.cores.core.data 12306108 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::total 12306108 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.demandMisses::processor.cores.core.data 63824 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.demandMisses::total 63824 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::processor.cores.core.data 63824 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::total 63824 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.demandMissLatency::processor.cores.core.data 322578765 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMissLatency::total 322578765 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::processor.cores.core.data 322578765 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::total 322578765 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandAccesses::processor.cores.core.data 12369932 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandAccesses::total 12369932 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::processor.cores.core.data 12369932 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::total 12369932 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandMissRate::processor.cores.core.data 0.005160 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMissRate::total 0.005160 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::processor.cores.core.data 0.005160 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::total 0.005160 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::processor.cores.core.data 5054.192232 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::total 5054.192232 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::processor.cores.core.data 5054.192232 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::total 5054.192232 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.writebacks::writebacks 66235 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.writebacks::total 66235 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::processor.cores.core.data 259 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::total 259 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::processor.cores.core.data 259 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::total 259 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::processor.cores.core.data 63565 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::total 63565 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::cache_hierarchy.l1dcaches.prefetcher 4489 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::processor.cores.core.data 63565 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::total 68054 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::processor.cores.core.data 292974399 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::total 292974399 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 36718412 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::processor.cores.core.data 292974399 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::total 329692811 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::processor.cores.core.data 0.005139 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::total 0.005139 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::cache_hierarchy.l1dcaches.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::processor.cores.core.data 0.005139 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::total 0.005502 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::processor.cores.core.data 4609.052136 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::total 4609.052136 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 8179.641791 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::processor.cores.core.data 4609.052136 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::total 4844.576527 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.replacements 67798 # number of replacements (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches.prefetcher 4489 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::total 4489 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 36718412 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::total 36718412 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 8179.641791 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::total 8179.641791 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.hits::processor.cores.core.data 10213581 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.hits::total 10213581 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::processor.cores.core.data 63236 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::total 63236 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::processor.cores.core.data 311827860 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::total 311827860 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::processor.cores.core.data 10276817 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::total 10276817 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::processor.cores.core.data 0.006153 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::total 0.006153 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::processor.cores.core.data 4931.176229 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::total 4931.176229 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.mshrHits::processor.cores.core.data 218 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrHits::total 218 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::processor.cores.core.data 63018 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::total 63018 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::processor.cores.core.data 282749967 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::total 282749967 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::processor.cores.core.data 0.006132 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::total 0.006132 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::processor.cores.core.data 4486.812768 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::total 4486.812768 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.hits::processor.cores.core.data 2092527 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.hits::total 2092527 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::processor.cores.core.data 588 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::total 588 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::processor.cores.core.data 10750905 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::total 10750905 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::processor.cores.core.data 2093115 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::total 2093115 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::processor.cores.core.data 0.000281 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::total 0.000281 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::processor.cores.core.data 18283.852041 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::total 18283.852041 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.mshrHits::processor.cores.core.data 41 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrHits::total 41 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::processor.cores.core.data 547 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::total 547 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::processor.cores.core.data 10224432 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::total 10224432 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::processor.cores.core.data 0.000261 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::total 0.000261 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::processor.cores.core.data 18691.831810 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::total 18691.831810 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.prefetcher.demandMshrMisses 63565 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIssued 12178 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUnused 1864 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUseful 2581 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches.prefetcher.accuracy 0.211940 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.coverage 0.039020 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInCache 7551 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInMSHR 138 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfLate 7689 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIdentified 12187 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfBufferHit 6 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedDemand 1 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfSpanPage 569 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulSpanPage 394 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.tags.tagsInUse 255.731454 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches.tags.totalRefs 12374162 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.sampledRefs 68054 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.avgRefs 181.828577 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches.tags.warmupTick 132201 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches.tags.occupancies::cache_hierarchy.l1dcaches.prefetcher 13.140473 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.occupancies::processor.cores.core.data 242.590980 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::cache_hierarchy.l1dcaches.prefetcher 0.051330 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::processor.cores.core.data 0.947621 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::total 0.998951 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1022 182 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1024 74 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1022::0 154 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1022::1 28 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::0 72 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::3 2 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1022 0.710938 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1024 0.289062 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.tagAccesses 99027510 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches.tags.dataAccesses 99027510 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.demandHits::processor.cores.core.inst 3208587 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.demandHits::total 3208587 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.overallHits::processor.cores.core.inst 3208587 # number of overall hits (Count)
board.cache_hierarchy.l1icaches.overallHits::total 3208587 # number of overall hits (Count)
board.cache_hierarchy.l1icaches.demandMisses::processor.cores.core.inst 905 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.demandMisses::total 905 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::processor.cores.core.inst 905 # number of overall misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::total 905 # number of overall misses (Count)
board.cache_hierarchy.l1icaches.demandMissLatency::processor.cores.core.inst 46287999 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMissLatency::total 46287999 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::processor.cores.core.inst 46287999 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::total 46287999 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandAccesses::processor.cores.core.inst 3209492 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandAccesses::total 3209492 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::processor.cores.core.inst 3209492 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::total 3209492 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandMissRate::processor.cores.core.inst 0.000282 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMissRate::total 0.000282 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::processor.cores.core.inst 0.000282 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::total 0.000282 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMissLatency::processor.cores.core.inst 51146.960221 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMissLatency::total 51146.960221 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::processor.cores.core.inst 51146.960221 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::total 51146.960221 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.demandMshrHits::processor.cores.core.inst 207 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1icaches.demandMshrHits::total 207 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1icaches.overallMshrHits::processor.cores.core.inst 207 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1icaches.overallMshrHits::total 207 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1icaches.demandMshrMisses::processor.cores.core.inst 698 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMisses::total 698 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::processor.cores.core.inst 698 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::total 698 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::processor.cores.core.inst 38604690 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::total 38604690 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::processor.cores.core.inst 38604690 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::total 38604690 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissRate::processor.cores.core.inst 0.000217 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMshrMissRate::total 0.000217 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::processor.cores.core.inst 0.000217 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::total 0.000217 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::processor.cores.core.inst 55307.578797 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::total 55307.578797 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::processor.cores.core.inst 55307.578797 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::total 55307.578797 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.replacements 441 # number of replacements (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::processor.cores.core.inst 3208587 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::total 3208587 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::processor.cores.core.inst 905 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::total 905 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::processor.cores.core.inst 46287999 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::total 46287999 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.accesses::processor.cores.core.inst 3209492 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.accesses::total 3209492 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.missRate::processor.cores.core.inst 0.000282 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.missRate::total 0.000282 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::processor.cores.core.inst 51146.960221 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::total 51146.960221 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.mshrHits::processor.cores.core.inst 207 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrHits::total 207 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::processor.cores.core.inst 698 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::total 698 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::processor.cores.core.inst 38604690 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::total 38604690 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::processor.cores.core.inst 0.000217 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::total 0.000217 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::processor.cores.core.inst 55307.578797 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::total 55307.578797 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.prefetcher.demandMshrMisses 698 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.tags.tagsInUse 255.825339 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches.tags.totalRefs 3209284 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.sampledRefs 697 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.avgRefs 4604.424677 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches.tags.warmupTick 69930 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches.tags.occupancies::processor.cores.core.inst 255.825339 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::processor.cores.core.inst 0.999318 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::total 0.999318 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.occupanciesTaskId::1024 256 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::0 135 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::1 6 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::3 115 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches.tags.tagAccesses 25676633 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches.tags.dataAccesses 25676633 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2bus.transDist::ReadResp 68204 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::WritebackDirty 66235 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::CleanEvict 2005 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::HardPFReq 2059 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::ReadExReq 547 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::ReadExResp 547 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::ReadSharedReq 68205 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 1836 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 203906 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount::total 205742 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 44608 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 8594496 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize::total 8639104 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.snoops 2060 # Total snoops (Count)
board.cache_hierarchy.l2bus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2bus.snoopFanout::samples 70812 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::mean 0.000042 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::stdev 0.006509 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::0 70809 100.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::1 3 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::max_value 1 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::total 70812 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2bus.reqLayer0.occupancy 90475368 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer0.occupancy 696303 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer1.occupancy 67985946 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.snoop_filter.totRequests 136991 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2bus.snoop_filter.hitSingleRequests 68239 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2bus.snoop_filter.hitMultiRequests 2 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2bus.snoop_filter.totSnoops 1 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2bus.snoop_filter.hitSingleSnoops 1 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2bus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2cache.demandHits::cache_hierarchy.l1dcaches.prefetcher 4271 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores.core.inst 25 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores.core.data 63288 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::total 67584 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.overallHits::cache_hierarchy.l1dcaches.prefetcher 4271 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores.core.inst 25 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores.core.data 63288 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::total 67584 # number of overall hits (Count)
board.cache_hierarchy.l2cache.demandMisses::cache_hierarchy.l1dcaches.prefetcher 218 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores.core.inst 673 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores.core.data 277 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::total 1168 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.overallMisses::cache_hierarchy.l1dcaches.prefetcher 218 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::processor.cores.core.inst 673 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::processor.cores.core.data 277 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::total 1168 # number of overall misses (Count)
board.cache_hierarchy.l2cache.demandMissLatency::cache_hierarchy.l1dcaches.prefetcher 14918532 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores.core.inst 38045250 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores.core.data 18699282 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::total 71663064 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::cache_hierarchy.l1dcaches.prefetcher 14918532 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores.core.inst 38045250 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores.core.data 18699282 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::total 71663064 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.demandAccesses::cache_hierarchy.l1dcaches.prefetcher 4489 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores.core.inst 698 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores.core.data 63565 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::total 68752 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::cache_hierarchy.l1dcaches.prefetcher 4489 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores.core.inst 698 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores.core.data 63565 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::total 68752 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandMissRate::cache_hierarchy.l1dcaches.prefetcher 0.048563 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores.core.inst 0.964183 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores.core.data 0.004358 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::total 0.016989 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::cache_hierarchy.l1dcaches.prefetcher 0.048563 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores.core.inst 0.964183 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores.core.data 0.004358 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::total 0.016989 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.demandAvgMissLatency::cache_hierarchy.l1dcaches.prefetcher 68433.633028 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores.core.inst 56530.832095 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores.core.data 67506.433213 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::total 61355.363014 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::cache_hierarchy.l1dcaches.prefetcher 68433.633028 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores.core.inst 56530.832095 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores.core.data 67506.433213 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::total 61355.363014 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2cache.demandMshrHits::cache_hierarchy.l1dcaches.prefetcher 172 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::total 172 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::cache_hierarchy.l1dcaches.prefetcher 172 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::total 172 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::cache_hierarchy.l1dcaches.prefetcher 46 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores.core.inst 673 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores.core.data 277 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::total 996 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::cache_hierarchy.l1dcaches.prefetcher 46 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::cache_hierarchy.l2cache.prefetcher 1827 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores.core.inst 673 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores.core.data 277 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::total 2823 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 4476180 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores.core.inst 37821474 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores.core.data 18607041 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::total 60904695 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 4476180 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::cache_hierarchy.l2cache.prefetcher 108740358 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores.core.inst 37821474 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores.core.data 18607041 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::total 169645053 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissRate::cache_hierarchy.l1dcaches.prefetcher 0.010247 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores.core.inst 0.964183 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores.core.data 0.004358 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::total 0.014487 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::cache_hierarchy.l1dcaches.prefetcher 0.010247 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::cache_hierarchy.l2cache.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores.core.inst 0.964183 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores.core.data 0.004358 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::total 0.041061 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 97308.260870 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores.core.inst 56198.326895 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores.core.data 67173.433213 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::total 61149.292169 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 97308.260870 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::cache_hierarchy.l2cache.prefetcher 59518.532020 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores.core.inst 56198.326895 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores.core.data 67173.433213 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::total 60093.890542 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.replacements 1 # number of replacements (Count)
board.cache_hierarchy.l2cache.HardPFReq.mshrMisses::cache_hierarchy.l2cache.prefetcher 1827 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l2cache.HardPFReq.mshrMisses::total 1827 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l2cache.HardPFReq.mshrMissLatency::cache_hierarchy.l2cache.prefetcher 108740358 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.HardPFReq.mshrMissLatency::total 108740358 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.HardPFReq.mshrMissRate::cache_hierarchy.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l2cache.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l2cache.HardPFReq.avgMshrMissLatency::cache_hierarchy.l2cache.prefetcher 59518.532020 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.HardPFReq.avgMshrMissLatency::total 59518.532020 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.hits::processor.cores.core.data 435 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.hits::total 435 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::processor.cores.core.data 112 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::total 112 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::processor.cores.core.data 8259732 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::total 8259732 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.accesses::processor.cores.core.data 547 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.accesses::total 547 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.missRate::processor.cores.core.data 0.204753 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.missRate::total 0.204753 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::processor.cores.core.data 73747.607143 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::total 73747.607143 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::processor.cores.core.data 112 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::total 112 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::processor.cores.core.data 8222436 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::total 8222436 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::processor.cores.core.data 0.204753 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::total 0.204753 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::processor.cores.core.data 73414.607143 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::total 73414.607143 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.hits::cache_hierarchy.l1dcaches.prefetcher 4271 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.hits::processor.cores.core.inst 25 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.hits::processor.cores.core.data 62853 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.hits::total 67149 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.misses::cache_hierarchy.l1dcaches.prefetcher 218 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.misses::processor.cores.core.inst 673 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.misses::processor.cores.core.data 165 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.misses::total 1056 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.missLatency::cache_hierarchy.l1dcaches.prefetcher 14918532 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.missLatency::processor.cores.core.inst 38045250 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.missLatency::processor.cores.core.data 10439550 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.missLatency::total 63403332 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.accesses::cache_hierarchy.l1dcaches.prefetcher 4489 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.accesses::processor.cores.core.inst 698 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.accesses::processor.cores.core.data 63018 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.accesses::total 68205 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.missRate::cache_hierarchy.l1dcaches.prefetcher 0.048563 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.missRate::processor.cores.core.inst 0.964183 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.missRate::processor.cores.core.data 0.002618 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.missRate::total 0.015483 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::cache_hierarchy.l1dcaches.prefetcher 68433.633028 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores.core.inst 56530.832095 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores.core.data 63270 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::total 60041.034091 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.mshrHits::cache_hierarchy.l1dcaches.prefetcher 172 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrHits::total 172 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::cache_hierarchy.l1dcaches.prefetcher 46 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores.core.inst 673 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores.core.data 165 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::total 884 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 4476180 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores.core.inst 37821474 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores.core.data 10384605 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::total 52682259 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::cache_hierarchy.l1dcaches.prefetcher 0.010247 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores.core.inst 0.964183 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores.core.data 0.002618 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::total 0.012961 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 97308.260870 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.inst 56198.326895 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.data 62937 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::total 59595.315611 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.WritebackDirty.hits::writebacks 66235 # number of WritebackDirty hits (Count)
board.cache_hierarchy.l2cache.WritebackDirty.hits::total 66235 # number of WritebackDirty hits (Count)
board.cache_hierarchy.l2cache.WritebackDirty.accesses::writebacks 66235 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.WritebackDirty.accesses::total 66235 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2cache.prefetcher.demandMshrMisses 996 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2cache.prefetcher.pfIssued 6855 # number of hwpf issued (Count)
board.cache_hierarchy.l2cache.prefetcher.pfUseful 1653 # number of useful prefetch (Count)
board.cache_hierarchy.l2cache.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2cache.prefetcher.accuracy 0.241138 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2cache.prefetcher.coverage 0.624009 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2cache.prefetcher.pfHitInCache 4730 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2cache.prefetcher.pfHitInMSHR 298 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2cache.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2cache.prefetcher.pfLate 5028 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2cache.prefetcher.pfIdentified 7275 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2cache.prefetcher.pfBufferHit 279 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2cache.prefetcher.pfRemovedDemand 106 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2cache.prefetcher.pfSpanPage 361 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2cache.prefetcher.pfUsefulSpanPage 263 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2cache.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2cache.tags.tagsInUse 2341.023867 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2cache.tags.totalRefs 138643 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2cache.tags.sampledRefs 2822 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2cache.tags.avgRefs 49.129341 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2cache.tags.warmupTick 69264 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2cache.tags.occupancies::cache_hierarchy.l1dcaches.prefetcher 40.668975 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::cache_hierarchy.l2cache.prefetcher 1530.628690 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores.core.inst 531.317451 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores.core.data 238.408750 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::cache_hierarchy.l1dcaches.prefetcher 0.009929 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::cache_hierarchy.l2cache.prefetcher 0.373689 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores.core.inst 0.129716 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores.core.data 0.058205 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::total 0.571539 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.occupanciesTaskId::1022 1873 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2cache.tags.occupanciesTaskId::1024 948 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1022::2 55 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1022::3 1818 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1024::0 166 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1024::1 7 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1024::2 1 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1024::3 774 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ratioOccsTaskId::1022 0.457275 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2cache.tags.ratioOccsTaskId::1024 0.231445 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2cache.tags.tagAccesses 2194646 # Number of tag accesses (Count)
board.cache_hierarchy.l2cache.tags.dataAccesses 2194646 # Number of data accesses (Count)
board.cache_hierarchy.l2cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.transDist::ReadResp 2710 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq 112 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp 112 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq 2711 # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2cache.mem_side_port::board.memory.mem_ctrl.port 5645 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2cache.mem_side_port::total 5645 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total 5645 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2cache.mem_side_port::board.memory.mem_ctrl.port 180608 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2cache.mem_side_port::total 180608 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total 180608 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 2823 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 2823 100.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 2823 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy 1451434 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer2.occupancy 2412217 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer2.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests 2823 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl.avgPriority_cache_hierarchy.l1dcaches.prefetcher::samples 46.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_cache_hierarchy.l2cache.prefetcher::samples 1827.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.inst::samples 673.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.data::samples 277.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.priorityMinLatency 0.000000017492 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl.priorityMaxLatency 0.000000855966 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl.numStayReadState 7874 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl.readReqs 2823 # Number of read requests accepted (Count)
board.memory.mem_ctrl.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl.readBursts 2823 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl.avgRdQLen 1.17 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::6 2823 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.rdQLenPdf::0 1581 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::1 735 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::2 149 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::3 89 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::4 60 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::5 51 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::6 44 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::7 42 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::8 42 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::9 15 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::10 6 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::11 4 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::12 3 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl.bytesReadSys 180672 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl.avgRdBWSys 19076857.07517694 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.totGap 9470738448 # Total gap between requests (Tick)
board.memory.mem_ctrl.avgGap 3354848.90 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl.requestorReadBytes::cache_hierarchy.l1dcaches.prefetcher 2944 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::cache_hierarchy.l2cache.prefetcher 116928 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.inst 43072 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.data 17728 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadRate::cache_hierarchy.l1dcaches.prefetcher 310852.081281664723 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::cache_hierarchy.l2cache.prefetcher 12346233.750034812838 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.inst 4547901.102229572833 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.data 1871870.141630894039 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadAccesses::cache_hierarchy.l1dcaches.prefetcher 46 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::cache_hierarchy.l2cache.prefetcher 1827 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.inst 673 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.data 277 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadTotalLat::cache_hierarchy.l1dcaches.prefetcher 3224564 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::cache_hierarchy.l2cache.prefetcher 65152369 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.inst 19593546 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.data 11080752 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadAvgLat::cache_hierarchy.l1dcaches.prefetcher 70099.22 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::cache_hierarchy.l2cache.prefetcher 35660.85 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.inst 29113.74 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.data 40002.71 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.dram.bytesRead::cache_hierarchy.l1dcaches.prefetcher 2944 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::cache_hierarchy.l2cache.prefetcher 116928 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.inst 43008 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.data 17728 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::total 180608 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::processor.cores.core.inst 43008 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::total 43008 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.numReads::cache_hierarchy.l1dcaches.prefetcher 46 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::cache_hierarchy.l2cache.prefetcher 1827 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.inst 672 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.data 277 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::total 2822 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.bwRead::cache_hierarchy.l1dcaches.prefetcher 310852 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::cache_hierarchy.l2cache.prefetcher 12346234 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.inst 4541143 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.data 1871870 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::total 19070099 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::processor.cores.core.inst 4541143 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::total 4541143 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::cache_hierarchy.l1dcaches.prefetcher 310852 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::cache_hierarchy.l2cache.prefetcher 12346234 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.inst 4541143 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.data 1871870 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::total 19070099 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.readBursts 2823 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::0 166 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::1 101 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::2 66 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::3 79 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::4 104 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::5 128 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::6 128 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::7 143 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::8 168 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::9 136 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::10 248 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::11 156 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::12 143 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::13 142 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::14 156 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::15 161 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::16 142 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::17 153 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::18 97 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::19 24 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::20 28 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::21 15 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::22 3 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::24 1 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::25 18 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::26 21 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::27 10 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::28 4 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::29 8 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::30 24 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::31 50 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.totQLat 49671315 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl.dram.totBusLat 9406236 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl.dram.totMemAccLat 99051231 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl.dram.avgQLat 17595.22 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgBusLat 3332.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgMemAccLat 35087.22 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.readRowHits 1978 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl.dram.readRowHitRate 70.07 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl.dram.bytesPerActivate::samples 831 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::mean 213.795427 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::gmean 113.573388 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::stdev 304.792359 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::0-127 572 68.83% 68.83% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::128-255 81 9.75% 78.58% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::256-383 29 3.49% 82.07% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::384-511 28 3.37% 85.44% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::512-639 22 2.65% 88.09% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::640-767 7 0.84% 88.93% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::768-895 5 0.60% 89.53% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::896-1023 1 0.12% 89.65% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::1024-1151 86 10.35% 100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::total 831 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.dramBytesRead 180672 # Total bytes read (Byte)
board.memory.mem_ctrl.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl.dram.avgRdBW 19.076857 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl.dram.busUtil 0.10 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl.dram.busUtilRead 0.10 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl.dram.pageHitRate 70.07 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl.dram.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl.dram.rank0.actEnergy 828028.656000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preEnergy 1439765.863200 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.readEnergy 6102957.840000 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.refreshEnergy 821840348.313606 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actBackEnergy 739682894.445596 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preBackEnergy 2580606384.384026 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.totalEnergy 4150500379.502403 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.averagePower 438.244457 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::IDLE 7885711083 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::REF 425600000 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT 1159431361 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.actEnergy 489644.064000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preEnergy 847892.707200 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.readEnergy 1640255.635200 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.refreshEnergy 821840348.313606 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actBackEnergy 666848437.886382 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preBackEnergy 2630888039.673584 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.totalEnergy 4122554618.279929 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.averagePower 435.293710 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::IDLE 8040385441 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::REF 425600000 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT 1004757003 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles 28440669 # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.cpi 1.064072 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores.core.ipc 0.939786 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores.core.instsAdded 41938938 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.cores.core.nonSpecInstsAdded 3 # Number of non-speculative instructions added to the IQ (Count)
board.processor.cores.core.instsIssued 41394873 # Number of instructions issued (Count)
board.processor.cores.core.squashedInstsIssued 446 # Number of squashed instructions issued (Count)
board.processor.cores.core.squashedInstsExamined 842648 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
board.processor.cores.core.squashedOperandsExamined 2204708 # Number of squashed operands that are examined and possibly removed from graph (Count)
board.processor.cores.core.squashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed (Count)
board.processor.cores.core.numIssuedDist::samples 28387538 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::mean 1.458206 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::stdev 1.302167 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::0 7002359 24.67% 24.67% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::1 11054125 38.94% 63.61% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::2 4099224 14.44% 78.05% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::3 3036579 10.70% 88.74% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::4 3056233 10.77% 99.51% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::5 74005 0.26% 99.77% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::6 21892 0.08% 99.85% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::7 38714 0.14% 99.98% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::8 4407 0.02% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::total 28387538 # Number of insts issued each cycle (Count)
board.processor.cores.core.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntAlu 10275 1.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntMult 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntDiv 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatAdd 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCmp 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCvt 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMult 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMultAcc 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatDiv 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMisc 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatSqrt 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAdd 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAddAcc 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAlu 26 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCmp 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCvt 1 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMisc 13 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMult 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMultAcc 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMatMultAcc 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShift 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShiftAcc 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdDiv 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSqrt 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAdd 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAlu 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCmp 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCvt 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatDiv 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMisc 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMult 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMultAcc 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMatMultAcc 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatSqrt 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAdd 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAlu 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceCmp 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceAdd 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceCmp 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAes 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAesMix 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash2 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash2 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma2 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma3 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdPredAlu 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::Matrix 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MatrixMov 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MatrixOP 0 0.00% 1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemRead 1019567 98.99% 99.99% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemWrite 42 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemRead 16 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemWrite 13 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStrideSegmentedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStrideSegmentedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statIssuedInstType_0::No_OpClass 1113 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntAlu 22796941 55.07% 55.07% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntMult 3050337 7.37% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntDiv 127 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatAdd 161 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCmp 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCvt 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMult 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatDiv 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMisc 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatSqrt 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAdd 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAlu 301 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCmp 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCvt 157 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMisc 349 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMult 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShift 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdDiv 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSqrt 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAes 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAesMix 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::Matrix 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MatrixMov 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MatrixOP 0 0.00% 62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemRead 13450542 32.49% 94.94% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemWrite 2094061 5.06% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemRead 230 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemWrite 554 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::total 41394873 # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.issueRate 1.455482 # Inst issue rate ((Count/Cycle))
board.processor.cores.core.fuBusy 1029953 # FU busy when requested (Count)
board.processor.cores.core.fuBusyRate 0.024881 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.cores.core.intInstQueueReads 112203804 # Number of integer instruction queue reads (Count)
board.processor.cores.core.intInstQueueWrites 42779140 # Number of integer instruction queue writes (Count)
board.processor.cores.core.intInstQueueWakeupAccesses 41360411 # Number of integer instruction queue wakeup accesses (Count)
board.processor.cores.core.fpInstQueueReads 3879 # Number of floating instruction queue reads (Count)
board.processor.cores.core.fpInstQueueWrites 2526 # Number of floating instruction queue writes (Count)
board.processor.cores.core.fpInstQueueWakeupAccesses 1854 # Number of floating instruction queue wakeup accesses (Count)
board.processor.cores.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.cores.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.cores.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.cores.core.intAluAccesses 42421739 # Number of integer alu accesses (Count)
board.processor.cores.core.fpAluAccesses 1974 # Number of floating point alu accesses (Count)
board.processor.cores.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.numRecvResp 12369932 # Number of received responses (Count)
board.processor.cores.core.numRecvRespBytes 61983865 # Number of received response bytes (Byte)
board.processor.cores.core.recvRespAvgBW 2.18 # Average bandwidth of received responses ((Byte/Cycle))
board.processor.cores.core.recvRespAvgSize 5.01 # Average packet size per received response ((Byte/Count))
board.processor.cores.core.recvRespAvgRate 0.43 # Average rate of received responses per cycle ((Count/Cycle))
board.processor.cores.core.recvRespAvgRetryRate 0.00 # Average retry rate per received response ((Count/Count))
board.processor.cores.core.numSendRetryResp 0 # Number of retry responses sent (Count)
board.processor.cores.core.numSquashedInsts 31303 # Number of squashed instructions skipped in execute (Count)
board.processor.cores.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.cores.core.timesIdled 435 # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
board.processor.cores.core.idleCycles 53131 # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
board.processor.cores.core.MemDepUnit__0.insertedLoads 13582896 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.insertedStores 2136033 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingLoads 7234054 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingStores 2070703 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::Return 534 0.05% 0.05% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallDirect 583 0.05% 0.10% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallIndirect 201 0.02% 0.12% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectCond 1077215 98.81% 98.93% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectUncond 11247 1.03% 99.96% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectCond 0 0.00% 99.96% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectUncond 390 0.04% 100.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::total 1090170 # Number of BP lookups (Count)
board.processor.cores.core.branchPred.squashes_0::NoBranch 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::Return 275 0.77% 0.77% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallDirect 417 1.16% 1.93% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallIndirect 104 0.29% 2.22% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectCond 34059 94.85% 97.07% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectUncond 748 2.08% 99.15% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectCond 0 0.00% 99.15% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectUncond 304 0.85% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::total 35907 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.corrected_0::NoBranch 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::Return 1 0.01% 0.01% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallDirect 158 1.40% 1.41% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallIndirect 61 0.54% 1.95% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectCond 10849 96.01% 97.96% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectUncond 139 1.23% 99.19% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectCond 0 0.00% 99.19% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectUncond 92 0.81% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::total 11300 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::Return 259 0.02% 0.02% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::CallDirect 166 0.02% 0.04% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::CallIndirect 97 0.01% 0.05% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::DirectCond 1043154 98.95% 99.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::DirectUncond 10499 1.00% 99.99% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::IndirectCond 0 0.00% 99.99% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::IndirectUncond 86 0.01% 100.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::total 1054261 # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.mispredicted_0::NoBranch 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::Return 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallDirect 68 0.62% 0.62% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallIndirect 54 0.49% 1.11% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectCond 10735 97.46% 98.57% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectUncond 81 0.74% 99.30% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectCond 0 0.00% 99.30% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectUncond 77 0.70% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::total 11015 # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::NoBranch 0 0.00% 0.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::Return 0 0.00% 0.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::CallDirect 0 0.00% 0.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::CallIndirect 0 0.00% 0.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::DirectCond 10466 100.00% 100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::DirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::IndirectCond 0 0.00% 100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::IndirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::total 10466 # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::NoBranch 0 0.00% 0.00% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::Return 0 0.00% 0.00% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::CallDirect 68 12.39% 12.39% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::CallIndirect 54 9.84% 22.22% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::DirectCond 269 49.00% 71.22% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::DirectUncond 81 14.75% 85.97% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::IndirectCond 0 0.00% 85.97% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::IndirectUncond 77 14.03% 100.00% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::total 549 # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.targetProvider_0::NoTarget 5453 0.50% 0.50% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::BTB 1084082 99.44% 99.94% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::RAS 534 0.05% 99.99% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::Indirect 101 0.01% 100.00% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::total 1090170 # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetWrong_0::NoBranch 933 8.26% 8.26% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::Return 10358 91.68% 99.94% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallDirect 1 0.01% 99.95% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallIndirect 6 0.05% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::total 11298 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.condPredicted 1077215 # Number of conditional branches predicted (Count)
board.processor.cores.core.branchPred.condPredictedTaken 1073367 # Number of conditional branches predicted as taken (Count)
board.processor.cores.core.branchPred.condIncorrect 11300 # Number of conditional branches incorrect (Count)
board.processor.cores.core.branchPred.predTakenBTBMiss 418 # Number of branches predicted taken but missed in BTB (Count)
board.processor.cores.core.branchPred.BTBLookups 1090170 # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.BTBUpdates 787 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.BTBHits 1084925 # Number of BTB hits (Count)
board.processor.cores.core.branchPred.BTBHitRatio 0.995189 # BTB Hit Ratio (Ratio)
board.processor.cores.core.branchPred.BTBMispredicted 611 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.cores.core.branchPred.indirectLookups 591 # Number of indirect predictor lookups. (Count)
board.processor.cores.core.branchPred.indirectHits 101 # Number of indirect target hits. (Count)
board.processor.cores.core.branchPred.indirectMisses 490 # Number of indirect misses. (Count)
board.processor.cores.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.cores.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::Return 534 0.05% 0.05% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallDirect 583 0.05% 0.10% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallIndirect 201 0.02% 0.12% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectCond 1077215 98.81% 98.93% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectUncond 11247 1.03% 99.96% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectCond 0 0.00% 99.96% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectUncond 390 0.04% 100.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::total 1090170 # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.misses::NoBranch 0 0.00% 0.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::Return 534 10.18% 10.18% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallDirect 212 4.04% 14.22% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallIndirect 201 3.83% 18.06% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectCond 3702 70.58% 88.64% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectUncond 206 3.93% 92.56% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectCond 0 0.00% 92.56% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectUncond 390 7.44% 100.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::total 5245 # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.updates::NoBranch 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::Return 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallDirect 158 20.08% 20.08% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallIndirect 0 0.00% 20.08% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectCond 490 62.26% 82.34% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectUncond 139 17.66% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectCond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectUncond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::total 787 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.mispredict::NoBranch 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::Return 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallDirect 158 20.08% 20.08% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallIndirect 0 0.00% 20.08% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectCond 490 62.26% 82.34% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectUncond 139 17.66% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectCond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectUncond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::total 787 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.branchPred.indirectBranchPred.lookups 591 # Number of lookups (Count)
board.processor.cores.core.branchPred.indirectBranchPred.hits 101 # Number of hits of a tag (Count)
board.processor.cores.core.branchPred.indirectBranchPred.misses 490 # Number of misses (Count)
board.processor.cores.core.branchPred.indirectBranchPred.targetRecords 153 # Number of targets that where recorded/installed in the cache (Count)
board.processor.cores.core.branchPred.indirectBranchPred.indirectRecords 744 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.cores.core.branchPred.indirectBranchPred.speculativeOverflows 1 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.cores.core.branchPred.ras.pushes 1059 # Number of times a PC was pushed onto the RAS (Count)
board.processor.cores.core.branchPred.ras.pops 1055 # Number of times a PC was poped from the RAS (Count)
board.processor.cores.core.branchPred.ras.squashes 796 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.cores.core.branchPred.ras.used 259 # Number of times the RAS is the provider (Count)
board.processor.cores.core.branchPred.ras.correct 259 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.cores.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.cores.core.commit.commitSquashedInsts 841229 # The number of squashed insts skipped by commit (Count)
board.processor.cores.core.commit.branchMispredicts 11057 # The number of times a branch was mispredicted (Count)
board.processor.cores.core.commit.numCommittedDist::samples 28281109 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::mean 1.453136 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::stdev 2.048746 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::0 9981495 35.29% 35.29% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::1 10092654 35.69% 70.98% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::2 4081230 14.43% 85.41% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::3 2011792 7.11% 92.53% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::4 10877 0.04% 92.56% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::5 10425 0.04% 92.60% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::6 662 0.00% 92.60% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::7 29600 0.10% 92.71% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::8 2062374 7.29% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::total 28281109 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.cores.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.cores.core.commit.functionCalls 263 # Number of function calls committed. (Count)
board.processor.cores.core.commit.committedInstType_0::No_OpClass 341 0.00% 0.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntAlu 22647379 55.11% 55.11% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntMult 3040040 7.40% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntDiv 56 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatAdd 146 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCmp 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCvt 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMult 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatDiv 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMisc 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatSqrt 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAdd 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAlu 160 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCmp 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCvt 86 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMisc 270 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMult 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShift 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdDiv 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSqrt 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAes 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAesMix 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::Matrix 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MatrixMov 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MatrixOP 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemRead 13314606 32.40% 94.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemWrite 2092642 5.09% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemRead 88 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemWrite 473 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::total 41096287 # Class of committed instruction (Count)
board.processor.cores.core.commit.commitEligibleSamples 2062374 # number cycles where commit BW limit reached (Cycle)
board.processor.cores.core.commitStats0.numInsts 26728147 # Number of instructions committed (thread level) (Count)
board.processor.cores.core.commitStats0.numOps 41096287 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores.core.commitStats0.numInstsNotNOP 26728147 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores.core.commitStats0.numOpsNotNOP 41096287 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores.core.commitStats0.cpi 1.064072 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores.core.commitStats0.ipc 0.939786 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores.core.commitStats0.numMemRefs 15407809 # Number of memory references committed (Count)
board.processor.cores.core.commitStats0.numFpInsts 1372 # Number of float instructions (Count)
board.processor.cores.core.commitStats0.numIntInsts 41095237 # Number of integer instructions (Count)
board.processor.cores.core.commitStats0.numLoadInsts 13314694 # Number of load instructions (Count)
board.processor.cores.core.commitStats0.numStoreInsts 2093115 # Number of store instructions (Count)
board.processor.cores.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores.core.commitStats0.committedInstType::No_OpClass 341 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntAlu 22647379 55.11% 55.11% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntMult 3040040 7.40% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntDiv 56 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatAdd 146 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCmp 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCvt 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMult 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatDiv 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMisc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAdd 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAlu 160 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCmp 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCvt 86 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMisc 270 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMult 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShift 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdDiv 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAes 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::Matrix 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixMov 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixOP 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemRead 13314606 32.40% 94.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemWrite 2092642 5.09% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemRead 88 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemWrite 473 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::total 41096287 # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedControl::IsControl 1054261 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsDirectControl 1053819 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsIndirectControl 442 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCondControl 1043154 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsUncondControl 11107 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCall 263 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsReturn 259 # Class of control type instructions committed (Count)
board.processor.cores.core.decode.idleCycles 1078139 # Number of cycles decode is idle (Cycle)
board.processor.cores.core.decode.blockedCycles 22036454 # Number of cycles decode is blocked (Cycle)
board.processor.cores.core.decode.runCycles 2178752 # Number of cycles decode is running (Cycle)
board.processor.cores.core.decode.unblockCycles 3083024 # Number of cycles decode is unblocking (Cycle)
board.processor.cores.core.decode.squashCycles 11169 # Number of cycles decode is squashing (Cycle)
board.processor.cores.core.decode.branchResolved 1074037 # Number of times decode resolved a branch (Count)
board.processor.cores.core.decode.branchMispred 301 # Number of times decode detected a branch misprediction (Count)
board.processor.cores.core.decode.decodedInsts 42036435 # Number of instructions handled by decode (Count)
board.processor.cores.core.decode.squashedInsts 1466 # Number of squashed instructions handled by decode (Count)
board.processor.cores.core.executeStats0.numInsts 41363570 # Number of executed instructions (Count)
board.processor.cores.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores.core.executeStats0.numBranches 1056274 # Number of branches executed (Count)
board.processor.cores.core.executeStats0.numLoadInsts 13440260 # Number of load instructions executed (Count)
board.processor.cores.core.executeStats0.numStoreInsts 2094436 # Number of stores executed (Count)
board.processor.cores.core.executeStats0.instRate 1.454381 # Inst execution rate ((Count/Cycle))
board.processor.cores.core.executeStats0.numCCRegReads 7284971 # Number of times the CC registers were read (Count)
board.processor.cores.core.executeStats0.numCCRegWrites 17468302 # Number of times the CC registers were written (Count)
board.processor.cores.core.executeStats0.numFpRegReads 2333 # Number of times the floating registers were read (Count)
board.processor.cores.core.executeStats0.numFpRegWrites 1162 # Number of times the floating registers were written (Count)
board.processor.cores.core.executeStats0.numIntRegReads 61774811 # Number of times the integer registers were read (Count)
board.processor.cores.core.executeStats0.numIntRegWrites 37175912 # Number of times the integer registers were written (Count)
board.processor.cores.core.executeStats0.numMemRefs 15534696 # Number of memory refs (Count)
board.processor.cores.core.executeStats0.numMiscRegReads 17658691 # Number of times the Misc registers were read (Count)
board.processor.cores.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores.core.fetch.predictedBranches 1084717 # Number of branches that fetch has predicted taken (Count)
board.processor.cores.core.fetch.cycles 28344160 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.cores.core.fetch.squashCycles 22932 # Number of cycles fetch has spent squashing (Cycle)
board.processor.cores.core.fetch.miscStallCycles 66 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs (Cycle)
board.processor.cores.core.fetch.pendingTrapStallCycles 386 # Number of stall cycles due to pending traps (Cycle)
board.processor.cores.core.fetch.cacheLines 3209492 # Number of cache lines fetched (Count)
board.processor.cores.core.fetch.icacheSquashes 447 # Number of outstanding Icache misses that were squashed (Count)
board.processor.cores.core.fetch.nisnDist::samples 28387538 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::mean 1.492688 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::stdev 2.865191 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::0 20980603 73.91% 73.91% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::1 25689 0.09% 74.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::2 2044343 7.20% 81.20% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::3 11018 0.04% 81.24% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::4 1058298 3.73% 84.97% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::5 6530 0.02% 84.99% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::6 53565 0.19% 85.18% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::7 20860 0.07% 85.25% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::8 4186632 14.75% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::total 28387538 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetchStats0.numInsts 27553726 # Number of instructions fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.fetchRate 0.968814 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores.core.fetchStats0.numBranches 1090170 # Number of branches fetched (Count)
board.processor.cores.core.fetchStats0.branchRate 0.038331 # Number of branch fetches per cycle (Ratio)
board.processor.cores.core.fetchStats0.icacheStallCycles 31460 # ICache total stall cycles (Cycle)
board.processor.cores.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.cores.core.iew.squashCycles 11169 # Number of cycles IEW is squashing (Cycle)
board.processor.cores.core.iew.blockCycles 908519 # Number of cycles IEW is blocking (Cycle)
board.processor.cores.core.iew.unblockCycles 381 # Number of cycles IEW is unblocking (Cycle)
board.processor.cores.core.iew.dispatchedInsts 41938941 # Number of instructions dispatched to IQ (Count)
board.processor.cores.core.iew.dispSquashedInsts 73 # Number of squashed instructions skipped by dispatch (Count)
board.processor.cores.core.iew.dispLoadInsts 13582896 # Number of dispatched load instructions (Count)
board.processor.cores.core.iew.dispStoreInsts 2136033 # Number of dispatched store instructions (Count)
board.processor.cores.core.iew.dispNonSpecInsts 3 # Number of dispatched non-speculative instructions (Count)
board.processor.cores.core.iew.iqFullEvents 45 # Number of times the IQ has become full, causing a stall (Count)
board.processor.cores.core.iew.lsqFullEvents 213 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.cores.core.iew.memOrderViolationEvents 82 # Number of memory order violations (Count)
board.processor.cores.core.iew.predictedTakenIncorrect 10388 # Number of branches that were predicted taken incorrectly (Count)
board.processor.cores.core.iew.predictedNotTakenIncorrect 832 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.cores.core.iew.branchMispredicts 11220 # Number of branch mispredicts detected at execute (Count)
board.processor.cores.core.iew.instsToCommit 41363094 # Cumulative count of insts sent to commit (Count)
board.processor.cores.core.iew.writebackCount 41362265 # Cumulative count of insts written-back (Count)
board.processor.cores.core.iew.producerInst 33117625 # Number of instructions producing a value (Count)
board.processor.cores.core.iew.consumerInst 49537613 # Number of instructions consuming a value (Count)
board.processor.cores.core.iew.wbRate 1.454335 # Insts written-back per cycle ((Count/Cycle))
board.processor.cores.core.iew.wbFanout 0.668535 # Average fanout of values written-back ((Count/Count))
board.processor.cores.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.cores.core.lsq0.forwLoads 3163134 # Number of loads that had data forwarded from stores (Count)
board.processor.cores.core.lsq0.squashedLoads 268202 # Number of loads squashed (Count)
board.processor.cores.core.lsq0.ignoredResponses 84 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.cores.core.lsq0.memOrderViolation 82 # Number of memory ordering violations (Count)
board.processor.cores.core.lsq0.squashedStores 42918 # Number of stores squashed (Count)
board.processor.cores.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.cores.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.cores.core.lsq0.loadToUse::samples 13314694 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::mean 2.219190 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::stdev 1.233466 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::0-9 13251669 99.53% 99.53% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::10-19 62828 0.47% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::20-29 36 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::30-39 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::40-49 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::50-59 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::100-109 5 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::110-119 7 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::120-129 6 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::130-139 28 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::140-149 17 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::150-159 13 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::160-169 3 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::170-179 4 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::180-189 26 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::190-199 5 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::200-209 2 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::210-219 2 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::220-229 22 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::230-239 5 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::240-249 2 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::260-269 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::270-279 4 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::290-299 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::overflows 5 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::max_value 1245 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::total 13314694 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.addedLoadsAndStores 15718929 # Number of loads and stores written to the Load Store Queue (Count)
board.processor.cores.core.mmu.dtb.rdAccesses 13440270 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrAccesses 2094436 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.dtb.rdMisses 362 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrMisses 81 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.itb.wrAccesses 3209562 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.itb.wrMisses 126 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON 9470742444 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.rename.squashCycles 11169 # Number of cycles rename is squashing (Cycle)
board.processor.cores.core.rename.idleCycles 2152363 # Number of cycles rename is idle (Cycle)
board.processor.cores.core.rename.blockCycles 8936706 # Number of cycles rename is blocking (Cycle)
board.processor.cores.core.rename.serializeStallCycles 565 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.cores.core.rename.runCycles 3226946 # Number of cycles rename is running (Cycle)
board.processor.cores.core.rename.unblockCycles 14059789 # Number of cycles rename is unblocking (Cycle)
board.processor.cores.core.rename.renamedInsts 42028503 # Number of instructions processed by rename (Count)
board.processor.cores.core.rename.ROBFullEvents 172 # Number of times rename has blocked due to ROB full (Count)
board.processor.cores.core.rename.IQFullEvents 12997593 # Number of times rename has blocked due to IQ full (Count)
board.processor.cores.core.rename.LQFullEvents 46714 # Number of times rename has blocked due to LQ full (Count)
board.processor.cores.core.rename.SQFullEvents 6834 # Number of times rename has blocked due to SQ full (Count)
board.processor.cores.core.rename.renamedOperands 84919212 # Number of destination operands rename has renamed (Count)
board.processor.cores.core.rename.lookups 144966461 # Number of register rename lookups that rename has made (Count)
board.processor.cores.core.rename.intLookups 62890911 # Number of integer rename lookups (Count)
board.processor.cores.core.rename.fpLookups 2438 # Number of floating rename lookups (Count)
board.processor.cores.core.rename.committedMaps 83048018 # Number of HB maps that are committed (Count)
board.processor.cores.core.rename.undoneMaps 1871185 # Number of HB maps that are undone due to squashing (Count)
board.processor.cores.core.rename.serializing 25 # count of serializing insts renamed (Count)
board.processor.cores.core.rename.tempSerializing 25 # count of temporary serializing insts renamed (Count)
board.processor.cores.core.rename.skidInsts 29204515 # count of insts added to the skid buffer (Count)
board.processor.cores.core.rename.intReturned 36904843 # count of registers freed and written back to integer free list (Count)
board.processor.cores.core.rename.fpReturned 817 # count of registers freed and written back to floating point free list (Count)
board.processor.cores.core.rob.reads 68155601 # The number of ROB reads (Count)
board.processor.cores.core.rob.writes 83981495 # The number of ROB writes (Count)
board.processor.cores.core.thread_0.numInsts 26728147 # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps 41096287 # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.cores.core.workload.numSyscalls 18 # Number of system calls (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------