---------- Begin Simulation Statistics ----------
simSeconds                                   0.009474                       # Number of seconds simulated (Second)
simTicks                                   9474303879                       # Number of ticks simulated (Tick)
finalTick                                  9474303879                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq                                  1000000000000                       # The number of ticks per simulated second ((Tick/Second))
hostSeconds                                    127.13                       # Real time elapsed on the host (Second)
hostTickRate                                 74526655                       # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory                                    3649088                       # Number of bytes of host memory used (Byte)
simInsts                                     26728147                       # Number of instructions simulated (Count)
simOps                                       41096287                       # Number of ops (including micro ops) simulated (Count)
hostInstRate                                   210248                       # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate                                     323271                       # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.clusters.dptw_cache.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.dptw_cache.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.dptw_cache.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.clusters.dptw_cache.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.clusters.dptw_cache.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.dptw_cache.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.dptw_cache.replacements            0                       # number of replacements (Count)
board.cache_hierarchy.clusters.dptw_cache.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.dptw_cache.tags.tagsInUse            0                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.tags.totalRefs            0                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.clusters.dptw_cache.tags.sampledRefs            0                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.clusters.dptw_cache.tags.avgRefs          nan                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.clusters.dptw_cache.tags.warmupTick            0                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.clusters.dptw_cache.tags.tagAccesses            0                       # Number of tag accesses (Count)
board.cache_hierarchy.clusters.dptw_cache.tags.dataAccesses            0                       # Number of data accesses (Count)
board.cache_hierarchy.clusters.dptw_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.iptw_cache.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.iptw_cache.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.iptw_cache.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.clusters.iptw_cache.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.clusters.iptw_cache.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.iptw_cache.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.iptw_cache.replacements            0                       # number of replacements (Count)
board.cache_hierarchy.clusters.iptw_cache.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.iptw_cache.tags.tagsInUse            0                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.tags.totalRefs            0                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.clusters.iptw_cache.tags.sampledRefs            0                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.clusters.iptw_cache.tags.avgRefs          nan                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.clusters.iptw_cache.tags.warmupTick            0                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.clusters.iptw_cache.tags.tagAccesses            0                       # Number of tag accesses (Count)
board.cache_hierarchy.clusters.iptw_cache.tags.dataAccesses            0                       # Number of data accesses (Count)
board.cache_hierarchy.clusters.iptw_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l1dcache.demandHits::processor.cores.core.data     12306087                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l1dcache.demandHits::total     12306087                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l1dcache.overallHits::processor.cores.core.data     12306087                       # number of overall hits (Count)
board.cache_hierarchy.clusters.l1dcache.overallHits::total     12306087                       # number of overall hits (Count)
board.cache_hierarchy.clusters.l1dcache.demandMisses::processor.cores.core.data        63828                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l1dcache.demandMisses::total        63828                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l1dcache.overallMisses::processor.cores.core.data        63828                       # number of overall misses (Count)
board.cache_hierarchy.clusters.l1dcache.overallMisses::total        63828                       # number of overall misses (Count)
board.cache_hierarchy.clusters.l1dcache.demandMissLatency::processor.cores.core.data    324021321                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.demandMissLatency::total    324021321                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.overallMissLatency::processor.cores.core.data    324021321                       # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.overallMissLatency::total    324021321                       # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.demandAccesses::processor.cores.core.data     12369915                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1dcache.demandAccesses::total     12369915                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1dcache.overallAccesses::processor.cores.core.data     12369915                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1dcache.overallAccesses::total     12369915                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1dcache.demandMissRate::processor.cores.core.data     0.005160                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.demandMissRate::total     0.005160                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.overallMissRate::processor.cores.core.data     0.005160                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.overallMissRate::total     0.005160                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.demandAvgMissLatency::processor.cores.core.data  5076.476170                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.demandAvgMissLatency::total  5076.476170                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.overallAvgMissLatency::processor.cores.core.data  5076.476170                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.overallAvgMissLatency::total  5076.476170                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.l1dcache.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.l1dcache.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.clusters.l1dcache.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.clusters.l1dcache.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.l1dcache.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.l1dcache.writebacks::writebacks        66235                       # number of writebacks (Count)
board.cache_hierarchy.clusters.l1dcache.writebacks::total        66235                       # number of writebacks (Count)
board.cache_hierarchy.clusters.l1dcache.demandMshrHits::processor.cores.core.data          263                       # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.demandMshrHits::total          263                       # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.overallMshrHits::processor.cores.core.data          263                       # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.overallMshrHits::total          263                       # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.demandMshrMisses::processor.cores.core.data        63565                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.demandMshrMisses::total        63565                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.overallMshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher         4489                       # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.overallMshrMisses::processor.cores.core.data        63565                       # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.overallMshrMisses::total        68054                       # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.demandMshrMissLatency::processor.cores.core.data    294246459                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.demandMshrMissLatency::total    294246459                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.overallMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher     38300495                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.overallMshrMissLatency::processor.cores.core.data    294246459                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.overallMshrMissLatency::total    332546954                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.demandMshrMissRate::processor.cores.core.data     0.005139                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.demandMshrMissRate::total     0.005139                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.overallMshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher          inf                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.overallMshrMissRate::processor.cores.core.data     0.005139                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.overallMshrMissRate::total     0.005502                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.demandAvgMshrMissLatency::processor.cores.core.data  4629.064092                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.demandAvgMshrMissLatency::total  4629.064092                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.overallAvgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher  8532.077300                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.overallAvgMshrMissLatency::processor.cores.core.data  4629.064092                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.overallAvgMshrMissLatency::total  4886.515914                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.replacements        67798                       # number of replacements (Count)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.mshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher         4489                       # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.mshrMisses::total         4489                       # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.mshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher     38300495                       # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.mshrMissLatency::total     38300495                       # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.mshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.mshrMissRate::total          inf                       # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.avgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher  8532.077300                       # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.HardPFReq.avgMshrMissLatency::total  8532.077300                       # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.ReadReq.hits::processor.cores.core.data     10213557                       # number of ReadReq hits (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.hits::total     10213557                       # number of ReadReq hits (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.misses::processor.cores.core.data        63243                       # number of ReadReq misses (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.misses::total        63243                       # number of ReadReq misses (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.missLatency::processor.cores.core.data    312671349                       # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.ReadReq.missLatency::total    312671349                       # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.ReadReq.accesses::processor.cores.core.data     10276800                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.accesses::total     10276800                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.missRate::processor.cores.core.data     0.006154                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.ReadReq.missRate::total     0.006154                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.ReadReq.avgMissLatency::processor.cores.core.data  4943.967696                       # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.ReadReq.avgMissLatency::total  4943.967696                       # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrHits::processor.cores.core.data          225                       # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrHits::total          225                       # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrMisses::processor.cores.core.data        63018                       # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrMisses::total        63018                       # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrMissLatency::processor.cores.core.data    283450266                       # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrMissLatency::total    283450266                       # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrMissRate::processor.cores.core.data     0.006132                       # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrMissRate::total     0.006132                       # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.ReadReq.avgMshrMissLatency::processor.cores.core.data  4497.925450                       # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.ReadReq.avgMshrMissLatency::total  4497.925450                       # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.WriteReq.hits::processor.cores.core.data      2092530                       # number of WriteReq hits (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.hits::total      2092530                       # number of WriteReq hits (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.misses::processor.cores.core.data          585                       # number of WriteReq misses (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.misses::total          585                       # number of WriteReq misses (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.missLatency::processor.cores.core.data     11349972                       # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.WriteReq.missLatency::total     11349972                       # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.WriteReq.accesses::processor.cores.core.data      2093115                       # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.accesses::total      2093115                       # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.missRate::processor.cores.core.data     0.000279                       # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.WriteReq.missRate::total     0.000279                       # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.WriteReq.avgMissLatency::processor.cores.core.data 19401.661538                       # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.WriteReq.avgMissLatency::total 19401.661538                       # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrHits::processor.cores.core.data           38                       # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrHits::total           38                       # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrMisses::processor.cores.core.data          547                       # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrMisses::total          547                       # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrMissLatency::processor.cores.core.data     10796193                       # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrMissLatency::total     10796193                       # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrMissRate::processor.cores.core.data     0.000261                       # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrMissRate::total     0.000261                       # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.WriteReq.avgMshrMissLatency::processor.cores.core.data 19737.098720                       # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.WriteReq.avgMshrMissLatency::total 19737.098720                       # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l1dcache.prefetcher.demandMshrMisses        63565                       # demands not covered by prefetchs (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfIssued        12178                       # number of hwpf issued (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfUnused         1864                       # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfUseful         2584                       # number of useful prefetch (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfUsefulButMiss            0                       # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.accuracy     0.212186                       # accuracy of the prefetcher (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.coverage     0.039063                       # coverage brought by this prefetcher (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfHitInCache         7574                       # number of prefetches hitting in cache (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfHitInMSHR          115                       # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfHitInWB            0                       # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfLate         7689                       # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfIdentified        12187                       # number of prefetch candidates identified (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfBufferHit            6                       # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfRemovedDemand            1                       # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfSpanPage          569                       # number of prefetches that crossed the page (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfUsefulSpanPage          394                       # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l1dcache.tags.tagsInUse   255.699390                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.tags.totalRefs     12374141                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.clusters.l1dcache.tags.sampledRefs        68054                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.clusters.l1dcache.tags.avgRefs   181.828269                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.clusters.l1dcache.tags.warmupTick       140526                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.clusters.l1dcache.tags.occupancies::cache_hierarchy.clusters.l1dcache.prefetcher    13.170908                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l1dcache.tags.occupancies::processor.cores.core.data   242.528483                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l1dcache.tags.avgOccs::cache_hierarchy.clusters.l1dcache.prefetcher     0.051449                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l1dcache.tags.avgOccs::processor.cores.core.data     0.947377                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l1dcache.tags.avgOccs::total     0.998826                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l1dcache.tags.occupanciesTaskId::1022          182                       # Occupied blocks per task id (Count)
board.cache_hierarchy.clusters.l1dcache.tags.occupanciesTaskId::1024           74                       # Occupied blocks per task id (Count)
board.cache_hierarchy.clusters.l1dcache.tags.ageTaskId_1022::0          142                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l1dcache.tags.ageTaskId_1022::1           40                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l1dcache.tags.ageTaskId_1024::0           72                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l1dcache.tags.ageTaskId_1024::3            2                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l1dcache.tags.ratioOccsTaskId::1022     0.710938                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.clusters.l1dcache.tags.ratioOccsTaskId::1024     0.289062                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.clusters.l1dcache.tags.tagAccesses     99027374                       # Number of tag accesses (Count)
board.cache_hierarchy.clusters.l1dcache.tags.dataAccesses     99027374                       # Number of data accesses (Count)
board.cache_hierarchy.clusters.l1dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l1icache.demandHits::processor.cores.core.inst      3208546                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l1icache.demandHits::total      3208546                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l1icache.overallHits::processor.cores.core.inst      3208546                       # number of overall hits (Count)
board.cache_hierarchy.clusters.l1icache.overallHits::total      3208546                       # number of overall hits (Count)
board.cache_hierarchy.clusters.l1icache.demandMisses::processor.cores.core.inst          912                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l1icache.demandMisses::total          912                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l1icache.overallMisses::processor.cores.core.inst          912                       # number of overall misses (Count)
board.cache_hierarchy.clusters.l1icache.overallMisses::total          912                       # number of overall misses (Count)
board.cache_hierarchy.clusters.l1icache.demandMissLatency::processor.cores.core.inst     53165115                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.demandMissLatency::total     53165115                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.overallMissLatency::processor.cores.core.inst     53165115                       # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.overallMissLatency::total     53165115                       # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.demandAccesses::processor.cores.core.inst      3209458                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1icache.demandAccesses::total      3209458                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1icache.overallAccesses::processor.cores.core.inst      3209458                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1icache.overallAccesses::total      3209458                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1icache.demandMissRate::processor.cores.core.inst     0.000284                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.demandMissRate::total     0.000284                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.overallMissRate::processor.cores.core.inst     0.000284                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.overallMissRate::total     0.000284                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.demandAvgMissLatency::processor.cores.core.inst 58295.082237                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.demandAvgMissLatency::total 58295.082237                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.overallAvgMissLatency::processor.cores.core.inst 58295.082237                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.overallAvgMissLatency::total 58295.082237                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.l1icache.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.l1icache.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.clusters.l1icache.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.clusters.l1icache.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.l1icache.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.l1icache.demandMshrHits::processor.cores.core.inst          214                       # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l1icache.demandMshrHits::total          214                       # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l1icache.overallMshrHits::processor.cores.core.inst          214                       # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l1icache.overallMshrHits::total          214                       # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l1icache.demandMshrMisses::processor.cores.core.inst          698                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l1icache.demandMshrMisses::total          698                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l1icache.overallMshrMisses::processor.cores.core.inst          698                       # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l1icache.overallMshrMisses::total          698                       # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l1icache.demandMshrMissLatency::processor.cores.core.inst     42401223                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.demandMshrMissLatency::total     42401223                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.overallMshrMissLatency::processor.cores.core.inst     42401223                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.overallMshrMissLatency::total     42401223                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.demandMshrMissRate::processor.cores.core.inst     0.000217                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.demandMshrMissRate::total     0.000217                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.overallMshrMissRate::processor.cores.core.inst     0.000217                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.overallMshrMissRate::total     0.000217                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.demandAvgMshrMissLatency::processor.cores.core.inst 60746.737822                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.demandAvgMshrMissLatency::total 60746.737822                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.overallAvgMshrMissLatency::processor.cores.core.inst 60746.737822                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.overallAvgMshrMissLatency::total 60746.737822                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.replacements          441                       # number of replacements (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.hits::processor.cores.core.inst      3208546                       # number of ReadReq hits (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.hits::total      3208546                       # number of ReadReq hits (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.misses::processor.cores.core.inst          912                       # number of ReadReq misses (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.misses::total          912                       # number of ReadReq misses (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.missLatency::processor.cores.core.inst     53165115                       # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.ReadReq.missLatency::total     53165115                       # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.ReadReq.accesses::processor.cores.core.inst      3209458                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.accesses::total      3209458                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.missRate::processor.cores.core.inst     0.000284                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.ReadReq.missRate::total     0.000284                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.ReadReq.avgMissLatency::processor.cores.core.inst 58295.082237                       # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.ReadReq.avgMissLatency::total 58295.082237                       # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrHits::processor.cores.core.inst          214                       # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrHits::total          214                       # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrMisses::processor.cores.core.inst          698                       # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrMisses::total          698                       # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrMissLatency::processor.cores.core.inst     42401223                       # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrMissLatency::total     42401223                       # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrMissRate::processor.cores.core.inst     0.000217                       # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrMissRate::total     0.000217                       # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.ReadReq.avgMshrMissLatency::processor.cores.core.inst 60746.737822                       # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.ReadReq.avgMshrMissLatency::total 60746.737822                       # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l1icache.prefetcher.demandMshrMisses          698                       # demands not covered by prefetchs (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfIssued            0                       # number of hwpf issued (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfUseful            0                       # number of useful prefetch (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfUsefulButMiss            0                       # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.accuracy          nan                       # accuracy of the prefetcher (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.coverage            0                       # coverage brought by this prefetcher (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfHitInCache            0                       # number of prefetches hitting in cache (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfHitInMSHR            0                       # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfHitInWB            0                       # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfLate            0                       # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfRemovedDemand            0                       # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfSpanPage            0                       # number of prefetches that crossed the page (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfUsefulSpanPage            0                       # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l1icache.tags.tagsInUse   255.805965                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.tags.totalRefs      3209243                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.clusters.l1icache.tags.sampledRefs          697                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.clusters.l1icache.tags.avgRefs  4604.365854                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.clusters.l1icache.tags.warmupTick        70596                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.clusters.l1icache.tags.occupancies::processor.cores.core.inst   255.805965                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l1icache.tags.avgOccs::processor.cores.core.inst     0.999242                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l1icache.tags.avgOccs::total     0.999242                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l1icache.tags.occupanciesTaskId::1024          256                       # Occupied blocks per task id (Count)
board.cache_hierarchy.clusters.l1icache.tags.ageTaskId_1024::0          135                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l1icache.tags.ageTaskId_1024::1            6                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l1icache.tags.ageTaskId_1024::3          115                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l1icache.tags.ratioOccsTaskId::1024            1                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.clusters.l1icache.tags.tagAccesses     25676361                       # Number of tag accesses (Count)
board.cache_hierarchy.clusters.l1icache.tags.dataAccesses     25676361                       # Number of data accesses (Count)
board.cache_hierarchy.clusters.l1icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l2_bus.transDist::ReadResp        68204                       # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::WritebackDirty        66235                       # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::CleanEvict         2005                       # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::HardPFReq         2059                       # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::ReadExReq          547                       # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::ReadExResp          547                       # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::ReadSharedReq        68205                       # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.pktCount_board.cache_hierarchy.clusters.l1dcache.mem_side_port::board.cache_hierarchy.clusters.l2cache.cpu_side_port       203906                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.clusters.l2_bus.pktCount_board.cache_hierarchy.clusters.l1icache.mem_side_port::board.cache_hierarchy.clusters.l2cache.cpu_side_port         1836                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.clusters.l2_bus.pktCount::total       205742                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.clusters.l2_bus.pktSize_board.cache_hierarchy.clusters.l1dcache.mem_side_port::board.cache_hierarchy.clusters.l2cache.cpu_side_port      8594496                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.clusters.l2_bus.pktSize_board.cache_hierarchy.clusters.l1icache.mem_side_port::board.cache_hierarchy.clusters.l2cache.cpu_side_port        44608                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.clusters.l2_bus.pktSize::total      8639104                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.clusters.l2_bus.snoops         2060                       # Total snoops (Count)
board.cache_hierarchy.clusters.l2_bus.snoopTraffic            0                       # Total snoop traffic (Byte)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::samples        70812                       # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::mean     0.000042                       # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::stdev     0.006509                       # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::underflows            0      0.00%      0.00% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::0        70809    100.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::1            3      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::2            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::3            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::4            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::overflows            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::min_value            0                       # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::max_value            1                       # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::total        70812                       # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l2_bus.reqLayer0.occupancy     90476028                       # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.clusters.l2_bus.reqLayer0.utilization          0.0                       # Layer utilization (Ratio)
board.cache_hierarchy.clusters.l2_bus.respLayer0.occupancy     67985946                       # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.clusters.l2_bus.respLayer0.utilization          0.0                       # Layer utilization (Ratio)
board.cache_hierarchy.clusters.l2_bus.respLayer1.occupancy       696303                       # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.clusters.l2_bus.respLayer1.utilization          0.0                       # Layer utilization (Ratio)
board.cache_hierarchy.clusters.l2_bus.snoop_filter.totRequests       136991                       # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.clusters.l2_bus.snoop_filter.hitSingleRequests        68239                       # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.clusters.l2_bus.snoop_filter.hitMultiRequests            2                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.clusters.l2_bus.snoop_filter.totSnoops            1                       # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.clusters.l2_bus.snoop_filter.hitSingleSnoops            1                       # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.clusters.l2_bus.snoop_filter.hitMultiSnoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.clusters.l2cache.demandHits::cache_hierarchy.clusters.l1dcache.prefetcher         4285                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l2cache.demandHits::processor.cores.core.inst           25                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l2cache.demandHits::processor.cores.core.data        63288                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l2cache.demandHits::total        67598                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l2cache.overallHits::cache_hierarchy.clusters.l1dcache.prefetcher         4285                       # number of overall hits (Count)
board.cache_hierarchy.clusters.l2cache.overallHits::processor.cores.core.inst           25                       # number of overall hits (Count)
board.cache_hierarchy.clusters.l2cache.overallHits::processor.cores.core.data        63288                       # number of overall hits (Count)
board.cache_hierarchy.clusters.l2cache.overallHits::total        67598                       # number of overall hits (Count)
board.cache_hierarchy.clusters.l2cache.demandMisses::cache_hierarchy.clusters.l1dcache.prefetcher          204                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMisses::processor.cores.core.inst          673                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMisses::processor.cores.core.data          277                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMisses::total         1154                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMisses::cache_hierarchy.clusters.l1dcache.prefetcher          204                       # number of overall misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMisses::processor.cores.core.inst          673                       # number of overall misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMisses::processor.cores.core.data          277                       # number of overall misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMisses::total         1154                       # number of overall misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher     16438722                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMissLatency::processor.cores.core.inst     41840784                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMissLatency::processor.cores.core.data     19971009                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMissLatency::total     78250515                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher     16438722                       # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMissLatency::processor.cores.core.inst     41840784                       # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMissLatency::processor.cores.core.data     19971009                       # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMissLatency::total     78250515                       # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandAccesses::cache_hierarchy.clusters.l1dcache.prefetcher         4489                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.demandAccesses::processor.cores.core.inst          698                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.demandAccesses::processor.cores.core.data        63565                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.demandAccesses::total        68752                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.overallAccesses::cache_hierarchy.clusters.l1dcache.prefetcher         4489                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.overallAccesses::processor.cores.core.inst          698                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.overallAccesses::processor.cores.core.data        63565                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.overallAccesses::total        68752                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.demandMissRate::cache_hierarchy.clusters.l1dcache.prefetcher     0.045444                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMissRate::processor.cores.core.inst     0.964183                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMissRate::processor.cores.core.data     0.004358                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMissRate::total     0.016785                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMissRate::cache_hierarchy.clusters.l1dcache.prefetcher     0.045444                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMissRate::processor.cores.core.inst     0.964183                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMissRate::processor.cores.core.data     0.004358                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMissRate::total     0.016785                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandAvgMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 80581.970588                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMissLatency::processor.cores.core.inst 62170.555721                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMissLatency::processor.cores.core.data 72097.505415                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMissLatency::total 67808.071924                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 80581.970588                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMissLatency::processor.cores.core.inst 62170.555721                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMissLatency::processor.cores.core.data 72097.505415                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMissLatency::total 67808.071924                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.l2cache.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.l2cache.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.clusters.l2cache.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.clusters.l2cache.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.l2cache.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.l2cache.demandMshrHits::cache_hierarchy.clusters.l1dcache.prefetcher          158                       # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrHits::total          158                       # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrHits::cache_hierarchy.clusters.l1dcache.prefetcher          158                       # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrHits::total          158                       # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher           46                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrMisses::processor.cores.core.inst          673                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrMisses::processor.cores.core.data          277                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrMisses::total          996                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher           46                       # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrMisses::cache_hierarchy.clusters.l2cache.prefetcher         1827                       # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrMisses::processor.cores.core.inst          673                       # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrMisses::processor.cores.core.data          277                       # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrMisses::total         2823                       # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher      4944711                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMshrMissLatency::processor.cores.core.inst     41617008                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMshrMissLatency::processor.cores.core.data     19878768                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMshrMissLatency::total     66440487                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher      4944711                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher    120923823                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrMissLatency::processor.cores.core.inst     41617008                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrMissLatency::processor.cores.core.data     19878768                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrMissLatency::total    187364310                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher     0.010247                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMshrMissRate::processor.cores.core.inst     0.964183                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMshrMissRate::processor.cores.core.data     0.004358                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMshrMissRate::total     0.014487                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher     0.010247                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMshrMissRate::cache_hierarchy.clusters.l2cache.prefetcher          inf                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMshrMissRate::processor.cores.core.inst     0.964183                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMshrMissRate::processor.cores.core.data     0.004358                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMshrMissRate::total     0.041061                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandAvgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 107493.717391                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMshrMissLatency::processor.cores.core.inst 61838.050520                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMshrMissLatency::processor.cores.core.data 71764.505415                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMshrMissLatency::total 66707.316265                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 107493.717391                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 66187.095238                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrMissLatency::processor.cores.core.inst 61838.050520                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrMissLatency::processor.cores.core.data 71764.505415                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrMissLatency::total 66370.637620                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.replacements            1                       # number of replacements (Count)
board.cache_hierarchy.clusters.l2cache.HardPFReq.mshrMisses::cache_hierarchy.clusters.l2cache.prefetcher         1827                       # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.HardPFReq.mshrMisses::total         1827                       # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.HardPFReq.mshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher    120923823                       # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.HardPFReq.mshrMissLatency::total    120923823                       # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.HardPFReq.mshrMissRate::cache_hierarchy.clusters.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.HardPFReq.mshrMissRate::total          inf                       # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.HardPFReq.avgMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 66187.095238                       # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.HardPFReq.avgMshrMissLatency::total 66187.095238                       # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadExReq.hits::processor.cores.core.data          435                       # number of ReadExReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.hits::total          435                       # number of ReadExReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.misses::processor.cores.core.data          112                       # number of ReadExReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.misses::total          112                       # number of ReadExReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.missLatency::processor.cores.core.data      8831493                       # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadExReq.missLatency::total      8831493                       # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadExReq.accesses::processor.cores.core.data          547                       # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.accesses::total          547                       # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.missRate::processor.cores.core.data     0.204753                       # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadExReq.missRate::total     0.204753                       # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadExReq.avgMissLatency::processor.cores.core.data 78852.616071                       # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadExReq.avgMissLatency::total 78852.616071                       # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadExReq.mshrMisses::processor.cores.core.data          112                       # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.mshrMisses::total          112                       # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.mshrMissLatency::processor.cores.core.data      8794197                       # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadExReq.mshrMissLatency::total      8794197                       # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadExReq.mshrMissRate::processor.cores.core.data     0.204753                       # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadExReq.mshrMissRate::total     0.204753                       # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadExReq.avgMshrMissLatency::processor.cores.core.data 78519.616071                       # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadExReq.avgMshrMissLatency::total 78519.616071                       # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.hits::cache_hierarchy.clusters.l1dcache.prefetcher         4285                       # number of ReadSharedReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.hits::processor.cores.core.inst           25                       # number of ReadSharedReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.hits::processor.cores.core.data        62853                       # number of ReadSharedReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.hits::total        67163                       # number of ReadSharedReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.misses::cache_hierarchy.clusters.l1dcache.prefetcher          204                       # number of ReadSharedReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.misses::processor.cores.core.inst          673                       # number of ReadSharedReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.misses::processor.cores.core.data          165                       # number of ReadSharedReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.misses::total         1042                       # number of ReadSharedReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missLatency::cache_hierarchy.clusters.l1dcache.prefetcher     16438722                       # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missLatency::processor.cores.core.inst     41840784                       # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missLatency::processor.cores.core.data     11139516                       # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missLatency::total     69419022                       # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.accesses::cache_hierarchy.clusters.l1dcache.prefetcher         4489                       # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.accesses::processor.cores.core.inst          698                       # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.accesses::processor.cores.core.data        63018                       # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.accesses::total        68205                       # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missRate::cache_hierarchy.clusters.l1dcache.prefetcher     0.045444                       # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missRate::processor.cores.core.inst     0.964183                       # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missRate::processor.cores.core.data     0.002618                       # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missRate::total     0.015277                       # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 80581.970588                       # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMissLatency::processor.cores.core.inst 62170.555721                       # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMissLatency::processor.cores.core.data 67512.218182                       # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMissLatency::total 66620.942418                       # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrHits::cache_hierarchy.clusters.l1dcache.prefetcher          158                       # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrHits::total          158                       # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher           46                       # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMisses::processor.cores.core.inst          673                       # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMisses::processor.cores.core.data          165                       # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMisses::total          884                       # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher      4944711                       # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissLatency::processor.cores.core.inst     41617008                       # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissLatency::processor.cores.core.data     11084571                       # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissLatency::total     57646290                       # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher     0.010247                       # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissRate::processor.cores.core.inst     0.964183                       # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissRate::processor.cores.core.data     0.002618                       # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissRate::total     0.012961                       # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 107493.717391                       # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.inst 61838.050520                       # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.data 67179.218182                       # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMshrMissLatency::total 65210.735294                       # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.WritebackDirty.hits::writebacks        66235                       # number of WritebackDirty hits (Count)
board.cache_hierarchy.clusters.l2cache.WritebackDirty.hits::total        66235                       # number of WritebackDirty hits (Count)
board.cache_hierarchy.clusters.l2cache.WritebackDirty.accesses::writebacks        66235                       # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.WritebackDirty.accesses::total        66235                       # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l2cache.prefetcher.demandMshrMisses          996                       # demands not covered by prefetchs (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfIssued         6855                       # number of hwpf issued (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfUseful         1667                       # number of useful prefetch (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfUsefulButMiss            0                       # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.accuracy     0.243180                       # accuracy of the prefetcher (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.coverage     0.625986                       # coverage brought by this prefetcher (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfHitInCache         4724                       # number of prefetches hitting in cache (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfHitInMSHR          304                       # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfHitInWB            0                       # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfLate         5028                       # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfIdentified         7275                       # number of prefetch candidates identified (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfBufferHit          279                       # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfRemovedDemand          106                       # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfSpanPage          361                       # number of prefetches that crossed the page (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfUsefulSpanPage          259                       # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l2cache.tags.tagsInUse  2340.421589                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.tags.totalRefs       138657                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.clusters.l2cache.tags.sampledRefs         2822                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.clusters.l2cache.tags.avgRefs    49.134302                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.clusters.l2cache.tags.warmupTick        69930                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.clusters.l2cache.tags.occupancies::cache_hierarchy.clusters.l1dcache.prefetcher    40.659159                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l2cache.tags.occupancies::cache_hierarchy.clusters.l2cache.prefetcher  1530.153723                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l2cache.tags.occupancies::processor.cores.core.inst   531.239982                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l2cache.tags.occupancies::processor.cores.core.data   238.368724                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::cache_hierarchy.clusters.l1dcache.prefetcher     0.009927                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::cache_hierarchy.clusters.l2cache.prefetcher     0.373573                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::processor.cores.core.inst     0.129697                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::processor.cores.core.data     0.058195                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::total     0.571392                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.occupanciesTaskId::1022         1873                       # Occupied blocks per task id (Count)
board.cache_hierarchy.clusters.l2cache.tags.occupanciesTaskId::1024          948                       # Occupied blocks per task id (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1022::2           55                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1022::3         1818                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1024::0          166                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1024::1            7                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1024::2            1                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1024::3          774                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ratioOccsTaskId::1022     0.457275                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.clusters.l2cache.tags.ratioOccsTaskId::1024     0.231445                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.clusters.l2cache.tags.tagAccesses      2194646                       # Number of tag accesses (Count)
board.cache_hierarchy.clusters.l2cache.tags.dataAccesses      2194646                       # Number of data accesses (Count)
board.cache_hierarchy.clusters.l2cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l3_bus.transDist::ReadResp         2710                       # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::ReadExReq          112                       # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::ReadExResp          112                       # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::ReadSharedReq         2711                       # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.pktCount_board.cache_hierarchy.clusters.l2cache.mem_side_port::board.cache_hierarchy.l3_cache.cpu_side_port         5645                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l3_bus.pktSize_board.cache_hierarchy.clusters.l2cache.mem_side_port::board.cache_hierarchy.l3_cache.cpu_side_port       180608                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l3_bus.snoops                 0                       # Total snoops (Count)
board.cache_hierarchy.l3_bus.snoopTraffic            0                       # Total snoop traffic (Byte)
board.cache_hierarchy.l3_bus.snoopFanout::samples         2823                       # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::mean            0                       # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::stdev            0                       # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::underflows            0      0.00%      0.00% # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::0         2823    100.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::1            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::overflows            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::min_value            0                       # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::max_value            0                       # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::total         2823                       # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l3_bus.reqLayer0.occupancy      1451428                       # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l3_bus.reqLayer0.utilization          0.0                       # Layer utilization (Ratio)
board.cache_hierarchy.l3_bus.respLayer0.occupancy      2819178                       # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l3_bus.respLayer0.utilization          0.0                       # Layer utilization (Ratio)
board.cache_hierarchy.l3_bus.snoop_filter.totRequests         2823                       # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l3_bus.snoop_filter.hitSingleRequests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l3_bus.snoop_filter.hitMultiRequests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l3_bus.snoop_filter.totSnoops            0                       # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l3_bus.snoop_filter.hitSingleSnoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l3_bus.snoop_filter.hitMultiSnoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l3_cache.demandMisses::cache_hierarchy.clusters.l1dcache.prefetcher           46                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l3_cache.demandMisses::cache_hierarchy.clusters.l2cache.prefetcher         1827                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l3_cache.demandMisses::processor.cores.core.inst          673                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l3_cache.demandMisses::processor.cores.core.data          277                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l3_cache.demandMisses::total         2823                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l3_cache.overallMisses::cache_hierarchy.clusters.l1dcache.prefetcher           46                       # number of overall misses (Count)
board.cache_hierarchy.l3_cache.overallMisses::cache_hierarchy.clusters.l2cache.prefetcher         1827                       # number of overall misses (Count)
board.cache_hierarchy.l3_cache.overallMisses::processor.cores.core.inst          673                       # number of overall misses (Count)
board.cache_hierarchy.l3_cache.overallMisses::processor.cores.core.data          277                       # number of overall misses (Count)
board.cache_hierarchy.l3_cache.overallMisses::total         2823                       # number of overall misses (Count)
board.cache_hierarchy.l3_cache.demandMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher      4759575                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMissLatency::cache_hierarchy.clusters.l2cache.prefetcher    120231523                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMissLatency::processor.cores.core.inst     38931696                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMissLatency::processor.cores.core.data     18771876                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMissLatency::total    182694670                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher      4759575                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMissLatency::cache_hierarchy.clusters.l2cache.prefetcher    120231523                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMissLatency::processor.cores.core.inst     38931696                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMissLatency::processor.cores.core.data     18771876                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMissLatency::total    182694670                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandAccesses::cache_hierarchy.clusters.l1dcache.prefetcher           46                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.demandAccesses::cache_hierarchy.clusters.l2cache.prefetcher         1827                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.demandAccesses::processor.cores.core.inst          673                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.demandAccesses::processor.cores.core.data          277                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.demandAccesses::total         2823                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.overallAccesses::cache_hierarchy.clusters.l1dcache.prefetcher           46                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.overallAccesses::cache_hierarchy.clusters.l2cache.prefetcher         1827                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.overallAccesses::processor.cores.core.inst          673                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.overallAccesses::processor.cores.core.data          277                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.overallAccesses::total         2823                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.demandMissRate::cache_hierarchy.clusters.l1dcache.prefetcher            1                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMissRate::cache_hierarchy.clusters.l2cache.prefetcher            1                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMissRate::processor.cores.core.inst            1                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMissRate::processor.cores.core.data            1                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMissRate::total            1                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMissRate::cache_hierarchy.clusters.l1dcache.prefetcher            1                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMissRate::cache_hierarchy.clusters.l2cache.prefetcher            1                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMissRate::processor.cores.core.inst            1                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMissRate::processor.cores.core.data            1                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMissRate::total            1                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.demandAvgMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 103469.021739                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 65808.168035                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMissLatency::processor.cores.core.inst 57847.988113                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMissLatency::processor.cores.core.data 67768.505415                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMissLatency::total 64716.496635                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 103469.021739                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 65808.168035                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMissLatency::processor.cores.core.inst 57847.988113                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMissLatency::processor.cores.core.data 67768.505415                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMissLatency::total 64716.496635                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l3_cache.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l3_cache.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l3_cache.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l3_cache.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l3_cache.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l3_cache.demandMshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher           46                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l3_cache.demandMshrMisses::cache_hierarchy.clusters.l2cache.prefetcher         1827                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l3_cache.demandMshrMisses::processor.cores.core.inst          673                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l3_cache.demandMshrMisses::processor.cores.core.data          277                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l3_cache.demandMshrMisses::total         2823                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher           46                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrMisses::cache_hierarchy.clusters.l2cache.prefetcher         1827                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrMisses::processor.cores.core.inst          673                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrMisses::processor.cores.core.data          277                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrMisses::total         2823                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l3_cache.demandMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher      4744257                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher    119623132                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMshrMissLatency::processor.cores.core.inst     38707920                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMshrMissLatency::processor.cores.core.data     18679635                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMshrMissLatency::total    181754944                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher      4744257                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher    119623132                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrMissLatency::processor.cores.core.inst     38707920                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrMissLatency::processor.cores.core.data     18679635                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrMissLatency::total    181754944                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher            1                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMshrMissRate::cache_hierarchy.clusters.l2cache.prefetcher            1                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMshrMissRate::processor.cores.core.inst            1                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMshrMissRate::processor.cores.core.data            1                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMshrMissRate::total            1                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher            1                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMshrMissRate::cache_hierarchy.clusters.l2cache.prefetcher            1                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMshrMissRate::processor.cores.core.inst            1                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMshrMissRate::processor.cores.core.data            1                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMshrMissRate::total            1                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.demandAvgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 103136.021739                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 65475.168035                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMshrMissLatency::processor.cores.core.inst 57515.482912                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMshrMissLatency::processor.cores.core.data 67435.505415                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMshrMissLatency::total 64383.614594                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 103136.021739                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 65475.168035                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrMissLatency::processor.cores.core.inst 57515.482912                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrMissLatency::processor.cores.core.data 67435.505415                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrMissLatency::total 64383.614594                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.replacements            0                       # number of replacements (Count)
board.cache_hierarchy.l3_cache.ReadExReq.misses::processor.cores.core.data          112                       # number of ReadExReq misses (Count)
board.cache_hierarchy.l3_cache.ReadExReq.misses::total          112                       # number of ReadExReq misses (Count)
board.cache_hierarchy.l3_cache.ReadExReq.missLatency::processor.cores.core.data      8346645                       # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadExReq.missLatency::total      8346645                       # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadExReq.accesses::processor.cores.core.data          112                       # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadExReq.accesses::total          112                       # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadExReq.missRate::processor.cores.core.data            1                       # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadExReq.missRate::total            1                       # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadExReq.avgMissLatency::processor.cores.core.data 74523.616071                       # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadExReq.avgMissLatency::total 74523.616071                       # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadExReq.mshrMisses::processor.cores.core.data          112                       # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadExReq.mshrMisses::total          112                       # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadExReq.mshrMissLatency::processor.cores.core.data      8309349                       # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadExReq.mshrMissLatency::total      8309349                       # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadExReq.mshrMissRate::processor.cores.core.data            1                       # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadExReq.mshrMissRate::total            1                       # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadExReq.avgMshrMissLatency::processor.cores.core.data 74190.616071                       # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadExReq.avgMshrMissLatency::total 74190.616071                       # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.misses::cache_hierarchy.clusters.l1dcache.prefetcher           46                       # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.misses::cache_hierarchy.clusters.l2cache.prefetcher         1827                       # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.misses::processor.cores.core.inst          673                       # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.misses::processor.cores.core.data          165                       # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.misses::total         2711                       # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.missLatency::cache_hierarchy.clusters.l1dcache.prefetcher      4759575                       # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.missLatency::cache_hierarchy.clusters.l2cache.prefetcher    120231523                       # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.missLatency::processor.cores.core.inst     38931696                       # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.missLatency::processor.cores.core.data     10425231                       # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.missLatency::total    174348025                       # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.accesses::cache_hierarchy.clusters.l1dcache.prefetcher           46                       # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.accesses::cache_hierarchy.clusters.l2cache.prefetcher         1827                       # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.accesses::processor.cores.core.inst          673                       # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.accesses::processor.cores.core.data          165                       # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.accesses::total         2711                       # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.missRate::cache_hierarchy.clusters.l1dcache.prefetcher            1                       # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.missRate::cache_hierarchy.clusters.l2cache.prefetcher            1                       # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.missRate::processor.cores.core.inst            1                       # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.missRate::processor.cores.core.data            1                       # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.missRate::total            1                       # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 103469.021739                       # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 65808.168035                       # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMissLatency::processor.cores.core.inst 57847.988113                       # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMissLatency::processor.cores.core.data 63183.218182                       # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMissLatency::total 64311.333456                       # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher           46                       # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMisses::cache_hierarchy.clusters.l2cache.prefetcher         1827                       # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMisses::processor.cores.core.inst          673                       # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMisses::processor.cores.core.data          165                       # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMisses::total         2711                       # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher      4744257                       # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher    119623132                       # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissLatency::processor.cores.core.inst     38707920                       # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissLatency::processor.cores.core.data     10370286                       # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissLatency::total    173445595                       # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher            1                       # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissRate::cache_hierarchy.clusters.l2cache.prefetcher            1                       # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissRate::processor.cores.core.inst            1                       # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissRate::processor.cores.core.data            1                       # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissRate::total            1                       # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 103136.021739                       # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 65475.168035                       # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.inst 57515.482912                       # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.data 62850.218182                       # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMshrMissLatency::total 63978.456289                       # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l3_cache.tags.tagsInUse  2340.421854                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l3_cache.tags.totalRefs         2822                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l3_cache.tags.sampledRefs         2822                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l3_cache.tags.avgRefs            1                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l3_cache.tags.warmupTick        69264                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l3_cache.tags.occupancies::cache_hierarchy.clusters.l1dcache.prefetcher    40.659163                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l3_cache.tags.occupancies::cache_hierarchy.clusters.l2cache.prefetcher  1530.153852                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l3_cache.tags.occupancies::processor.cores.core.inst   531.240096                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l3_cache.tags.occupancies::processor.cores.core.data   238.368744                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::cache_hierarchy.clusters.l1dcache.prefetcher     0.000310                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::cache_hierarchy.clusters.l2cache.prefetcher     0.011674                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::processor.cores.core.inst     0.004053                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::processor.cores.core.data     0.001819                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::total     0.017856                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.occupanciesTaskId::1022         1873                       # Occupied blocks per task id (Count)
board.cache_hierarchy.l3_cache.tags.occupanciesTaskId::1024          949                       # Occupied blocks per task id (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1022::2           55                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1022::3         1818                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1024::0          166                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1024::1            7                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1024::2            1                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1024::3          775                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ratioOccsTaskId::1022     0.014290                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l3_cache.tags.ratioOccsTaskId::1024     0.007240                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l3_cache.tags.tagAccesses        47990                       # Number of tag accesses (Count)
board.cache_hierarchy.l3_cache.tags.dataAccesses        47990                       # Number of data accesses (Count)
board.cache_hierarchy.l3_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.transDist::ReadResp         2710                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq          112                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp          112                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq         2710                       # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l3_cache.mem_side_port::board.memory.mem_ctrl.port         5644                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l3_cache.mem_side_port::total         5644                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total         5644                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l3_cache.mem_side_port::board.memory.mem_ctrl.port       180608                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l3_cache.mem_side_port::total       180608                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total       180608                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops                 0                       # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic            0                       # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples         2822                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows            0      0.00%      0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0         2822    100.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total         2822                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy       948170                       # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization          0.0                       # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer1.occupancy      2412298                       # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer1.utilization          0.0                       # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests         2822                       # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops            0                       # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock                            333                       # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage             1                       # Voltage in Volts (Volt)
board.memory.mem_ctrl.avgPriority_cache_hierarchy.clusters.l1dcache.prefetcher::samples        46.00                       # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_cache_hierarchy.clusters.l2cache.prefetcher::samples      1827.00                       # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.inst::samples       672.00                       # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.data::samples       277.00                       # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.priorityMinLatency 0.000000017492                       # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl.priorityMaxLatency 0.000000817660                       # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl.numReadWriteTurnArounds            0                       # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl.numWriteReadTurnArounds            0                       # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl.numStayReadState           7856                       # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl.numStayWriteState             0                       # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl.readReqs                   2822                       # Number of read requests accepted (Count)
board.memory.mem_ctrl.writeReqs                     0                       # Number of write requests accepted (Count)
board.memory.mem_ctrl.readBursts                 2822                       # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl.writeBursts                   0                       # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl.servicedByWrQ                 0                       # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl.mergedWrBursts                0                       # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl.avgRdQLen                  1.17                       # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.avgWrQLen                  0.00                       # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.numRdRetry                    0                       # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl.numWrRetry                    0                       # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl.readPktSize::0                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::1                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::2                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::3                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::4                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::5                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::6             2822                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::0               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::1               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::2               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::3               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::4               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::5               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::6               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.rdQLenPdf::0               1608                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::1                751                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::2                141                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::3                 77                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::4                 55                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::5                 50                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::6                 42                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::7                 41                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::8                 37                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::9                 13                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::10                 4                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::11                 2                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::12                 1                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::13                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::14                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::15                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::16                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::17                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::18                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::19                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::20                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::21                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::22                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::23                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::24                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::25                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::26                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::27                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::28                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::29                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::30                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::31                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::32                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::33                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::34                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::35                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::36                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::37                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::38                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::39                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::40                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::41                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::42                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::43                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::44                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::45                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::46                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::47                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::48                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::49                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::50                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::51                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::52                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::53                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::54                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::55                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::56                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::57                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::58                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::59                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::60                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::61                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::62                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::63                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::0                  0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::1                  0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::2                  0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::3                  0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::4                  0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::5                  0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::6                  0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::7                  0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::8                  0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::9                  0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::10                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::11                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::12                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::13                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::14                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::15                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::16                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::17                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::18                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::19                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::20                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::21                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::22                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::23                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::24                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::25                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::26                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::27                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::28                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::29                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::30                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::31                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::32                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::33                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::34                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::35                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::36                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::37                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::38                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::39                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::40                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::41                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::42                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::43                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::44                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::45                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::46                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::47                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::48                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::49                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::50                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::51                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::52                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::53                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::54                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::55                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::56                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::57                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::58                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::59                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::60                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::61                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::62                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::63                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::64                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::65                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::66                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::67                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::68                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::69                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::70                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::71                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::72                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::73                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::74                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::75                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::76                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::77                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::78                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::79                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::80                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::81                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::82                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::83                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::84                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::85                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::86                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::87                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::88                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::89                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::90                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::91                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::92                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::93                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::94                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::95                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::96                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::97                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::98                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::99                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::100                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::101                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::102                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::103                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::104                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::105                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::106                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::107                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::108                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::109                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::110                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::111                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::112                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::113                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::114                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::115                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::116                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::117                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::118                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::119                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::120                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::121                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::122                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::123                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::124                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::125                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::126                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::127                0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.bytesReadWrQ                  0                       # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl.bytesReadSys             180608                       # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl.bytesWrittenSys               0                       # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl.avgRdBWSys         19062930.88195340                       # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.avgWrBWSys           0.00000000                       # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.totGap               9474241608                       # Total gap between requests (Tick)
board.memory.mem_ctrl.avgGap               3357279.10                       # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl.requestorReadBytes::cache_hierarchy.clusters.l1dcache.prefetcher         2944                       # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::cache_hierarchy.clusters.l2cache.prefetcher       116928                       # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.inst        43008                       # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.data        17728                       # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadRate::cache_hierarchy.clusters.l1dcache.prefetcher 310735.230535030656                       # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::cache_hierarchy.clusters.l2cache.prefetcher 12341592.743206543848                       # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.inst 4539436.411294360645                       # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.data 1871166.496917467099                       # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadAccesses::cache_hierarchy.clusters.l1dcache.prefetcher           46                       # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::cache_hierarchy.clusters.l2cache.prefetcher         1827                       # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.inst          672                       # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.data          277                       # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadTotalLat::cache_hierarchy.clusters.l1dcache.prefetcher      3339827                       # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::cache_hierarchy.clusters.l2cache.prefetcher     62815404                       # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.inst     18225813                       # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.data     10229708                       # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadAvgLat::cache_hierarchy.clusters.l1dcache.prefetcher     72604.93                       # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::cache_hierarchy.clusters.l2cache.prefetcher     34381.72                       # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.inst     27121.75                       # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.data     36930.35                       # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.dram.bytesRead::cache_hierarchy.clusters.l1dcache.prefetcher         2944                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::cache_hierarchy.clusters.l2cache.prefetcher       116928                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.inst        43008                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.data        17728                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::total       180608                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::processor.cores.core.inst        43008                       # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::total        43008                       # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.numReads::cache_hierarchy.clusters.l1dcache.prefetcher           46                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::cache_hierarchy.clusters.l2cache.prefetcher         1827                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.inst          672                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.data          277                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::total         2822                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.bwRead::cache_hierarchy.clusters.l1dcache.prefetcher       310735                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::cache_hierarchy.clusters.l2cache.prefetcher     12341593                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.inst      4539436                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.data      1871166                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::total     19062931                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::processor.cores.core.inst      4539436                       # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::total      4539436                       # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::cache_hierarchy.clusters.l1dcache.prefetcher       310735                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::cache_hierarchy.clusters.l2cache.prefetcher     12341593                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.inst      4539436                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.data      1871166                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::total     19062931                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.readBursts            2822                       # Number of DRAM read bursts (Count)
board.memory.mem_ctrl.dram.writeBursts              0                       # Number of DRAM write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::0          166                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::1          101                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::2           66                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::3           79                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::4          104                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::5          128                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::6          128                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::7          143                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::8          167                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::9          136                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::10          248                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::11          156                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::12          143                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::13          142                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::14          156                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::15          161                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::16          142                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::17          153                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::18           97                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::19           24                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::20           28                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::21           15                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::22            3                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::23            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::24            1                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::25           18                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::26           21                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::27           10                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::28            4                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::29            8                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::30           24                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::31           50                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::0            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::1            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::2            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::3            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::4            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::5            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::6            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::7            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::8            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::9            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::10            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::11            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::12            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::13            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::14            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::15            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::16            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::17            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::18            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::19            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::20            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::21            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::22            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::23            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::24            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::25            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::26            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::27            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::28            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::29            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::30            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::31            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.totQLat           45248328                       # Total ticks spent queuing (Tick)
board.memory.mem_ctrl.dram.totBusLat          9402904                       # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl.dram.totMemAccLat      94610752                       # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl.dram.avgQLat           16034.13                       # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgBusLat          3332.00                       # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgMemAccLat      33526.13                       # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.readRowHits           1995                       # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl.dram.writeRowHits             0                       # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl.dram.readRowHitRate        70.69                       # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl.dram.writeRowHitRate          nan                       # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl.dram.bytesPerActivate::samples          807                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::mean   218.884758                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::gmean   113.935892                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::stdev   312.987946                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::0-127          562     69.64%     69.64% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::128-255           70      8.67%     78.31% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::256-383           26      3.22%     81.54% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::384-511           24      2.97%     84.51% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::512-639           20      2.48%     86.99% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::640-767           10      1.24%     88.23% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::768-895            3      0.37%     88.60% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::896-1023            6      0.74%     89.34% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::1024-1151           86     10.66%    100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::total          807                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.dramBytesRead       180608                       # Total bytes read (Byte)
board.memory.mem_ctrl.dram.dramBytesWritten            0                       # Total bytes written (Byte)
board.memory.mem_ctrl.dram.avgRdBW          19.062931                       # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.avgWrBW                  0                       # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.peakBW            19207.00                       # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl.dram.busUtil               0.10                       # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl.dram.busUtilRead           0.10                       # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl.dram.busUtilWrite          0.00                       # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl.dram.pageHitRate          70.69                       # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl.dram.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl.dram.rank0.actEnergy 806197.392000                       # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preEnergy 1392966.590400                       # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.readEnergy 6100214.937600                       # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.writeEnergy            0                       # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.refreshEnergy 821840348.313606                       # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actBackEnergy 732452735.666396                       # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preBackEnergy 2586760369.804822                       # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actPowerDownEnergy            0                       # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.prePowerDownEnergy            0                       # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.selfRefreshEnergy            0                       # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.totalEnergy 4149352832.704803                       # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.averagePower   437.958597                       # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank0.totalIdleTime            0                       # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::IDLE   7904722833                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::REF    425600000                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::SREF            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::PRE_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT   1143981046                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.actEnergy 483406.560000                       # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preEnergy 828622.418400                       # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.readEnergy 1640255.635200                       # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.writeEnergy            0                       # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.refreshEnergy 821840348.313606                       # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actBackEnergy 660018029.143182                       # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preBackEnergy 2636766055.526383                       # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actPowerDownEnergy            0                       # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.prePowerDownEnergy            0                       # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.selfRefreshEnergy            0                       # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.totalEnergy 4121576717.596730                       # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.averagePower   435.026865                       # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank1.totalIdleTime            0                       # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::IDLE   8058414093                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::REF    425600000                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::SREF            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::PRE_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT    990289786                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles         28451364                       # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.cpi               1.064472                       # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores.core.ipc               0.939433                       # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores.core.numWorkItemsStarted            0                       # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted            0                       # Number of work items this cpu completed (Count)
board.processor.cores.core.instsAdded        41938859                       # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.cores.core.nonSpecInstsAdded            3                       # Number of non-speculative instructions added to the IQ (Count)
board.processor.cores.core.instsIssued       41394800                       # Number of instructions issued (Count)
board.processor.cores.core.squashedInstsIssued          429                       # Number of squashed instructions issued (Count)
board.processor.cores.core.squashedInstsExamined       842569                       # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
board.processor.cores.core.squashedOperandsExamined      2204665                       # Number of squashed operands that are examined and possibly removed from graph (Count)
board.processor.cores.core.squashedNonSpecRemoved            3                       # Number of squashed non-spec instructions that were removed (Count)
board.processor.cores.core.numIssuedDist::samples     28389125                       # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::mean     1.458122                       # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::stdev     1.302173                       # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::underflows            0      0.00%      0.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::0      7003988     24.67%     24.67% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::1     11054082     38.94%     63.61% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::2      4099210     14.44%     78.05% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::3      3036611     10.70%     88.74% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::4      3056240     10.77%     99.51% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::5        73971      0.26%     99.77% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::6        21890      0.08%     99.85% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::7        38754      0.14%     99.98% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::8         4379      0.02%    100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::overflows            0      0.00%    100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::min_value            0                       # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::max_value            8                       # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::total     28389125                       # Number of insts issued each cycle (Count)
board.processor.cores.core.statFuBusy::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntAlu        10279      1.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntMult            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntDiv            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatAdd            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCmp            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCvt            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMult            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMultAcc            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatDiv            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMisc            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatSqrt            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAdd            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAddAcc            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAlu           26      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCmp            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCvt            1      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMisc           13      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMult            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMultAcc            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMatMultAcc            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShift            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShiftAcc            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdDiv            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSqrt            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAdd            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAlu            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCmp            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCvt            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatDiv            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMisc            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMult            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMultAcc            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMatMultAcc            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatSqrt            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAdd            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAlu            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceCmp            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceAdd            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceCmp            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAes            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAesMix            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash2            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash2            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma2            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma3            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdPredAlu            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::Matrix            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MatrixMov            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MatrixOP            0      0.00%      1.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemRead      1019567     98.99%     99.99% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemWrite           40      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemRead           16      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemWrite           13      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IprAccess            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideLoad            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideStore            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideMaskLoad            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideMaskStore            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStridedLoad            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStridedStore            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdIndexedLoad            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdIndexedStore            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdWholeRegisterLoad            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdWholeRegisterStore            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedLoad            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedStore            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedFaultOnlyFirstLoad            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStrideSegmentedLoad            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStrideSegmentedStore            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdExt            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatExt            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdConfig            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statIssuedInstType_0::No_OpClass         1110      0.00%      0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntAlu     22796879     55.07%     55.07% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntMult      3050331      7.37%     62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntDiv          111      0.00%     62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatAdd          161      0.00%     62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCmp            0      0.00%     62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCvt            0      0.00%     62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMult            0      0.00%     62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMultAcc            0      0.00%     62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatDiv            0      0.00%     62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMisc            0      0.00%     62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatSqrt            0      0.00%     62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAdd            0      0.00%     62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAddAcc            0      0.00%     62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAlu          301      0.00%     62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCmp            0      0.00%     62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCvt          157      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMisc          349      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMult            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMultAcc            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMatMultAcc            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShift            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShiftAcc            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdDiv            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSqrt            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAdd            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAlu            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCmp            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCvt            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatDiv            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMisc            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMult            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMultAcc            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMatMultAcc            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatSqrt            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAdd            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAlu            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceCmp            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceAdd            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceCmp            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAes            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAesMix            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash2            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash2            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma2            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma3            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdPredAlu            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::Matrix            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MatrixMov            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MatrixOP            0      0.00%     62.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemRead     13450561     32.49%     94.94% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemWrite      2094056      5.06%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemRead          230      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemWrite          554      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IprAccess            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::InstPrefetch            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideLoad            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideStore            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideMaskLoad            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideMaskStore            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStridedLoad            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStridedStore            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdIndexedLoad            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdIndexedStore            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdWholeRegisterLoad            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdWholeRegisterStore            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedFaultOnlyFirstLoad            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStrideSegmentedLoad            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStrideSegmentedStore            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdExt            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatExt            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdConfig            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::total     41394800                       # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.issueRate         1.454932                       # Inst issue rate ((Count/Cycle))
board.processor.cores.core.fuBusy             1029955                       # FU busy when requested (Count)
board.processor.cores.core.fuBusyRate        0.024881                       # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.cores.core.intInstQueueReads    112205230                       # Number of integer instruction queue reads (Count)
board.processor.cores.core.intInstQueueWrites     42778987                       # Number of integer instruction queue writes (Count)
board.processor.cores.core.intInstQueueWakeupAccesses     41360372                       # Number of integer instruction queue wakeup accesses (Count)
board.processor.cores.core.fpInstQueueReads         3879                       # Number of floating instruction queue reads (Count)
board.processor.cores.core.fpInstQueueWrites         2526                       # Number of floating instruction queue writes (Count)
board.processor.cores.core.fpInstQueueWakeupAccesses         1855                       # Number of floating instruction queue wakeup accesses (Count)
board.processor.cores.core.vecInstQueueReads            0                       # Number of vector instruction queue reads (Count)
board.processor.cores.core.vecInstQueueWrites            0                       # Number of vector instruction queue writes (Count)
board.processor.cores.core.vecInstQueueWakeupAccesses            0                       # Number of vector instruction queue wakeup accesses (Count)
board.processor.cores.core.intAluAccesses     42421671                       # Number of integer alu accesses (Count)
board.processor.cores.core.fpAluAccesses         1974                       # Number of floating point alu accesses (Count)
board.processor.cores.core.vecAluAccesses            0                       # Number of vector alu accesses (Count)
board.processor.cores.core.numRecvResp       12369915                       # Number of received responses (Count)
board.processor.cores.core.numRecvRespBytes     61983859                       # Number of received response bytes (Byte)
board.processor.cores.core.recvRespAvgBW         2.18                       # Average bandwidth of received responses ((Byte/Cycle))
board.processor.cores.core.recvRespAvgSize         5.01                       # Average packet size per received response ((Byte/Count))
board.processor.cores.core.recvRespAvgRate         0.43                       # Average rate of received responses per cycle ((Count/Cycle))
board.processor.cores.core.recvRespAvgRetryRate         0.00                       # Average retry rate per received response ((Count/Count))
board.processor.cores.core.numSendRetryResp            0                       # Number of retry responses sent (Count)
board.processor.cores.core.numSquashedInsts        31260                       # Number of squashed instructions skipped in execute (Count)
board.processor.cores.core.numSwp                   0                       # Number of swp insts executed (Count)
board.processor.cores.core.timesIdled             438                       # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
board.processor.cores.core.idleCycles           62239                       # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
board.processor.cores.core.MemDepUnit__0.insertedLoads     13582908                       # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.insertedStores      2136016                       # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingLoads      7234052                       # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingStores      2070716                       # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__1.insertedLoads            0                       # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.insertedStores            0                       # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingLoads            0                       # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingStores            0                       # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__2.insertedLoads            0                       # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.insertedStores            0                       # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingLoads            0                       # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingStores            0                       # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__3.insertedLoads            0                       # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.insertedStores            0                       # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingLoads            0                       # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingStores            0                       # Number of conflicting stores. (Count)
board.processor.cores.core.branchPred.lookups_0::NoBranch            0      0.00%      0.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::Return          534      0.05%      0.05% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallDirect          585      0.05%      0.10% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallIndirect          202      0.02%      0.12% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectCond      1077202     98.81%     98.93% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectUncond        11229      1.03%     99.96% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectCond            0      0.00%     99.96% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectUncond          388      0.04%    100.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::total      1090140                       # Number of BP lookups (Count)
board.processor.cores.core.branchPred.squashes_0::NoBranch            0      0.00%      0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::Return          275      0.77%      0.77% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallDirect          419      1.17%      1.93% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallIndirect          105      0.29%      2.23% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectCond        34046     94.90%     97.12% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectUncond          730      2.03%     99.16% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectCond            0      0.00%     99.16% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectUncond          302      0.84%    100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::total        35877                       # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.corrected_0::NoBranch            0      0.00%      0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::Return            1      0.01%      0.01% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallDirect          158      1.40%      1.41% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallIndirect           61      0.54%      1.95% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectCond        10851     96.01%     97.96% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectUncond          139      1.23%     99.19% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectCond            0      0.00%     99.19% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectUncond           92      0.81%    100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::total        11302                       # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.earlyResteers_0::NoBranch            0                       # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::Return            0                       # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallDirect            0                       # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallIndirect            0                       # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectCond            0                       # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectUncond            0                       # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectCond            0                       # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectUncond            0                       # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::total            0                       # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.committed_0::NoBranch            0      0.00%      0.00% # Number of branches finally committed  (Count)
board.processor.cores.core.branchPred.committed_0::Return          259      0.02%      0.02% # Number of branches finally committed  (Count)
board.processor.cores.core.branchPred.committed_0::CallDirect          166      0.02%      0.04% # Number of branches finally committed  (Count)
board.processor.cores.core.branchPred.committed_0::CallIndirect           97      0.01%      0.05% # Number of branches finally committed  (Count)
board.processor.cores.core.branchPred.committed_0::DirectCond      1043154     98.95%     99.00% # Number of branches finally committed  (Count)
board.processor.cores.core.branchPred.committed_0::DirectUncond        10499      1.00%     99.99% # Number of branches finally committed  (Count)
board.processor.cores.core.branchPred.committed_0::IndirectCond            0      0.00%     99.99% # Number of branches finally committed  (Count)
board.processor.cores.core.branchPred.committed_0::IndirectUncond           86      0.01%    100.00% # Number of branches finally committed  (Count)
board.processor.cores.core.branchPred.committed_0::total      1054261                       # Number of branches finally committed  (Count)
board.processor.cores.core.branchPred.mispredicted_0::NoBranch            0      0.00%      0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::Return            0      0.00%      0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallDirect           67      0.61%      0.61% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallIndirect           54      0.49%      1.10% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectCond        10733     97.47%     98.57% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectUncond           81      0.74%     99.30% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectCond            0      0.00%     99.30% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectUncond           77      0.70%    100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::total        11012                       # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::NoBranch            0      0.00%      0.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::Return            0      0.00%      0.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::CallDirect            0      0.00%      0.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::CallIndirect            0      0.00%      0.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::DirectCond        10467    100.00%    100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::DirectUncond            0      0.00%    100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::IndirectCond            0      0.00%    100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::IndirectUncond            0      0.00%    100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::total        10467                       # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::NoBranch            0      0.00%      0.00% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::Return            0      0.00%      0.00% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::CallDirect           67     12.29%     12.29% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::CallIndirect           54      9.91%     22.20% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::DirectCond          266     48.81%     71.01% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::DirectUncond           81     14.86%     85.87% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::IndirectCond            0      0.00%     85.87% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::IndirectUncond           77     14.13%    100.00% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::total          545                       # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.targetProvider_0::NoTarget         5440      0.50%      0.50% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::BTB      1084067     99.44%     99.94% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::RAS          534      0.05%     99.99% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::Indirect           99      0.01%    100.00% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::total      1090140                       # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetWrong_0::NoBranch          934      8.27%      8.27% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::Return        10359     91.67%     99.94% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallDirect            1      0.01%     99.95% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallIndirect            6      0.05%    100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectCond            0      0.00%    100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectUncond            0      0.00%    100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectCond            0      0.00%    100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectUncond            0      0.00%    100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::total        11300                       # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.condPredicted      1077202                       # Number of conditional branches predicted (Count)
board.processor.cores.core.branchPred.condPredictedTaken      1073373                       # Number of conditional branches predicted as taken (Count)
board.processor.cores.core.branchPred.condIncorrect        11302                       # Number of conditional branches incorrect (Count)
board.processor.cores.core.branchPred.predTakenBTBMiss          418                       # Number of branches predicted taken but missed in BTB (Count)
board.processor.cores.core.branchPred.BTBLookups      1090140                       # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.BTBUpdates          788                       # Number of BTB updates (Count)
board.processor.cores.core.branchPred.BTBHits      1084915                       # Number of BTB hits (Count)
board.processor.cores.core.branchPred.BTBHitRatio     0.995207                       # BTB Hit Ratio (Ratio)
board.processor.cores.core.branchPred.BTBMispredicted          611                       # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.cores.core.branchPred.indirectLookups          590                       # Number of indirect predictor lookups. (Count)
board.processor.cores.core.branchPred.indirectHits           99                       # Number of indirect target hits. (Count)
board.processor.cores.core.branchPred.indirectMisses          491                       # Number of indirect misses. (Count)
board.processor.cores.core.branchPred.indirectMispredicted            0                       # Number of mispredicted indirect branches. (Count)
board.processor.cores.core.branchPred.btb.lookups::NoBranch            0      0.00%      0.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::Return          534      0.05%      0.05% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallDirect          585      0.05%      0.10% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallIndirect          202      0.02%      0.12% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectCond      1077202     98.81%     98.93% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectUncond        11229      1.03%     99.96% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectCond            0      0.00%     99.96% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectUncond          388      0.04%    100.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::total      1090140                       # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.misses::NoBranch            0      0.00%      0.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::Return          534     10.22%     10.22% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallDirect          216      4.13%     14.35% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallIndirect          202      3.87%     18.22% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectCond         3679     70.41%     88.63% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectUncond          206      3.94%     92.57% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectCond            0      0.00%     92.57% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectUncond          388      7.43%    100.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::total         5225                       # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.updates::NoBranch            0      0.00%      0.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::Return            0      0.00%      0.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallDirect          158     20.05%     20.05% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallIndirect            0      0.00%     20.05% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectCond          491     62.31%     82.36% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectUncond          139     17.64%    100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectCond            0      0.00%    100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectUncond            0      0.00%    100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::total          788                       # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.mispredict::NoBranch            0      0.00%      0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::Return            0      0.00%      0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallDirect          158     20.05%     20.05% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallIndirect            0      0.00%     20.05% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectCond          491     62.31%     82.36% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectUncond          139     17.64%    100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectCond            0      0.00%    100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectUncond            0      0.00%    100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::total          788                       # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.branchPred.indirectBranchPred.lookups          590                       # Number of lookups (Count)
board.processor.cores.core.branchPred.indirectBranchPred.hits           99                       # Number of hits of a tag (Count)
board.processor.cores.core.branchPred.indirectBranchPred.misses          491                       # Number of misses (Count)
board.processor.cores.core.branchPred.indirectBranchPred.targetRecords          153                       # Number of targets that where recorded/installed in the cache (Count)
board.processor.cores.core.branchPred.indirectBranchPred.indirectRecords          743                       # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.cores.core.branchPred.indirectBranchPred.speculativeOverflows            1                       # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.cores.core.branchPred.ras.pushes         1062                       # Number of times a PC was pushed onto the RAS (Count)
board.processor.cores.core.branchPred.ras.pops         1058                       # Number of times a PC was poped from the RAS (Count)
board.processor.cores.core.branchPred.ras.squashes          799                       # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.cores.core.branchPred.ras.used          259                       # Number of times the RAS is the provider (Count)
board.processor.cores.core.branchPred.ras.correct          259                       # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.cores.core.branchPred.ras.incorrect            0                       # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.cores.core.commit.commitSquashedInsts       841180                       # The number of squashed insts skipped by commit (Count)
board.processor.cores.core.commit.branchMispredicts        11062                       # The number of times a branch was mispredicted (Count)
board.processor.cores.core.commit.numCommittedDist::samples     28282690                       # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::mean     1.453054                       # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::stdev     2.048719                       # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::underflows            0      0.00%      0.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::0      9983089     35.30%     35.30% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::1     10092639     35.68%     70.98% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::2      4081227     14.43%     85.41% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::3      2011798      7.11%     92.53% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::4        10882      0.04%     92.56% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::5        10408      0.04%     92.60% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::6          669      0.00%     92.60% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::7        29606      0.10%     92.71% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::8      2062372      7.29%    100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::overflows            0      0.00%    100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::min_value            0                       # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::max_value            8                       # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::total     28282690                       # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.amos              0                       # Number of atomic instructions committed (Count)
board.processor.cores.core.commit.membars            0                       # Number of memory barriers committed (Count)
board.processor.cores.core.commit.functionCalls          263                       # Number of function calls committed. (Count)
board.processor.cores.core.commit.committedInstType_0::No_OpClass          341      0.00%      0.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntAlu     22647379     55.11%     55.11% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntMult      3040040      7.40%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntDiv           56      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatAdd          146      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCmp            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCvt            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMult            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMultAcc            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatDiv            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMisc            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatSqrt            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAdd            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAddAcc            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAlu          160      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCmp            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCvt           86      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMisc          270      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMult            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMultAcc            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMatMultAcc            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShift            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShiftAcc            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdDiv            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSqrt            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAdd            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAlu            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCmp            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCvt            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatDiv            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMisc            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMult            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMultAcc            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMatMultAcc            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatSqrt            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAdd            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAlu            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceCmp            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceAdd            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceCmp            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAes            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAesMix            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash2            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash2            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma2            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma3            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdPredAlu            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::Matrix            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MatrixMov            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MatrixOP            0      0.00%     62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemRead     13314606     32.40%     94.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemWrite      2092642      5.09%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemRead           88      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemWrite          473      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IprAccess            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideLoad            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideStore            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideMaskLoad            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideMaskStore            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStridedLoad            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStridedStore            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdIndexedLoad            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdIndexedStore            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdWholeRegisterLoad            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdWholeRegisterStore            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedFaultOnlyFirstLoad            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStrideSegmentedLoad            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStrideSegmentedStore            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdExt            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatExt            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdConfig            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::total     41096287                       # Class of committed instruction (Count)
board.processor.cores.core.commit.commitEligibleSamples      2062372                       # number cycles where commit BW limit reached (Cycle)
board.processor.cores.core.commitStats0.numInsts     26728147                       # Number of instructions committed (thread level) (Count)
board.processor.cores.core.commitStats0.numOps     41096287                       # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores.core.commitStats0.numInstsNotNOP     26728147                       # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores.core.commitStats0.numOpsNotNOP     41096287                       # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores.core.commitStats0.cpi     1.064472                       # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores.core.commitStats0.ipc     0.939433                       # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores.core.commitStats0.numMemRefs     15407809                       # Number of memory references committed (Count)
board.processor.cores.core.commitStats0.numFpInsts         1372                       # Number of float instructions (Count)
board.processor.cores.core.commitStats0.numIntInsts     41095237                       # Number of integer instructions (Count)
board.processor.cores.core.commitStats0.numLoadInsts     13314694                       # Number of load instructions (Count)
board.processor.cores.core.commitStats0.numStoreInsts      2093115                       # Number of store instructions (Count)
board.processor.cores.core.commitStats0.numVecInsts            0                       # Number of vector instructions (Count)
board.processor.cores.core.commitStats0.committedInstType::No_OpClass          341      0.00%      0.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntAlu     22647379     55.11%     55.11% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntMult      3040040      7.40%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntDiv           56      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatAdd          146      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCmp            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCvt            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMult            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMultAcc            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatDiv            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMisc            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatSqrt            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAdd            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAddAcc            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAlu          160      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCmp            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCvt           86      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMisc          270      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMult            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMultAcc            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMatMultAcc            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShift            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShiftAcc            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdDiv            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSqrt            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAdd            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAlu            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCmp            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCvt            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatDiv            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMisc            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMult            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMultAcc            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMatMultAcc            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatSqrt            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAdd            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAlu            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceCmp            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceAdd            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceCmp            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAes            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAesMix            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash2            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash2            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma2            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma3            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdPredAlu            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::Matrix            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixMov            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixOP            0      0.00%     62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemRead     13314606     32.40%     94.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemWrite      2092642      5.09%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemRead           88      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemWrite          473      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IprAccess            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::InstPrefetch            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideLoad            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideStore            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskStore            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedLoad            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedStore            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedLoad            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedStore            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterLoad            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterStore            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedFaultOnlyFirstLoad            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedLoad            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedStore            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdExt            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatExt            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdConfig            0      0.00%    100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::total     41096287                       # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedControl::IsControl      1054261                       # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsDirectControl      1053819                       # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsIndirectControl          442                       # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCondControl      1043154                       # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsUncondControl        11107                       # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCall          263                       # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsReturn          259                       # Class of control type instructions committed (Count)
board.processor.cores.core.decode.idleCycles      1078124                       # Number of cycles decode is idle (Cycle)
board.processor.cores.core.decode.blockedCycles     22038047                       # Number of cycles decode is blocked (Cycle)
board.processor.cores.core.decode.runCycles      2178776                       # Number of cycles decode is running (Cycle)
board.processor.cores.core.decode.unblockCycles      3083001                       # Number of cycles decode is unblocking (Cycle)
board.processor.cores.core.decode.squashCycles        11177                       # Number of cycles decode is squashing (Cycle)
board.processor.cores.core.decode.branchResolved      1074034                       # Number of times decode resolved a branch (Count)
board.processor.cores.core.decode.branchMispred          303                       # Number of times decode detected a branch misprediction (Count)
board.processor.cores.core.decode.decodedInsts     42036286                       # Number of instructions handled by decode (Count)
board.processor.cores.core.decode.squashedInsts         1450                       # Number of squashed instructions handled by decode (Count)
board.processor.cores.core.executeStats0.numInsts     41363540                       # Number of executed instructions (Count)
board.processor.cores.core.executeStats0.numNop            0                       # Number of nop insts executed (Count)
board.processor.cores.core.executeStats0.numBranches      1056274                       # Number of branches executed (Count)
board.processor.cores.core.executeStats0.numLoadInsts     13440278                       # Number of load instructions executed (Count)
board.processor.cores.core.executeStats0.numStoreInsts      2094439                       # Number of stores executed (Count)
board.processor.cores.core.executeStats0.instRate     1.453833                       # Inst execution rate ((Count/Cycle))
board.processor.cores.core.executeStats0.numCCRegReads      7284959                       # Number of times the CC registers were read (Count)
board.processor.cores.core.executeStats0.numCCRegWrites     17468285                       # Number of times the CC registers were written (Count)
board.processor.cores.core.executeStats0.numFpRegReads         2335                       # Number of times the floating registers were read (Count)
board.processor.cores.core.executeStats0.numFpRegWrites         1163                       # Number of times the floating registers were written (Count)
board.processor.cores.core.executeStats0.numIntRegReads     61774709                       # Number of times the integer registers were read (Count)
board.processor.cores.core.executeStats0.numIntRegWrites     37175851                       # Number of times the integer registers were written (Count)
board.processor.cores.core.executeStats0.numMemRefs     15534717                       # Number of memory refs (Count)
board.processor.cores.core.executeStats0.numMiscRegReads     17658713                       # Number of times the Misc registers were read (Count)
board.processor.cores.core.executeStats0.numVecAluAccesses            0                       # Number of vector alu accesses (Count)
board.processor.cores.core.executeStats0.numDiscardedOps            0                       # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores.core.fetch.predictedBranches      1084700                       # Number of branches that fetch has predicted taken (Count)
board.processor.cores.core.fetch.cycles      28345724                       # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.cores.core.fetch.squashCycles        22948                       # Number of cycles fetch has spent squashing (Cycle)
board.processor.cores.core.fetch.miscStallCycles           69                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs (Cycle)
board.processor.cores.core.fetch.pendingTrapStallCycles          403                       # Number of stall cycles due to pending traps (Cycle)
board.processor.cores.core.fetch.cacheLines      3209458                       # Number of cache lines fetched (Count)
board.processor.cores.core.fetch.icacheSquashes          457                       # Number of outstanding Icache misses that were squashed (Count)
board.processor.cores.core.fetch.nisnDist::samples     28389125                       # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::mean     1.492595                       # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::stdev     2.865127                       # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::underflows            0      0.00%      0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::0     20982241     73.91%     73.91% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::1        25682      0.09%     74.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::2      2044343      7.20%     81.20% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::3        11020      0.04%     81.24% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::4      1058292      3.73%     84.97% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::5         6522      0.02%     84.99% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::6        53546      0.19%     85.18% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::7        20857      0.07%     85.25% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::8      4186622     14.75%    100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::overflows            0      0.00%    100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::min_value            0                       # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::max_value            8                       # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::total     28389125                       # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetchStats0.numInsts     27553599                       # Number of instructions fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.numOps            0                       # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.fetchRate     0.968446                       # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores.core.fetchStats0.numBranches      1090140                       # Number of branches fetched (Count)
board.processor.cores.core.fetchStats0.branchRate     0.038316                       # Number of branch fetches per cycle (Ratio)
board.processor.cores.core.fetchStats0.icacheStallCycles        31455                       # ICache total stall cycles (Cycle)
board.processor.cores.core.fetchStats0.numFetchSuspends            0                       # Number of times Execute suspended instruction fetching (Count)
board.processor.cores.core.iew.idleCycles            0                       # Number of cycles IEW is idle (Cycle)
board.processor.cores.core.iew.squashCycles        11177                       # Number of cycles IEW is squashing (Cycle)
board.processor.cores.core.iew.blockCycles       908610                       # Number of cycles IEW is blocking (Cycle)
board.processor.cores.core.iew.unblockCycles          404                       # Number of cycles IEW is unblocking (Cycle)
board.processor.cores.core.iew.dispatchedInsts     41938862                       # Number of instructions dispatched to IQ (Count)
board.processor.cores.core.iew.dispSquashedInsts           73                       # Number of squashed instructions skipped by dispatch (Count)
board.processor.cores.core.iew.dispLoadInsts     13582908                       # Number of dispatched load instructions (Count)
board.processor.cores.core.iew.dispStoreInsts      2136016                       # Number of dispatched store instructions (Count)
board.processor.cores.core.iew.dispNonSpecInsts            3                       # Number of dispatched non-speculative instructions (Count)
board.processor.cores.core.iew.iqFullEvents           45                       # Number of times the IQ has become full, causing a stall (Count)
board.processor.cores.core.iew.lsqFullEvents          236                       # Number of times the LSQ has become full, causing a stall (Count)
board.processor.cores.core.iew.memOrderViolationEvents           87                       # Number of memory order violations (Count)
board.processor.cores.core.iew.predictedTakenIncorrect        10389                       # Number of branches that were predicted taken incorrectly (Count)
board.processor.cores.core.iew.predictedNotTakenIncorrect          836                       # Number of branches that were predicted not taken incorrectly (Count)
board.processor.cores.core.iew.branchMispredicts        11225                       # Number of branch mispredicts detected at execute (Count)
board.processor.cores.core.iew.instsToCommit     41363062                       # Cumulative count of insts sent to commit (Count)
board.processor.cores.core.iew.writebackCount     41362227                       # Cumulative count of insts written-back (Count)
board.processor.cores.core.iew.producerInst     33117588                       # Number of instructions producing a value (Count)
board.processor.cores.core.iew.consumerInst     49537523                       # Number of instructions consuming a value (Count)
board.processor.cores.core.iew.wbRate        1.453787                       # Insts written-back per cycle ((Count/Cycle))
board.processor.cores.core.iew.wbFanout      0.668535                       # Average fanout of values written-back ((Count/Count))
board.processor.cores.core.interrupts.clk_domain.clock         5328                       # Clock period in ticks (Tick)
board.processor.cores.core.lsq0.forwLoads      3163176                       # Number of loads that had data forwarded from stores (Count)
board.processor.cores.core.lsq0.squashedLoads       268214                       # Number of loads squashed (Count)
board.processor.cores.core.lsq0.ignoredResponses           84                       # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.cores.core.lsq0.memOrderViolation           87                       # Number of memory ordering violations (Count)
board.processor.cores.core.lsq0.squashedStores        42901                       # Number of stores squashed (Count)
board.processor.cores.core.lsq0.rescheduledLoads            0                       # Number of loads that were rescheduled (Count)
board.processor.cores.core.lsq0.blockedByCache            0                       # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.cores.core.lsq0.loadToUse::samples     13314694                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::mean     2.219359                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::stdev     1.219654                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::0-9     13251665     99.53%     99.53% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::10-19        62829      0.47%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::20-29           36      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::30-39            2      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::40-49            1      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::50-59            1      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::60-69            3      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::70-79            1      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::80-89            4      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::110-119            3      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::120-129            1      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::130-139            4      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::140-149            5      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::150-159            1      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::160-169           32      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::170-179           17      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::180-189            3      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::190-199            8      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::200-209           35      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::210-219            4      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::220-229            2      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::230-239            2      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::240-249           17      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::250-259            1      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::260-269            7      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::280-289            1      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::overflows            9      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::min_value            2                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::max_value         1152                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::total     13314694                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.addedLoadsAndStores     15718924                       # Number of loads and stores written to the Load Store Queue (Count)
board.processor.cores.core.mmu.dtb.rdAccesses     13440288                       # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrAccesses      2094439                       # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.dtb.rdMisses          355                       # TLB misses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrMisses           83                       # TLB misses on write requests (Count)
board.processor.cores.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.rdAccesses            0                       # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.itb.wrAccesses      3209532                       # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.itb.rdMisses            0                       # TLB misses on read requests (Count)
board.processor.cores.core.mmu.itb.wrMisses          130                       # TLB misses on write requests (Count)
board.processor.cores.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON   9474303879                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.rename.squashCycles        11177                       # Number of cycles rename is squashing (Cycle)
board.processor.cores.core.rename.idleCycles      2152334                       # Number of cycles rename is idle (Cycle)
board.processor.cores.core.rename.blockCycles      8936897                       # Number of cycles rename is blocking (Cycle)
board.processor.cores.core.rename.serializeStallCycles          611                       # count of cycles rename stalled for serializing inst (Cycle)
board.processor.cores.core.rename.runCycles      3226966                       # Number of cycles rename is running (Cycle)
board.processor.cores.core.rename.unblockCycles     14061140                       # Number of cycles rename is unblocking (Cycle)
board.processor.cores.core.rename.renamedInsts     42028379                       # Number of instructions processed by rename (Count)
board.processor.cores.core.rename.ROBFullEvents          143                       # Number of times rename has blocked due to ROB full (Count)
board.processor.cores.core.rename.IQFullEvents     12997580                       # Number of times rename has blocked due to IQ full (Count)
board.processor.cores.core.rename.LQFullEvents        46657                       # Number of times rename has blocked due to LQ full (Count)
board.processor.cores.core.rename.SQFullEvents         8288                       # Number of times rename has blocked due to SQ full (Count)
board.processor.cores.core.rename.renamedOperands     84918919                       # Number of destination operands rename has renamed (Count)
board.processor.cores.core.rename.lookups    144966038                       # Number of register rename lookups that rename has made (Count)
board.processor.cores.core.rename.intLookups     62890723                       # Number of integer rename lookups (Count)
board.processor.cores.core.rename.fpLookups         2438                       # Number of floating rename lookups (Count)
board.processor.cores.core.rename.committedMaps     83048018                       # Number of HB maps that are committed (Count)
board.processor.cores.core.rename.undoneMaps      1870892                       # Number of HB maps that are undone due to squashing (Count)
board.processor.cores.core.rename.serializing           25                       # count of serializing insts renamed (Count)
board.processor.cores.core.rename.tempSerializing           25                       # count of temporary serializing insts renamed (Count)
board.processor.cores.core.rename.skidInsts     29204297                       # count of insts added to the skid buffer (Count)
board.processor.cores.core.rename.intReturned     36904843                       # count of registers freed and written back to integer free list (Count)
board.processor.cores.core.rename.fpReturned          817                       # count of registers freed and written back to floating point free list (Count)
board.processor.cores.core.rob.reads         68157135                       # The number of ROB reads (Count)
board.processor.cores.core.rob.writes        83981405                       # The number of ROB writes (Count)
board.processor.cores.core.thread_0.numInsts     26728147                       # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps     41096287                       # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs            0                       # Number of Memory References (Count)
board.processor.cores.core.workload.numSyscalls           18                       # Number of system calls (Count)
board.workload.inst.arm                             0                       # number of arm instructions executed (Count)
board.workload.inst.quiesce                         0                       # number of quiesce instructions executed (Count)

---------- End Simulation Statistics   ----------