[board]
type=System
children=apicbridge bridge cache_hierarchy clk_domain dvfs_handler iobus memory pc processor workload
auto_unlink_shared_backstore=false
cache_line_size=64
eventq_index=0
exit_on_work_items=true
external_memory_ranges=
init_param=0
m5ops_base=4294901760
mem_mode=atomic_noncaching
mem_ranges=0:3221225472 3221225472:3222274048
memories=board.memory.mem_ctrl0.dram board.memory.mem_ctrl1.dram
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
readfile=with_perf/readfile_-0x5e0fb3f33dd1d877
redirect_paths=
shadow_rom_ranges=
shared_backstore=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
workload=board.workload
system_port=board.cache_hierarchy.membus.cpu_side_ports[1]
[board.apicbridge]
type=Bridge
children=power_state
clk_domain=board.clk_domain
delay=50000
eventq_index=0
power_model=
power_state=board.apicbridge.power_state
ranges=11529215046068469760:11529215046068477951
req_size=16
resp_size=16
cpu_side_port=board.iobus.mem_side_ports[0]
mem_side_port=board.cache_hierarchy.membus.cpu_side_ports[0]
[board.apicbridge.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.bridge]
type=Bridge
children=power_state
clk_domain=board.clk_domain
delay=50000
eventq_index=0
power_model=
power_state=board.bridge.power_state
ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
req_size=16
resp_size=16
cpu_side_port=board.cache_hierarchy.membus.mem_side_ports[0]
mem_side_port=board.iobus.cpu_side_ports[0]
[board.bridge.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.cache_hierarchy]
type=SubSystem
children=iocache l1dcaches0 l1dcaches1 l1icaches0 l1icaches1 membus
eventq_index=0
thermal_domain=Null
[board.cache_hierarchy.iocache]
type=Cache
children=power_state replacement_policy tags
addr_ranges=0:3221225472 3221225472:3222274048
assoc=8
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=50
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=20
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.iocache.power_state
prefetcher=Null
replace_expansions=true
replacement_policy=board.cache_hierarchy.iocache.replacement_policy
response_latency=50
sequential_access=false
size=1024
system=board
tag_latency=50
tags=board.cache_hierarchy.iocache.tags
tgts_per_mshr=12
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=false
cpu_side=board.iobus.mem_side_ports[15]
mem_side=board.cache_hierarchy.membus.cpu_side_ports[2]
[board.cache_hierarchy.iocache.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.cache_hierarchy.iocache.replacement_policy]
type=LRURP
eventq_index=0
[board.cache_hierarchy.iocache.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=8
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.iocache.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.iocache.tags.power_state
replacement_policy=board.cache_hierarchy.iocache.replacement_policy
sequential_access=false
size=1024
system=board
tag_latency=50
warmup_percentage=0
[board.cache_hierarchy.iocache.tags.indexing_policy]
type=TaggedSetAssociative
assoc=8
entry_size=64
eventq_index=0
size=1024
[board.cache_hierarchy.iocache.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.cache_hierarchy.l1dcaches0]
type=Cache
children=power_state prefetcher replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=16
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1dcaches0.power_state
prefetcher=board.cache_hierarchy.l1dcaches0.prefetcher
replace_expansions=true
replacement_policy=board.cache_hierarchy.l1dcaches0.replacement_policy
response_latency=1
sequential_access=false
size=32768
system=board
tag_latency=1
tags=board.cache_hierarchy.l1dcaches0.tags
tgts_per_mshr=20
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=false
cpu_side=board.processor.start0.core.dcache_port
mem_side=board.cache_hierarchy.membus.cpu_side_ports[4]
[board.cache_hierarchy.l1dcaches0.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.cache_hierarchy.l1dcaches0.prefetcher]
type=StridePrefetcher
children=power_state table_indexing_policy table_replacement_policy
block_size=64
cache_snoop=false
clk_domain=board.clk_domain
confidence_counter_bits=3
confidence_threshold=50
degree=4
distance=0
eventq_index=0
initial_confidence=4
latency=1
max_prefetch_requests_with_pending_translation=32
on_data=true
on_inst=false
on_miss=false
on_read=true
on_write=true
page_bytes=4096
power_model=
power_state=board.cache_hierarchy.l1dcaches0.prefetcher.power_state
prefetch_on_access=false
prefetch_on_pf_hit=true
queue_filter=true
queue_size=32
queue_squash=true
sys=board
table_assoc=4
table_entries=64
table_indexing_policy=board.cache_hierarchy.l1dcaches0.prefetcher.table_indexing_policy
table_replacement_policy=board.cache_hierarchy.l1dcaches0.prefetcher.table_replacement_policy
tag_prefetch=true
throttle_control_percentage=0
use_cache_line_address=true
use_requestor_id=true
use_virtual_addresses=false
[board.cache_hierarchy.l1dcaches0.prefetcher.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.cache_hierarchy.l1dcaches0.prefetcher.table_indexing_policy]
type=StridePrefetcherHashedSetAssociative
assoc=4
entry_size=1
eventq_index=0
size=64
[board.cache_hierarchy.l1dcaches0.prefetcher.table_replacement_policy]
type=RandomRP
eventq_index=0
[board.cache_hierarchy.l1dcaches0.replacement_policy]
type=LRURP
eventq_index=0
[board.cache_hierarchy.l1dcaches0.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=8
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.l1dcaches0.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1dcaches0.tags.power_state
replacement_policy=board.cache_hierarchy.l1dcaches0.replacement_policy
sequential_access=false
size=32768
system=board
tag_latency=1
warmup_percentage=0
[board.cache_hierarchy.l1dcaches0.tags.indexing_policy]
type=TaggedSetAssociative
assoc=8
entry_size=64
eventq_index=0
size=32768
[board.cache_hierarchy.l1dcaches0.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.cache_hierarchy.l1dcaches1]
type=Cache
children=power_state prefetcher replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=16
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1dcaches1.power_state
prefetcher=board.cache_hierarchy.l1dcaches1.prefetcher
replace_expansions=true
replacement_policy=board.cache_hierarchy.l1dcaches1.replacement_policy
response_latency=1
sequential_access=false
size=32768
system=board
tag_latency=1
tags=board.cache_hierarchy.l1dcaches1.tags
tgts_per_mshr=20
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=false
cpu_side=board.processor.start1.core.dcache_port
mem_side=board.cache_hierarchy.membus.cpu_side_ports[9]
[board.cache_hierarchy.l1dcaches1.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.cache_hierarchy.l1dcaches1.prefetcher]
type=StridePrefetcher
children=power_state table_indexing_policy table_replacement_policy
block_size=64
cache_snoop=false
clk_domain=board.clk_domain
confidence_counter_bits=3
confidence_threshold=50
degree=4
distance=0
eventq_index=0
initial_confidence=4
latency=1
max_prefetch_requests_with_pending_translation=32
on_data=true
on_inst=false
on_miss=false
on_read=true
on_write=true
page_bytes=4096
power_model=
power_state=board.cache_hierarchy.l1dcaches1.prefetcher.power_state
prefetch_on_access=false
prefetch_on_pf_hit=true
queue_filter=true
queue_size=32
queue_squash=true
sys=board
table_assoc=4
table_entries=64
table_indexing_policy=board.cache_hierarchy.l1dcaches1.prefetcher.table_indexing_policy
table_replacement_policy=board.cache_hierarchy.l1dcaches1.prefetcher.table_replacement_policy
tag_prefetch=true
throttle_control_percentage=0
use_cache_line_address=true
use_requestor_id=true
use_virtual_addresses=false
[board.cache_hierarchy.l1dcaches1.prefetcher.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.cache_hierarchy.l1dcaches1.prefetcher.table_indexing_policy]
type=StridePrefetcherHashedSetAssociative
assoc=4
entry_size=1
eventq_index=0
size=64
[board.cache_hierarchy.l1dcaches1.prefetcher.table_replacement_policy]
type=RandomRP
eventq_index=0
[board.cache_hierarchy.l1dcaches1.replacement_policy]
type=LRURP
eventq_index=0
[board.cache_hierarchy.l1dcaches1.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=8
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.l1dcaches1.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1dcaches1.tags.power_state
replacement_policy=board.cache_hierarchy.l1dcaches1.replacement_policy
sequential_access=false
size=32768
system=board
tag_latency=1
warmup_percentage=0
[board.cache_hierarchy.l1dcaches1.tags.indexing_policy]
type=TaggedSetAssociative
assoc=8
entry_size=64
eventq_index=0
size=32768
[board.cache_hierarchy.l1dcaches1.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.cache_hierarchy.l1icaches0]
type=Cache
children=power_state prefetcher replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=16
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1icaches0.power_state
prefetcher=board.cache_hierarchy.l1icaches0.prefetcher
replace_expansions=true
replacement_policy=board.cache_hierarchy.l1icaches0.replacement_policy
response_latency=1
sequential_access=false
size=32768
system=board
tag_latency=1
tags=board.cache_hierarchy.l1icaches0.tags
tgts_per_mshr=20
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=true
cpu_side=board.processor.start0.core.icache_port
mem_side=board.cache_hierarchy.membus.cpu_side_ports[3]
[board.cache_hierarchy.l1icaches0.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.cache_hierarchy.l1icaches0.prefetcher]
type=StridePrefetcher
children=power_state table_indexing_policy table_replacement_policy
block_size=64
cache_snoop=false
clk_domain=board.clk_domain
confidence_counter_bits=3
confidence_threshold=50
degree=4
distance=0
eventq_index=0
initial_confidence=4
latency=1
max_prefetch_requests_with_pending_translation=32
on_data=true
on_inst=false
on_miss=false
on_read=true
on_write=true
page_bytes=4096
power_model=
power_state=board.cache_hierarchy.l1icaches0.prefetcher.power_state
prefetch_on_access=false
prefetch_on_pf_hit=true
queue_filter=true
queue_size=32
queue_squash=true
sys=board
table_assoc=4
table_entries=64
table_indexing_policy=board.cache_hierarchy.l1icaches0.prefetcher.table_indexing_policy
table_replacement_policy=board.cache_hierarchy.l1icaches0.prefetcher.table_replacement_policy
tag_prefetch=true
throttle_control_percentage=0
use_cache_line_address=true
use_requestor_id=true
use_virtual_addresses=false
[board.cache_hierarchy.l1icaches0.prefetcher.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.cache_hierarchy.l1icaches0.prefetcher.table_indexing_policy]
type=StridePrefetcherHashedSetAssociative
assoc=4
entry_size=1
eventq_index=0
size=64
[board.cache_hierarchy.l1icaches0.prefetcher.table_replacement_policy]
type=RandomRP
eventq_index=0
[board.cache_hierarchy.l1icaches0.replacement_policy]
type=LRURP
eventq_index=0
[board.cache_hierarchy.l1icaches0.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=8
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.l1icaches0.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1icaches0.tags.power_state
replacement_policy=board.cache_hierarchy.l1icaches0.replacement_policy
sequential_access=false
size=32768
system=board
tag_latency=1
warmup_percentage=0
[board.cache_hierarchy.l1icaches0.tags.indexing_policy]
type=TaggedSetAssociative
assoc=8
entry_size=64
eventq_index=0
size=32768
[board.cache_hierarchy.l1icaches0.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.cache_hierarchy.l1icaches1]
type=Cache
children=power_state prefetcher replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=16
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1icaches1.power_state
prefetcher=board.cache_hierarchy.l1icaches1.prefetcher
replace_expansions=true
replacement_policy=board.cache_hierarchy.l1icaches1.replacement_policy
response_latency=1
sequential_access=false
size=32768
system=board
tag_latency=1
tags=board.cache_hierarchy.l1icaches1.tags
tgts_per_mshr=20
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=true
cpu_side=board.processor.start1.core.icache_port
mem_side=board.cache_hierarchy.membus.cpu_side_ports[8]
[board.cache_hierarchy.l1icaches1.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.cache_hierarchy.l1icaches1.prefetcher]
type=StridePrefetcher
children=power_state table_indexing_policy table_replacement_policy
block_size=64
cache_snoop=false
clk_domain=board.clk_domain
confidence_counter_bits=3
confidence_threshold=50
degree=4
distance=0
eventq_index=0
initial_confidence=4
latency=1
max_prefetch_requests_with_pending_translation=32
on_data=true
on_inst=false
on_miss=false
on_read=true
on_write=true
page_bytes=4096
power_model=
power_state=board.cache_hierarchy.l1icaches1.prefetcher.power_state
prefetch_on_access=false
prefetch_on_pf_hit=true
queue_filter=true
queue_size=32
queue_squash=true
sys=board
table_assoc=4
table_entries=64
table_indexing_policy=board.cache_hierarchy.l1icaches1.prefetcher.table_indexing_policy
table_replacement_policy=board.cache_hierarchy.l1icaches1.prefetcher.table_replacement_policy
tag_prefetch=true
throttle_control_percentage=0
use_cache_line_address=true
use_requestor_id=true
use_virtual_addresses=false
[board.cache_hierarchy.l1icaches1.prefetcher.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.cache_hierarchy.l1icaches1.prefetcher.table_indexing_policy]
type=StridePrefetcherHashedSetAssociative
assoc=4
entry_size=1
eventq_index=0
size=64
[board.cache_hierarchy.l1icaches1.prefetcher.table_replacement_policy]
type=RandomRP
eventq_index=0
[board.cache_hierarchy.l1icaches1.replacement_policy]
type=LRURP
eventq_index=0
[board.cache_hierarchy.l1icaches1.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=8
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.l1icaches1.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1icaches1.tags.power_state
replacement_policy=board.cache_hierarchy.l1icaches1.replacement_policy
sequential_access=false
size=32768
system=board
tag_latency=1
warmup_percentage=0
[board.cache_hierarchy.l1icaches1.tags.indexing_policy]
type=TaggedSetAssociative
assoc=8
entry_size=64
eventq_index=0
size=32768
[board.cache_hierarchy.l1icaches1.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.cache_hierarchy.membus]
type=CoherentXBar
children=badaddr_responder power_state snoop_filter
clk_domain=board.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
header_latency=1
max_outstanding_snoops=512
max_routing_table_size=512
point_of_coherency=true
point_of_unification=true
power_model=
power_state=board.cache_hierarchy.membus.power_state
response_latency=2
snoop_filter=board.cache_hierarchy.membus.snoop_filter
snoop_response_latency=4
system=board
use_default_range=false
width=64
cpu_side_ports=board.apicbridge.mem_side_port board.system_port board.cache_hierarchy.iocache.mem_side board.cache_hierarchy.l1icaches0.mem_side board.cache_hierarchy.l1dcaches0.mem_side board.processor.start0.core.mmu.itb.walker.port board.processor.start0.core.mmu.dtb.walker.port board.processor.start0.core.interrupts.int_requestor board.cache_hierarchy.l1icaches1.mem_side board.cache_hierarchy.l1dcaches1.mem_side board.processor.start1.core.mmu.itb.walker.port board.processor.start1.core.mmu.dtb.walker.port board.processor.start1.core.interrupts.int_requestor
default=board.cache_hierarchy.membus.badaddr_responder.pio
mem_side_ports=board.bridge.cpu_side_port board.memory.mem_ctrl0.port board.memory.mem_ctrl1.port board.processor.start0.core.interrupts.pio board.processor.start0.core.interrupts.int_responder board.processor.start1.core.interrupts.pio board.processor.start1.core.interrupts.int_responder
[board.cache_hierarchy.membus.badaddr_responder]
type=IsaFake
children=power_state
clk_domain=board.clk_domain
eventq_index=0
fake_mem=false
pio_addr=0
pio_latency=100000
pio_size=8
power_model=
power_state=board.cache_hierarchy.membus.badaddr_responder.power_state
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=board
update_data=false
warn_access=
pio=board.cache_hierarchy.membus.default
[board.cache_hierarchy.membus.badaddr_responder.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.cache_hierarchy.membus.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.cache_hierarchy.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=board
[board.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=333
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=board.clk_domain.voltage_domain
[board.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0
[board.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=board.clk_domain
transition_latency=100000000
[board.iobus]
type=NoncoherentXBar
children=power_state
clk_domain=board.clk_domain
eventq_index=0
forward_latency=1
frontend_latency=2
header_latency=1
power_model=
power_state=board.iobus.power_state
response_latency=2
use_default_range=false
width=16
cpu_side_ports=board.bridge.mem_side_port board.pc.south_bridge.io_apic.int_requestor board.pc.pci_host.down_to_up.mem_side_port
default=board.pc.default_bus.cpu_side_ports[0]
mem_side_ports=board.apicbridge.cpu_side_port board.pc.south_bridge.cmos.pio board.pc.south_bridge.dma1.pio board.pc.south_bridge.keyboard.pio board.pc.south_bridge.pic1.pio board.pc.south_bridge.pic2.pio board.pc.south_bridge.pit.pio board.pc.south_bridge.speaker.pio board.pc.south_bridge.io_apic.pio board.pc.com_1.pio board.pc.fake_com_2.pio board.pc.fake_com_3.pio board.pc.fake_com_4.pio board.pc.fake_floppy.pio board.pc.pci_host.up_to_down.cpu_side_port board.cache_hierarchy.iocache.cpu_side
[board.iobus.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.memory]
type=SubSystem
children=mem_ctrl0 mem_ctrl1
eventq_index=0
thermal_domain=Null
[board.memory.mem_ctrl0]
type=MemCtrl
children=dram power_state
clk_domain=board.clk_domain
command_window=10000
disable_sanity_check=false
dram=board.memory.mem_ctrl0.dram
eventq_index=0
mem_sched_policy=frfcfs
min_reads_per_switch=16
min_writes_per_switch=16
power_model=
power_state=board.memory.mem_ctrl0.power_state
qos_policy=Null
qos_priorities=1
qos_priority_escalation=false
qos_q_policy=fifo
qos_requestors=
qos_syncro_scheduler=false
qos_turnaround_policy=Null
static_backend_latency=10000
static_frontend_latency=10000
system=board
write_high_thresh_perc=85
write_low_thresh_perc=50
port=board.cache_hierarchy.membus.mem_side_ports[1]
[board.memory.mem_ctrl0.dram]
type=DRAMInterface
children=power_state
IDD0=0.048
IDD02=0.003
IDD2N=0.034
IDD2N2=0.0
IDD2P0=0.0
IDD2P02=0.0
IDD2P1=0.025
IDD2P12=0.0
IDD3N=0.043000000000000003
IDD3N2=0.003
IDD3P0=0.0
IDD3P02=0.0
IDD3P1=0.037
IDD3P12=0.0
IDD4R=0.135
IDD4R2=0.0
IDD4W=0.123
IDD4W2=0.0
IDD5=0.25
IDD52=0.0
IDD6=0.03
IDD62=0.0
VDD=1.2
VDD2=2.5
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=4
banks_per_rank=16
beats_per_clock=2
burst_length=8
clk_domain=board.clk_domain
collect_stats=true
conf_table_reported=true
data_clock_sync=false
device_bus_width=8
device_rowbuffer_size=1024
device_size=1073741824
devices_per_rank=8
dll=true
enable_dram_powerdown=false
eventq_index=0
image_file=
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
null=false
page_policy=open_adaptive
power_model=
power_state=board.memory.mem_ctrl0.dram.power_state
range=0:3221225472:0:64
ranks_per_channel=2
read_buffer_size=64
tAAD=833
tBURST=3332
tBURST_MAX=3332
tBURST_MIN=3332
tCCD_L=5000
tCCD_L_WR=5000
tCK=833
tCL=14160
tCS=1666
tCWL=14160
tPPD=0
tRAS=32000
tRCD=14160
tRCD_WR=14160
tREFI=7800000
tRFC=350000
tRP=14160
tRRD=3332
tRRD_L=4900
tRTP=7500
tRTW=1666
tWR=15000
tWTR=5000
tWTR_L=5000
tXAW=21000
tXP=6000
tXPDLL=0
tXS=340000
tXSDLL=0
two_cycle_activate=false
write_buffer_size=128
writeable=true
[board.memory.mem_ctrl0.dram.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.memory.mem_ctrl0.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.memory.mem_ctrl1]
type=MemCtrl
children=dram power_state
clk_domain=board.clk_domain
command_window=10000
disable_sanity_check=false
dram=board.memory.mem_ctrl1.dram
eventq_index=0
mem_sched_policy=frfcfs
min_reads_per_switch=16
min_writes_per_switch=16
power_model=
power_state=board.memory.mem_ctrl1.power_state
qos_policy=Null
qos_priorities=1
qos_priority_escalation=false
qos_q_policy=fifo
qos_requestors=
qos_syncro_scheduler=false
qos_turnaround_policy=Null
static_backend_latency=10000
static_frontend_latency=10000
system=board
write_high_thresh_perc=85
write_low_thresh_perc=50
port=board.cache_hierarchy.membus.mem_side_ports[2]
[board.memory.mem_ctrl1.dram]
type=DRAMInterface
children=power_state
IDD0=0.048
IDD02=0.003
IDD2N=0.034
IDD2N2=0.0
IDD2P0=0.0
IDD2P02=0.0
IDD2P1=0.025
IDD2P12=0.0
IDD3N=0.043000000000000003
IDD3N2=0.003
IDD3P0=0.0
IDD3P02=0.0
IDD3P1=0.037
IDD3P12=0.0
IDD4R=0.135
IDD4R2=0.0
IDD4W=0.123
IDD4W2=0.0
IDD5=0.25
IDD52=0.0
IDD6=0.03
IDD62=0.0
VDD=1.2
VDD2=2.5
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=4
banks_per_rank=16
beats_per_clock=2
burst_length=8
clk_domain=board.clk_domain
collect_stats=true
conf_table_reported=true
data_clock_sync=false
device_bus_width=8
device_rowbuffer_size=1024
device_size=1073741824
devices_per_rank=8
dll=true
enable_dram_powerdown=false
eventq_index=0
image_file=
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
null=false
page_policy=open_adaptive
power_model=
power_state=board.memory.mem_ctrl1.dram.power_state
range=0:3221225472:1:64
ranks_per_channel=2
read_buffer_size=64
tAAD=833
tBURST=3332
tBURST_MAX=3332
tBURST_MIN=3332
tCCD_L=5000
tCCD_L_WR=5000
tCK=833
tCL=14160
tCS=1666
tCWL=14160
tPPD=0
tRAS=32000
tRCD=14160
tRCD_WR=14160
tREFI=7800000
tRFC=350000
tRP=14160
tRRD=3332
tRRD_L=4900
tRTP=7500
tRTW=1666
tWR=15000
tWTR=5000
tWTR_L=5000
tXAW=21000
tXP=6000
tXPDLL=0
tXS=340000
tXSDLL=0
two_cycle_activate=false
write_buffer_size=128
writeable=true
[board.memory.mem_ctrl1.dram.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.memory.mem_ctrl1.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc]
type=Pc
children=bad_addr com_1 default_bus empty_isa fake_com_2 fake_com_3 fake_com_4 fake_floppy pci_bus pci_host south_bridge
eventq_index=0
south_bridge=board.pc.south_bridge
system=board
[board.pc.bad_addr]
type=IsaFake
children=power_state
clk_domain=board.clk_domain
eventq_index=0
fake_mem=false
pio_addr=0
pio_latency=100000
pio_size=8
power_model=
power_state=board.pc.bad_addr.power_state
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=board
update_data=false
warn_access=
pio=board.pc.default_bus.default
[board.pc.bad_addr.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.com_1]
type=Uart8250
children=device power_state
clk_domain=board.clk_domain
device=board.pc.com_1.device
eventq_index=0
pio_addr=9223372036854776824
pio_latency=100000
pio_size=8
platform=board.pc
power_model=
power_state=board.pc.com_1.power_state
system=board
pio=board.iobus.mem_side_ports[9]
[board.pc.com_1.device]
type=Terminal
eventq_index=0
number=0
outfile=file
port=#3456
[board.pc.com_1.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.default_bus]
type=NoncoherentXBar
children=power_state
clk_domain=board.clk_domain
eventq_index=0
forward_latency=1
frontend_latency=2
header_latency=1
power_model=
power_state=board.pc.default_bus.power_state
response_latency=2
use_default_range=false
width=16
cpu_side_ports=board.iobus.default
default=board.pc.bad_addr.pio
mem_side_ports=board.pc.empty_isa.pio
[board.pc.default_bus.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.empty_isa]
type=IsaFake
children=power_state
clk_domain=board.clk_domain
eventq_index=0
fake_mem=false
pio_addr=9223372036854775808
pio_latency=100000
pio_size=65536
power_model=
power_state=board.pc.empty_isa.power_state
ret_bad_addr=false
ret_data16=0
ret_data32=0
ret_data64=0
ret_data8=0
system=board
update_data=false
warn_access=
pio=board.pc.default_bus.mem_side_ports[0]
[board.pc.empty_isa.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.fake_com_2]
type=IsaFake
children=power_state
clk_domain=board.clk_domain
eventq_index=0
fake_mem=false
pio_addr=9223372036854776568
pio_latency=100000
pio_size=8
power_model=
power_state=board.pc.fake_com_2.power_state
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=board
update_data=false
warn_access=
pio=board.iobus.mem_side_ports[10]
[board.pc.fake_com_2.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.fake_com_3]
type=IsaFake
children=power_state
clk_domain=board.clk_domain
eventq_index=0
fake_mem=false
pio_addr=9223372036854776808
pio_latency=100000
pio_size=8
power_model=
power_state=board.pc.fake_com_3.power_state
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=board
update_data=false
warn_access=
pio=board.iobus.mem_side_ports[11]
[board.pc.fake_com_3.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.fake_com_4]
type=IsaFake
children=power_state
clk_domain=board.clk_domain
eventq_index=0
fake_mem=false
pio_addr=9223372036854776552
pio_latency=100000
pio_size=8
power_model=
power_state=board.pc.fake_com_4.power_state
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=board
update_data=false
warn_access=
pio=board.iobus.mem_side_ports[12]
[board.pc.fake_com_4.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.fake_floppy]
type=IsaFake
children=power_state
clk_domain=board.clk_domain
eventq_index=0
fake_mem=false
pio_addr=9223372036854776818
pio_latency=100000
pio_size=2
power_model=
power_state=board.pc.fake_floppy.power_state
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=board
update_data=false
warn_access=
pio=board.iobus.mem_side_ports[13]
[board.pc.fake_floppy.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.pci_bus]
type=PciBus
children=power_state
clk_domain=board.clk_domain
eventq_index=0
forward_latency=0
frontend_latency=0
header_latency=1
power_model=
power_state=board.pc.pci_bus.power_state
response_latency=0
use_default_range=false
width=16
config_error_port=board.pc.pci_host.config_error.pio
cpu_side_ports=board.pc.south_bridge.ide.dma board.pc.pci_host.up_to_down.mem_side_port
default=board.pc.pci_host.down_to_up.cpu_side_port
mem_side_ports=board.pc.south_bridge.ide.pio
[board.pc.pci_bus.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.pci_host]
type=GenericPciHost
children=config_error down_to_up power_state up_to_down
clk_domain=board.clk_domain
conf_base=13835058055282163712
conf_device_bits=8
conf_size=16777216
config_error=board.pc.pci_host.config_error
down_to_up=board.pc.pci_host.down_to_up
eventq_index=0
pci_dma_base=0
pci_mem_base=0
pci_pio_base=9223372036854775808
platform=board.pc
power_model=
power_state=board.pc.pci_host.power_state
up_to_down=board.pc.pci_host.up_to_down
[board.pc.pci_host.config_error]
type=PciConfigError
children=power_state
clk_domain=board.clk_domain
eventq_index=0
fake_mem=false
pio_addr=0
pio_latency=100000
pio_size=0
power_model=
power_state=board.pc.pci_host.config_error.power_state
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=board
update_data=false
warn_access=
pio=board.pc.pci_bus.config_error_port
[board.pc.pci_host.config_error.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.pci_host.down_to_up]
type=Bridge
children=power_state
clk_domain=board.clk_domain
delay=0
eventq_index=0
power_model=
power_state=board.pc.pci_host.down_to_up.power_state
ranges=0:18446744073709551615
req_size=16
resp_size=16
cpu_side_port=board.pc.pci_bus.default
mem_side_port=board.iobus.cpu_side_ports[2]
[board.pc.pci_host.down_to_up.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.pci_host.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.pci_host.up_to_down]
type=PciUpDownBridge
children=power_state
clk_domain=board.clk_domain
delay=0
eventq_index=0
power_model=
power_state=board.pc.pci_host.up_to_down.power_state
req_size=16
resp_size=16
cpu_side_port=board.iobus.mem_side_ports[14]
mem_side_port=board.pc.pci_bus.cpu_side_ports[1]
[board.pc.pci_host.up_to_down.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.south_bridge]
type=SouthBridge
children=cmos dma1 ide io_apic keyboard pic1 pic2 pit speaker
cmos=board.pc.south_bridge.cmos
dma1=board.pc.south_bridge.dma1
eventq_index=0
io_apic=board.pc.south_bridge.io_apic
keyboard=board.pc.south_bridge.keyboard
pic1=board.pc.south_bridge.pic1
pic2=board.pc.south_bridge.pic2
pit=board.pc.south_bridge.pit
speaker=board.pc.south_bridge.speaker
[board.pc.south_bridge.cmos]
type=Cmos
children=power_state
clk_domain=board.clk_domain
eventq_index=0
pio_addr=9223372036854775920
pio_latency=100000
power_model=
power_state=board.pc.south_bridge.cmos.power_state
system=board
time=Sun Jan 1 00:00:00 2012
int_pin=board.pc.south_bridge.pic2.inputs[0]
pio=board.iobus.mem_side_ports[1]
[board.pc.south_bridge.cmos.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.south_bridge.dma1]
type=I8237
children=power_state
clk_domain=board.clk_domain
eventq_index=0
pio_addr=9223372036854775808
pio_latency=100000
power_model=
power_state=board.pc.south_bridge.dma1.power_state
system=board
pio=board.iobus.mem_side_ports[2]
[board.pc.south_bridge.dma1.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.south_bridge.ide]
type=X86IdeController
children=BAR0 BAR1 BAR2 BAR3 BAR4 BAR5 disks power_state
BAR0=board.pc.south_bridge.ide.BAR0
BAR1=board.pc.south_bridge.ide.BAR1
BAR2=board.pc.south_bridge.ide.BAR2
BAR3=board.pc.south_bridge.ide.BAR3
BAR4=board.pc.south_bridge.ide.BAR4
BAR5=board.pc.south_bridge.ide.BAR5
BIST=0
CacheLineSize=0
CapabilityPtr=0
CardbusCIS=0
ClassCode=1
Command=0
DeviceID=28945
ExpansionROM=0
HeaderType=0
InterruptLine=255
InterruptPin=1
LatencyTimer=0
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
MSICAPMsgAddr=0
MSICAPMsgCtrl=0
MSICAPMsgData=0
MSICAPMsgUpperAddr=0
MSICAPNextCapability=0
MSICAPPendingBits=0
MSIXCAPBaseOffset=0
MSIXCAPCapId=0
MSIXCAPNextCapability=0
MSIXMsgCtrl=0
MSIXPbaOffset=0
MSIXTableOffset=0
MaximumLatency=0
MinimumGrant=0
PMCAPBaseOffset=0
PMCAPCapId=0
PMCAPCapabilities=0
PMCAPCtrlStatus=0
PMCAPNextCapability=0
PXCAPBaseOffset=0
PXCAPCapId=0
PXCAPCapabilities=0
PXCAPDevCap2=0
PXCAPDevCapabilities=0
PXCAPDevCtrl=0
PXCAPDevCtrl2=0
PXCAPDevStatus=0
PXCAPDevStatus2=0
PXCAPLinkCap=0
PXCAPLinkCap2=0
PXCAPLinkCtrl=0
PXCAPLinkCtrl2=0
PXCAPLinkStatus=0
PXCAPLinkStatus2=0
PXCAPNextCapability=0
PXCAPRootCap=0
PXCAPRootCtrl=0
PXCAPRootStatus=0
PXCAPSlotCap=0
PXCAPSlotCap2=0
PXCAPSlotCtrl=0
PXCAPSlotCtrl2=0
PXCAPSlotStatus=0
PXCAPSlotStatus2=0
ProgIF=128
Revision=0
Status=640
SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
clk_domain=board.clk_domain
config_latency=20000
ctrl_offset=0
disks=board.pc.south_bridge.ide.disks
eventq_index=0
io_shift=0
pci_dev=4
pci_func=0
pio_latency=30000
power_model=
power_state=board.pc.south_bridge.ide.power_state
sid=NullOpt
ssid=NullOpt
system=board
upstream=board.pc.pci_host
dma=board.pc.pci_bus.cpu_side_ports[0]
int_primary=board.pc.south_bridge.pic2.inputs[6] board.pc.south_bridge.io_apic.inputs[14]
int_secondary=board.pc.south_bridge.pic2.inputs[7] board.pc.south_bridge.io_apic.inputs[15]
pio=board.pc.pci_bus.mem_side_ports[0]
[board.pc.south_bridge.ide.BAR0]
type=PciLegacyIoBar
addr=496
eventq_index=0
size=8
[board.pc.south_bridge.ide.BAR1]
type=PciLegacyIoBar
addr=1012
eventq_index=0
size=3
[board.pc.south_bridge.ide.BAR2]
type=PciLegacyIoBar
addr=368
eventq_index=0
size=8
[board.pc.south_bridge.ide.BAR3]
type=PciLegacyIoBar
addr=884
eventq_index=0
size=3
[board.pc.south_bridge.ide.BAR4]
type=PciIoBar
eventq_index=0
size=16
[board.pc.south_bridge.ide.BAR5]
type=PciBarNone
eventq_index=0
[board.pc.south_bridge.ide.disks]
type=IdeDisk
children=image
delay=1000000
driveID=device0
eventq_index=0
image=board.pc.south_bridge.ide.disks.image
[board.pc.south_bridge.ide.disks.image]
type=CowDiskImage
children=child
child=board.pc.south_bridge.ide.disks.image.child
eventq_index=0
image_file=
read_only=false
table_size=65536
[board.pc.south_bridge.ide.disks.image.child]
type=RawDiskImage
eventq_index=0
image_file=/home/namiel/.cache/gem5/x86-ubuntu-24.04-npb-img-5.0.0
read_only=true
[board.pc.south_bridge.ide.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.south_bridge.io_apic]
type=I82094AA
children=power_state
apic_id=2
clk_domain=board.clk_domain
eventq_index=0
int_latency=1000
pio_addr=4273995776
pio_latency=100000
power_model=
power_state=board.pc.south_bridge.io_apic.power_state
system=board
inputs=board.pc.south_bridge.pic1.output[0] board.pc.south_bridge.keyboard.keyboard_int_pin[0] board.pc.south_bridge.pit.int_pin[1] None None None None None None None None None board.pc.south_bridge.keyboard.mouse_int_pin[0] None board.pc.south_bridge.ide.int_primary[1] board.pc.south_bridge.ide.int_secondary[1]
int_requestor=board.iobus.cpu_side_ports[1]
pio=board.iobus.mem_side_ports[8]
[board.pc.south_bridge.io_apic.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.south_bridge.keyboard]
type=I8042
children=keyboard mouse power_state
clk_domain=board.clk_domain
command_port=9223372036854775908
data_port=9223372036854775904
eventq_index=0
keyboard=board.pc.south_bridge.keyboard.keyboard
mouse=board.pc.south_bridge.keyboard.mouse
pio_latency=100000
power_model=
power_state=board.pc.south_bridge.keyboard.power_state
system=board
keyboard_int_pin=board.pc.south_bridge.io_apic.inputs[1]
mouse_int_pin=board.pc.south_bridge.io_apic.inputs[12]
pio=board.iobus.mem_side_ports[3]
[board.pc.south_bridge.keyboard.keyboard]
type=PS2Keyboard
eventq_index=0
vnc=Null
[board.pc.south_bridge.keyboard.mouse]
type=PS2Mouse
eventq_index=0
[board.pc.south_bridge.keyboard.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.south_bridge.pic1]
type=I8259
children=power_state
clk_domain=board.clk_domain
eventq_index=0
mode=I8259Master
pio_addr=9223372036854775840
pio_latency=100000
power_model=
power_state=board.pc.south_bridge.pic1.power_state
slave=board.pc.south_bridge.pic2
system=board
inputs=board.pc.south_bridge.pit.int_pin[0] None board.pc.south_bridge.pic2.output[0]
output=board.pc.south_bridge.io_apic.inputs[0]
pio=board.iobus.mem_side_ports[4]
[board.pc.south_bridge.pic1.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.south_bridge.pic2]
type=I8259
children=power_state
clk_domain=board.clk_domain
eventq_index=0
mode=I8259Slave
pio_addr=9223372036854775968
pio_latency=100000
power_model=
power_state=board.pc.south_bridge.pic2.power_state
slave=Null
system=board
inputs=board.pc.south_bridge.cmos.int_pin[0] None None None None None board.pc.south_bridge.ide.int_primary[0] board.pc.south_bridge.ide.int_secondary[0]
output=board.pc.south_bridge.pic1.inputs[2]
pio=board.iobus.mem_side_ports[5]
[board.pc.south_bridge.pic2.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.south_bridge.pit]
type=I8254
children=power_state
clk_domain=board.clk_domain
eventq_index=0
pio_addr=9223372036854775872
pio_latency=100000
power_model=
power_state=board.pc.south_bridge.pit.power_state
system=board
int_pin=board.pc.south_bridge.pic1.inputs[0] board.pc.south_bridge.io_apic.inputs[2]
pio=board.iobus.mem_side_ports[6]
[board.pc.south_bridge.pit.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.pc.south_bridge.speaker]
type=PcSpeaker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
i8254=board.pc.south_bridge.pit
pio_addr=9223372036854775905
pio_latency=100000
power_model=
power_state=board.pc.south_bridge.speaker.power_state
system=board
pio=board.iobus.mem_side_ports[7]
[board.pc.south_bridge.speaker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.processor]
type=SubSystem
children=kvm_vm start0 start1 switch0 switch1
eventq_index=0
thermal_domain=Null
[board.processor.kvm_vm]
type=KvmVM
coalescedMMIO=
eventq_index=0
system=board
[board.processor.start0]
type=SubSystem
children=core
eventq_index=0
thermal_domain=Null
[board.processor.start0.core]
type=X86KvmCPU
children=decoder interrupts isa mmu power_state tracer
alwaysSyncTC=false
checker=Null
clk_domain=board.clk_domain
cpu_id=0
decoder=board.processor.start0.core.decoder
do_checkpoint_insts=true
do_statistics_insts=true
eventq_index=1
function_trace=false
function_trace_start=0
hostFactor=1.0
hostFreq=500
interrupts=board.processor.start0.core.interrupts
isa=board.processor.start0.core.isa
max_insts_all_threads=0
max_insts_any_thread=0
mmu=board.processor.start0.core.mmu
numThreads=1
power_gating_on_idle=false
power_model=
power_state=board.processor.start0.core.power_state
progress_interval=0
pwr_gating_latency=300
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=board
tracer=board.processor.start0.core.tracer
useCoalescedMMIO=false
usePerf=true
usePerfOverflow=false
useXSave=true
workload=
dcache_port=board.cache_hierarchy.l1dcaches0.cpu_side
icache_port=board.cache_hierarchy.l1icaches0.cpu_side
[board.processor.start0.core.decoder]
type=X86Decoder
eventq_index=0
isa=board.processor.start0.core.isa
[board.processor.start0.core.interrupts]
type=X86LocalApic
children=clk_domain
clk_domain=board.processor.start0.core.interrupts.clk_domain
eventq_index=0
int_latency=1000
pio_latency=100000
system=board
int_requestor=board.cache_hierarchy.membus.cpu_side_ports[7]
int_responder=board.cache_hierarchy.membus.mem_side_ports[4]
pio=board.cache_hierarchy.membus.mem_side_ports[3]
[board.processor.start0.core.interrupts.clk_domain]
type=DerivedClockDomain
clk_divider=16
clk_domain=board.clk_domain
eventq_index=0
[board.processor.start0.core.isa]
type=X86ISA
APMInfo=2147483672 1752462657 1769238117 1145913699
CacheParams=0 0 0 0
ExtendedFeatures=0 25165824 0 0
ExtendedState=0 0 0 0 0 0 0 0
FamilyModelStepping=134993 2053 4024171519 521
FamilyModelSteppingBrandFeatures=134993 1029 3956538367 131073
L1CacheAndTLB=4278779656 4280352544 1073873216 1073873216
L2L3CacheAndL2TLB=0 1107313152 0 67141952
LongModeAddressSize=12336 0 0 0
eventq_index=0
name_string=Fake gem5 x86_64 CPU
vendor_string=HygonGenuine
[board.processor.start0.core.mmu]
type=X86MMU
children=dtb itb
dtb=board.processor.start0.core.mmu.dtb
eventq_index=0
itb=board.processor.start0.core.mmu.itb
[board.processor.start0.core.mmu.dtb]
type=X86TLB
children=walker
entry_type=data
eventq_index=0
next_level=Null
size=64
system=board
walker=board.processor.start0.core.mmu.dtb.walker
[board.processor.start0.core.mmu.dtb.walker]
type=X86PagetableWalker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
num_squash_per_cycle=4
power_model=
power_state=board.processor.start0.core.mmu.dtb.walker.power_state
system=board
port=board.cache_hierarchy.membus.cpu_side_ports[6]
[board.processor.start0.core.mmu.dtb.walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.processor.start0.core.mmu.itb]
type=X86TLB
children=walker
entry_type=instruction
eventq_index=0
next_level=Null
size=64
system=board
walker=board.processor.start0.core.mmu.itb.walker
[board.processor.start0.core.mmu.itb.walker]
type=X86PagetableWalker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
num_squash_per_cycle=4
power_model=
power_state=board.processor.start0.core.mmu.itb.walker.power_state
system=board
port=board.cache_hierarchy.membus.cpu_side_ports[5]
[board.processor.start0.core.mmu.itb.walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.processor.start0.core.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=ON CLK_GATED OFF
[board.processor.start0.core.tracer]
type=ExeTracer
children=disassembler
disassembler=board.processor.start0.core.tracer.disassembler
eventq_index=0
[board.processor.start0.core.tracer.disassembler]
type=InstDisassembler
eventq_index=0
[board.processor.start1]
type=SubSystem
children=core
eventq_index=0
thermal_domain=Null
[board.processor.start1.core]
type=X86KvmCPU
children=decoder interrupts isa mmu power_state tracer
alwaysSyncTC=false
checker=Null
clk_domain=board.clk_domain
cpu_id=1
decoder=board.processor.start1.core.decoder
do_checkpoint_insts=true
do_statistics_insts=true
eventq_index=2
function_trace=false
function_trace_start=0
hostFactor=1.0
hostFreq=500
interrupts=board.processor.start1.core.interrupts
isa=board.processor.start1.core.isa
max_insts_all_threads=0
max_insts_any_thread=0
mmu=board.processor.start1.core.mmu
numThreads=1
power_gating_on_idle=false
power_model=
power_state=board.processor.start1.core.power_state
progress_interval=0
pwr_gating_latency=300
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=board
tracer=board.processor.start1.core.tracer
useCoalescedMMIO=false
usePerf=true
usePerfOverflow=false
useXSave=true
workload=
dcache_port=board.cache_hierarchy.l1dcaches1.cpu_side
icache_port=board.cache_hierarchy.l1icaches1.cpu_side
[board.processor.start1.core.decoder]
type=X86Decoder
eventq_index=0
isa=board.processor.start1.core.isa
[board.processor.start1.core.interrupts]
type=X86LocalApic
children=clk_domain
clk_domain=board.processor.start1.core.interrupts.clk_domain
eventq_index=0
int_latency=1000
pio_latency=100000
system=board
int_requestor=board.cache_hierarchy.membus.cpu_side_ports[12]
int_responder=board.cache_hierarchy.membus.mem_side_ports[6]
pio=board.cache_hierarchy.membus.mem_side_ports[5]
[board.processor.start1.core.interrupts.clk_domain]
type=DerivedClockDomain
clk_divider=16
clk_domain=board.clk_domain
eventq_index=0
[board.processor.start1.core.isa]
type=X86ISA
APMInfo=2147483672 1752462657 1769238117 1145913699
CacheParams=0 0 0 0
ExtendedFeatures=0 25165824 0 0
ExtendedState=0 0 0 0 0 0 0 0
FamilyModelStepping=134993 2053 4024171519 521
FamilyModelSteppingBrandFeatures=134993 1029 3956538367 131073
L1CacheAndTLB=4278779656 4280352544 1073873216 1073873216
L2L3CacheAndL2TLB=0 1107313152 0 67141952
LongModeAddressSize=12336 0 0 0
eventq_index=0
name_string=Fake gem5 x86_64 CPU
vendor_string=HygonGenuine
[board.processor.start1.core.mmu]
type=X86MMU
children=dtb itb
dtb=board.processor.start1.core.mmu.dtb
eventq_index=0
itb=board.processor.start1.core.mmu.itb
[board.processor.start1.core.mmu.dtb]
type=X86TLB
children=walker
entry_type=data
eventq_index=0
next_level=Null
size=64
system=board
walker=board.processor.start1.core.mmu.dtb.walker
[board.processor.start1.core.mmu.dtb.walker]
type=X86PagetableWalker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
num_squash_per_cycle=4
power_model=
power_state=board.processor.start1.core.mmu.dtb.walker.power_state
system=board
port=board.cache_hierarchy.membus.cpu_side_ports[11]
[board.processor.start1.core.mmu.dtb.walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.processor.start1.core.mmu.itb]
type=X86TLB
children=walker
entry_type=instruction
eventq_index=0
next_level=Null
size=64
system=board
walker=board.processor.start1.core.mmu.itb.walker
[board.processor.start1.core.mmu.itb.walker]
type=X86PagetableWalker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
num_squash_per_cycle=4
power_model=
power_state=board.processor.start1.core.mmu.itb.walker.power_state
system=board
port=board.cache_hierarchy.membus.cpu_side_ports[10]
[board.processor.start1.core.mmu.itb.walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.processor.start1.core.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=ON CLK_GATED OFF
[board.processor.start1.core.tracer]
type=ExeTracer
children=disassembler
disassembler=board.processor.start1.core.tracer.disassembler
eventq_index=0
[board.processor.start1.core.tracer.disassembler]
type=InstDisassembler
eventq_index=0
[board.processor.switch0]
type=SubSystem
children=core
eventq_index=0
thermal_domain=Null
[board.processor.switch0.core]
type=BaseTimingSimpleCPU
children=decoder isa mmu power_state tracer
branchPred=Null
checker=Null
clk_domain=board.clk_domain
cpu_id=0
decoder=board.processor.switch0.core.decoder
do_checkpoint_insts=true
do_statistics_insts=true
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=
isa=board.processor.switch0.core.isa
max_insts_all_threads=0
max_insts_any_thread=0
mmu=board.processor.switch0.core.mmu
numThreads=1
power_gating_on_idle=false
power_model=
power_state=board.processor.switch0.core.power_state
progress_interval=0
pwr_gating_latency=300
simpoint_start_insts=
socket_id=0
switched_out=true
syscallRetryLatency=10000
system=board
tracer=board.processor.switch0.core.tracer
workload=
[board.processor.switch0.core.decoder]
type=X86Decoder
eventq_index=0
isa=board.processor.switch0.core.isa
[board.processor.switch0.core.isa]
type=X86ISA
APMInfo=2147483672 1752462657 1769238117 1145913699
CacheParams=0 0 0 0
ExtendedFeatures=0 25165824 0 0
ExtendedState=0 0 0 0 0 0 0 0
FamilyModelStepping=134993 2053 4024171519 521
FamilyModelSteppingBrandFeatures=134993 1029 3956538367 131073
L1CacheAndTLB=4278779656 4280352544 1073873216 1073873216
L2L3CacheAndL2TLB=0 1107313152 0 67141952
LongModeAddressSize=12336 0 0 0
eventq_index=0
name_string=Fake gem5 x86_64 CPU
vendor_string=HygonGenuine
[board.processor.switch0.core.mmu]
type=X86MMU
children=dtb itb
dtb=board.processor.switch0.core.mmu.dtb
eventq_index=0
itb=board.processor.switch0.core.mmu.itb
[board.processor.switch0.core.mmu.dtb]
type=X86TLB
children=walker
entry_type=data
eventq_index=0
next_level=Null
size=64
system=board
walker=board.processor.switch0.core.mmu.dtb.walker
[board.processor.switch0.core.mmu.dtb.walker]
type=X86PagetableWalker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
num_squash_per_cycle=4
power_model=
power_state=board.processor.switch0.core.mmu.dtb.walker.power_state
system=board
[board.processor.switch0.core.mmu.dtb.walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.processor.switch0.core.mmu.itb]
type=X86TLB
children=walker
entry_type=instruction
eventq_index=0
next_level=Null
size=64
system=board
walker=board.processor.switch0.core.mmu.itb.walker
[board.processor.switch0.core.mmu.itb.walker]
type=X86PagetableWalker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
num_squash_per_cycle=4
power_model=
power_state=board.processor.switch0.core.mmu.itb.walker.power_state
system=board
[board.processor.switch0.core.mmu.itb.walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.processor.switch0.core.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=ON CLK_GATED OFF
[board.processor.switch0.core.tracer]
type=ExeTracer
children=disassembler
disassembler=board.processor.switch0.core.tracer.disassembler
eventq_index=0
[board.processor.switch0.core.tracer.disassembler]
type=InstDisassembler
eventq_index=0
[board.processor.switch1]
type=SubSystem
children=core
eventq_index=0
thermal_domain=Null
[board.processor.switch1.core]
type=BaseTimingSimpleCPU
children=decoder isa mmu power_state tracer
branchPred=Null
checker=Null
clk_domain=board.clk_domain
cpu_id=1
decoder=board.processor.switch1.core.decoder
do_checkpoint_insts=true
do_statistics_insts=true
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=
isa=board.processor.switch1.core.isa
max_insts_all_threads=0
max_insts_any_thread=0
mmu=board.processor.switch1.core.mmu
numThreads=1
power_gating_on_idle=false
power_model=
power_state=board.processor.switch1.core.power_state
progress_interval=0
pwr_gating_latency=300
simpoint_start_insts=
socket_id=0
switched_out=true
syscallRetryLatency=10000
system=board
tracer=board.processor.switch1.core.tracer
workload=
[board.processor.switch1.core.decoder]
type=X86Decoder
eventq_index=0
isa=board.processor.switch1.core.isa
[board.processor.switch1.core.isa]
type=X86ISA
APMInfo=2147483672 1752462657 1769238117 1145913699
CacheParams=0 0 0 0
ExtendedFeatures=0 25165824 0 0
ExtendedState=0 0 0 0 0 0 0 0
FamilyModelStepping=134993 2053 4024171519 521
FamilyModelSteppingBrandFeatures=134993 1029 3956538367 131073
L1CacheAndTLB=4278779656 4280352544 1073873216 1073873216
L2L3CacheAndL2TLB=0 1107313152 0 67141952
LongModeAddressSize=12336 0 0 0
eventq_index=0
name_string=Fake gem5 x86_64 CPU
vendor_string=HygonGenuine
[board.processor.switch1.core.mmu]
type=X86MMU
children=dtb itb
dtb=board.processor.switch1.core.mmu.dtb
eventq_index=0
itb=board.processor.switch1.core.mmu.itb
[board.processor.switch1.core.mmu.dtb]
type=X86TLB
children=walker
entry_type=data
eventq_index=0
next_level=Null
size=64
system=board
walker=board.processor.switch1.core.mmu.dtb.walker
[board.processor.switch1.core.mmu.dtb.walker]
type=X86PagetableWalker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
num_squash_per_cycle=4
power_model=
power_state=board.processor.switch1.core.mmu.dtb.walker.power_state
system=board
[board.processor.switch1.core.mmu.dtb.walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.processor.switch1.core.mmu.itb]
type=X86TLB
children=walker
entry_type=instruction
eventq_index=0
next_level=Null
size=64
system=board
walker=board.processor.switch1.core.mmu.itb.walker
[board.processor.switch1.core.mmu.itb.walker]
type=X86PagetableWalker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
num_squash_per_cycle=4
power_model=
power_state=board.processor.switch1.core.mmu.itb.walker.power_state
system=board
[board.processor.switch1.core.mmu.itb.walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=
[board.processor.switch1.core.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=ON CLK_GATED OFF
[board.processor.switch1.core.tracer]
type=ExeTracer
children=disassembler
disassembler=board.processor.switch1.core.tracer.disassembler
eventq_index=0
[board.processor.switch1.core.tracer.disassembler]
type=InstDisassembler
eventq_index=0
[board.workload]
type=X86FsLinux
children=acpi_description_table_pointer e820_table intel_mp_pointer intel_mp_table smbios_table
acpi_description_table_pointer=board.workload.acpi_description_table_pointer
addr_check=true
command_line=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/sda2
e820_table=board.workload.e820_table
enable_osxsave=false
eventq_index=0
exit_on_kernel_oops=false
exit_on_kernel_panic=true
extras=
extras_addrs=
intel_mp_pointer=board.workload.intel_mp_pointer
intel_mp_table=board.workload.intel_mp_table
load_addr_mask=18446744073709551615
load_addr_offset=0
object_file=/home/namiel/.cache/gem5/x86-linux-kernel-6.8.0-52-generic-1.0.0
on_oops=DumpDmesgAndExit
on_panic=DumpDmesgAndExit
remote_gdb_port=#7000
smbios_table=board.workload.smbios_table
wait_for_remote_gdb=false
[board.workload.acpi_description_table_pointer]
type=X86ACPIRSDP
children=rsdt xsdt
eventq_index=0
oem_id=gem5
revision=2
rsdt=board.workload.acpi_description_table_pointer.rsdt
xsdt=board.workload.acpi_description_table_pointer.xsdt
[board.workload.acpi_description_table_pointer.rsdt]
type=X86ACPIRSDT
children=entries
creator_id=0
creator_revision=0
entries=board.workload.acpi_description_table_pointer.rsdt.entries
eventq_index=0
oem_id=gem5
oem_revision=0
oem_table_id=
[board.workload.acpi_description_table_pointer.rsdt.entries]
type=X86ACPIMadt
children=records00 records01 records02 records03 records04 records05 records06 records07 records08 records09 records10 records11 records12 records13 records14 records15 records16 records17
creator_id=0
creator_revision=0
eventq_index=0
flags=0
local_apic_address=0
oem_id=madt
oem_revision=0
oem_table_id=
records=board.workload.acpi_description_table_pointer.rsdt.entries.records00 board.workload.acpi_description_table_pointer.rsdt.entries.records01 board.workload.acpi_description_table_pointer.rsdt.entries.records02 board.workload.acpi_description_table_pointer.rsdt.entries.records03 board.workload.acpi_description_table_pointer.rsdt.entries.records04 board.workload.acpi_description_table_pointer.rsdt.entries.records05 board.workload.acpi_description_table_pointer.rsdt.entries.records06 board.workload.acpi_description_table_pointer.rsdt.entries.records07 board.workload.acpi_description_table_pointer.rsdt.entries.records08 board.workload.acpi_description_table_pointer.rsdt.entries.records09 board.workload.acpi_description_table_pointer.rsdt.entries.records10 board.workload.acpi_description_table_pointer.rsdt.entries.records11 board.workload.acpi_description_table_pointer.rsdt.entries.records12 board.workload.acpi_description_table_pointer.rsdt.entries.records13 board.workload.acpi_description_table_pointer.rsdt.entries.records14 board.workload.acpi_description_table_pointer.rsdt.entries.records15 board.workload.acpi_description_table_pointer.rsdt.entries.records16 board.workload.acpi_description_table_pointer.rsdt.entries.records17
[board.workload.acpi_description_table_pointer.rsdt.entries.records00]
type=X86ACPIMadtLAPIC
acpi_processor_id=0
apic_id=0
eventq_index=0
flags=1
[board.workload.acpi_description_table_pointer.rsdt.entries.records01]
type=X86ACPIMadtLAPIC
acpi_processor_id=1
apic_id=1
eventq_index=0
flags=1
[board.workload.acpi_description_table_pointer.rsdt.entries.records02]
type=X86ACPIMadtIOAPIC
address=4273995776
eventq_index=0
id=2
int_base=0
[board.workload.acpi_description_table_pointer.rsdt.entries.records03]
type=X86ACPIMadtIntSourceOverride
bus_source=0
eventq_index=0
flags=0
irq_source=16
sys_int=16
[board.workload.acpi_description_table_pointer.rsdt.entries.records04]
type=X86ACPIMadtIntSourceOverride
bus_source=1
eventq_index=0
flags=0
irq_source=0
sys_int=2
[board.workload.acpi_description_table_pointer.rsdt.entries.records05]
type=X86ACPIMadtIntSourceOverride
bus_source=1
eventq_index=0
flags=0
irq_source=1
sys_int=1
[board.workload.acpi_description_table_pointer.rsdt.entries.records06]
type=X86ACPIMadtIntSourceOverride
bus_source=1
eventq_index=0
flags=0
irq_source=3
sys_int=3
[board.workload.acpi_description_table_pointer.rsdt.entries.records07]
type=X86ACPIMadtIntSourceOverride
bus_source=1
eventq_index=0
flags=0
irq_source=4
sys_int=4
[board.workload.acpi_description_table_pointer.rsdt.entries.records08]
type=X86ACPIMadtIntSourceOverride
bus_source=1
eventq_index=0
flags=0
irq_source=5
sys_int=5
[board.workload.acpi_description_table_pointer.rsdt.entries.records09]
type=X86ACPIMadtIntSourceOverride
bus_source=1
eventq_index=0
flags=0
irq_source=6
sys_int=6
[board.workload.acpi_description_table_pointer.rsdt.entries.records10]
type=X86ACPIMadtIntSourceOverride
bus_source=1
eventq_index=0
flags=0
irq_source=7
sys_int=7
[board.workload.acpi_description_table_pointer.rsdt.entries.records11]
type=X86ACPIMadtIntSourceOverride
bus_source=1
eventq_index=0
flags=0
irq_source=8
sys_int=8
[board.workload.acpi_description_table_pointer.rsdt.entries.records12]
type=X86ACPIMadtIntSourceOverride
bus_source=1
eventq_index=0
flags=0
irq_source=9
sys_int=9
[board.workload.acpi_description_table_pointer.rsdt.entries.records13]
type=X86ACPIMadtIntSourceOverride
bus_source=1
eventq_index=0
flags=0
irq_source=10
sys_int=10
[board.workload.acpi_description_table_pointer.rsdt.entries.records14]
type=X86ACPIMadtIntSourceOverride
bus_source=1
eventq_index=0
flags=0
irq_source=11
sys_int=11
[board.workload.acpi_description_table_pointer.rsdt.entries.records15]
type=X86ACPIMadtIntSourceOverride
bus_source=1
eventq_index=0
flags=0
irq_source=12
sys_int=12
[board.workload.acpi_description_table_pointer.rsdt.entries.records16]
type=X86ACPIMadtIntSourceOverride
bus_source=1
eventq_index=0
flags=0
irq_source=13
sys_int=13
[board.workload.acpi_description_table_pointer.rsdt.entries.records17]
type=X86ACPIMadtIntSourceOverride
bus_source=1
eventq_index=0
flags=0
irq_source=14
sys_int=14
[board.workload.acpi_description_table_pointer.xsdt]
type=X86ACPIXSDT
creator_id=0
creator_revision=0
entries=board.workload.acpi_description_table_pointer.rsdt.entries
eventq_index=0
oem_id=gem5
oem_revision=0
oem_table_id=
[board.workload.e820_table]
type=X86E820Table
children=entries0 entries1 entries2 entries3
entries=board.workload.e820_table.entries0 board.workload.e820_table.entries1 board.workload.e820_table.entries2 board.workload.e820_table.entries3
eventq_index=0
[board.workload.e820_table.entries0]
type=X86E820Entry
addr=0
eventq_index=0
range_type=1
size=654336
[board.workload.e820_table.entries1]
type=X86E820Entry
addr=654336
eventq_index=0
range_type=2
size=394240
[board.workload.e820_table.entries2]
type=X86E820Entry
addr=1048576
eventq_index=0
range_type=1
size=3220176896
[board.workload.e820_table.entries3]
type=X86E820Entry
addr=4294901760
eventq_index=0
range_type=2
size=65536
[board.workload.intel_mp_pointer]
type=X86IntelMPFloatingPointer
default_config=0
eventq_index=0
imcr_present=true
spec_rev=4
[board.workload.intel_mp_table]
type=X86IntelMPConfigTable
children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 base_entries33 ext_entries
base_entries=board.workload.intel_mp_table.base_entries00 board.workload.intel_mp_table.base_entries01 board.workload.intel_mp_table.base_entries02 board.workload.intel_mp_table.base_entries03 board.workload.intel_mp_table.base_entries04 board.workload.intel_mp_table.base_entries05 board.workload.intel_mp_table.base_entries06 board.workload.intel_mp_table.base_entries07 board.workload.intel_mp_table.base_entries08 board.workload.intel_mp_table.base_entries09 board.workload.intel_mp_table.base_entries10 board.workload.intel_mp_table.base_entries11 board.workload.intel_mp_table.base_entries12 board.workload.intel_mp_table.base_entries13 board.workload.intel_mp_table.base_entries14 board.workload.intel_mp_table.base_entries15 board.workload.intel_mp_table.base_entries16 board.workload.intel_mp_table.base_entries17 board.workload.intel_mp_table.base_entries18 board.workload.intel_mp_table.base_entries19 board.workload.intel_mp_table.base_entries20 board.workload.intel_mp_table.base_entries21 board.workload.intel_mp_table.base_entries22 board.workload.intel_mp_table.base_entries23 board.workload.intel_mp_table.base_entries24 board.workload.intel_mp_table.base_entries25 board.workload.intel_mp_table.base_entries26 board.workload.intel_mp_table.base_entries27 board.workload.intel_mp_table.base_entries28 board.workload.intel_mp_table.base_entries29 board.workload.intel_mp_table.base_entries30 board.workload.intel_mp_table.base_entries31 board.workload.intel_mp_table.base_entries32 board.workload.intel_mp_table.base_entries33
eventq_index=0
ext_entries=board.workload.intel_mp_table.ext_entries
local_apic=4276092928
oem_id=
oem_table_addr=0
oem_table_size=0
product_id=
spec_rev=4
[board.workload.intel_mp_table.base_entries00]
type=X86IntelMPProcessor
bootstrap=true
enable=true
eventq_index=0
family=0
feature_flags=0
local_apic_id=0
local_apic_version=20
model=0
stepping=0
[board.workload.intel_mp_table.base_entries01]
type=X86IntelMPProcessor
bootstrap=false
enable=true
eventq_index=0
family=0
feature_flags=0
local_apic_id=1
local_apic_version=20
model=0
stepping=0
[board.workload.intel_mp_table.base_entries02]
type=X86IntelMPIOAPIC
address=4273995776
enable=true
eventq_index=0
id=2
version=17
[board.workload.intel_mp_table.base_entries03]
type=X86IntelMPBus
bus_id=0
bus_type=PCI
eventq_index=0
[board.workload.intel_mp_table.base_entries04]
type=X86IntelMPBus
bus_id=1
bus_type=ISA
eventq_index=0
[board.workload.intel_mp_table.base_entries05]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=16
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=0
source_bus_irq=16
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries06]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=0
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries07]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=2
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=0
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries08]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=1
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries09]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=1
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=1
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries10]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=3
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries11]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=3
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=3
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries12]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=4
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries13]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=4
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=4
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries14]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=5
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries15]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=5
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=5
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries16]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=6
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries17]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=6
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=6
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries18]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=7
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries19]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=7
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=7
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries20]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=8
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries21]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=8
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=8
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries22]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=9
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries23]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=9
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=9
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries24]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=10
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries25]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=10
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=10
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries26]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=11
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries27]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=11
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=11
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries28]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=12
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries29]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=12
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=12
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries30]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=13
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries31]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=13
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=13
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries32]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=14
trigger=ConformTrigger
[board.workload.intel_mp_table.base_entries33]
type=X86IntelMPIOIntAssignment
dest_io_apic_id=2
dest_io_apic_intin=14
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
source_bus_id=1
source_bus_irq=14
trigger=ConformTrigger
[board.workload.intel_mp_table.ext_entries]
type=X86IntelMPBusHierarchy
bus_id=1
eventq_index=0
parent_bus=0
subtractive_decode=true
[board.workload.smbios_table]
type=X86SMBiosSMBiosTable
children=structures
eventq_index=0
major_version=2
minor_version=5
structures=board.workload.smbios_table.structures
[board.workload.smbios_table.structures]
type=X86SMBiosBiosInformation
characteristic_ext_bytes=
characteristics=
emb_cont_firmware_major=0
emb_cont_firmware_minor=0
eventq_index=0
major=0
minor=0
release_date=06/08/2008
rom_size=0
starting_addr_segment=0
vendor=
version=
[root]
type=Root
children=board
eventq_index=0
full_system=true
sim_quantum=1000000000
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000