[board]
type=System
children=cache_hierarchy clk_domain dvfs_handler memory processor workload
auto_unlink_shared_backstore=false
cache_line_size=64
eventq_index=0
exit_on_work_items=true
external_memory_ranges=
init_param=0
m5ops_base=4294901760
mem_mode=timing
mem_ranges=0:1073741824
memories=board.memory.mem_ctrl.dram
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
readfile=
redirect_paths=
shadow_rom_ranges=
shared_backstore=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
workload=board.workload
system_port=board.cache_hierarchy.membus.cpu_side_ports[0]

[board.cache_hierarchy]
type=SubSystem
children=dptw_caches iptw_caches l1dcaches l1icaches membus
eventq_index=0
thermal_domain=Null

[board.cache_hierarchy.dptw_caches]
type=Cache
children=power_state replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=20
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.dptw_caches.power_state
prefetcher=Null
replace_expansions=true
replacement_policy=board.cache_hierarchy.dptw_caches.replacement_policy
response_latency=1
sequential_access=false
size=8192
system=board
tag_latency=1
tags=board.cache_hierarchy.dptw_caches.tags
tgts_per_mshr=12
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=true
cpu_side=board.processor.cores.core.mmu.dtb_walker.port
mem_side=board.cache_hierarchy.membus.cpu_side_ports[4]

[board.cache_hierarchy.dptw_caches.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.dptw_caches.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.dptw_caches.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=4
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.dptw_caches.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.dptw_caches.tags.power_state
replacement_policy=board.cache_hierarchy.dptw_caches.replacement_policy
sequential_access=false
size=8192
system=board
tag_latency=1
warmup_percentage=0

[board.cache_hierarchy.dptw_caches.tags.indexing_policy]
type=TaggedSetAssociative
assoc=4
entry_size=64
eventq_index=0
size=8192

[board.cache_hierarchy.dptw_caches.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.iptw_caches]
type=Cache
children=power_state replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=20
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.iptw_caches.power_state
prefetcher=Null
replace_expansions=true
replacement_policy=board.cache_hierarchy.iptw_caches.replacement_policy
response_latency=1
sequential_access=false
size=8192
system=board
tag_latency=1
tags=board.cache_hierarchy.iptw_caches.tags
tgts_per_mshr=12
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=true
cpu_side=board.processor.cores.core.mmu.itb_walker.port
mem_side=board.cache_hierarchy.membus.cpu_side_ports[3]

[board.cache_hierarchy.iptw_caches.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.iptw_caches.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.iptw_caches.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=4
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.iptw_caches.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.iptw_caches.tags.power_state
replacement_policy=board.cache_hierarchy.iptw_caches.replacement_policy
sequential_access=false
size=8192
system=board
tag_latency=1
warmup_percentage=0

[board.cache_hierarchy.iptw_caches.tags.indexing_policy]
type=TaggedSetAssociative
assoc=4
entry_size=64
eventq_index=0
size=8192

[board.cache_hierarchy.iptw_caches.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1dcaches]
type=Cache
children=power_state prefetcher replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=16
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1dcaches.power_state
prefetcher=board.cache_hierarchy.l1dcaches.prefetcher
replace_expansions=true
replacement_policy=board.cache_hierarchy.l1dcaches.replacement_policy
response_latency=1
sequential_access=false
size=65536
system=board
tag_latency=1
tags=board.cache_hierarchy.l1dcaches.tags
tgts_per_mshr=20
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=false
cpu_side=board.processor.cores.core.dcache_port
mem_side=board.cache_hierarchy.membus.cpu_side_ports[2]

[board.cache_hierarchy.l1dcaches.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1dcaches.prefetcher]
type=StridePrefetcher
children=power_state table_indexing_policy table_replacement_policy
block_size=64
cache_snoop=false
clk_domain=board.clk_domain
confidence_counter_bits=3
confidence_threshold=50
degree=4
distance=0
eventq_index=0
initial_confidence=4
latency=1
max_prefetch_requests_with_pending_translation=32
on_data=true
on_inst=false
on_miss=false
on_read=true
on_write=true
page_bytes=4096
power_model=
power_state=board.cache_hierarchy.l1dcaches.prefetcher.power_state
prefetch_on_access=false
prefetch_on_pf_hit=true
queue_filter=true
queue_size=32
queue_squash=true
sys=board
table_assoc=4
table_entries=64
table_indexing_policy=board.cache_hierarchy.l1dcaches.prefetcher.table_indexing_policy
table_replacement_policy=board.cache_hierarchy.l1dcaches.prefetcher.table_replacement_policy
tag_prefetch=true
throttle_control_percentage=0
use_cache_line_address=true
use_requestor_id=true
use_virtual_addresses=false

[board.cache_hierarchy.l1dcaches.prefetcher.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1dcaches.prefetcher.table_indexing_policy]
type=StridePrefetcherHashedSetAssociative
assoc=4
entry_size=1
eventq_index=0
size=64

[board.cache_hierarchy.l1dcaches.prefetcher.table_replacement_policy]
type=RandomRP
eventq_index=0

[board.cache_hierarchy.l1dcaches.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.l1dcaches.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=8
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.l1dcaches.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1dcaches.tags.power_state
replacement_policy=board.cache_hierarchy.l1dcaches.replacement_policy
sequential_access=false
size=65536
system=board
tag_latency=1
warmup_percentage=0

[board.cache_hierarchy.l1dcaches.tags.indexing_policy]
type=TaggedSetAssociative
assoc=8
entry_size=64
eventq_index=0
size=65536

[board.cache_hierarchy.l1dcaches.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1icaches]
type=Cache
children=power_state prefetcher replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=16
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1icaches.power_state
prefetcher=board.cache_hierarchy.l1icaches.prefetcher
replace_expansions=true
replacement_policy=board.cache_hierarchy.l1icaches.replacement_policy
response_latency=1
sequential_access=false
size=65536
system=board
tag_latency=1
tags=board.cache_hierarchy.l1icaches.tags
tgts_per_mshr=20
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=true
cpu_side=board.processor.cores.core.icache_port
mem_side=board.cache_hierarchy.membus.cpu_side_ports[1]

[board.cache_hierarchy.l1icaches.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1icaches.prefetcher]
type=StridePrefetcher
children=power_state table_indexing_policy table_replacement_policy
block_size=64
cache_snoop=false
clk_domain=board.clk_domain
confidence_counter_bits=3
confidence_threshold=50
degree=4
distance=0
eventq_index=0
initial_confidence=4
latency=1
max_prefetch_requests_with_pending_translation=32
on_data=true
on_inst=false
on_miss=false
on_read=true
on_write=true
page_bytes=4096
power_model=
power_state=board.cache_hierarchy.l1icaches.prefetcher.power_state
prefetch_on_access=false
prefetch_on_pf_hit=true
queue_filter=true
queue_size=32
queue_squash=true
sys=board
table_assoc=4
table_entries=64
table_indexing_policy=board.cache_hierarchy.l1icaches.prefetcher.table_indexing_policy
table_replacement_policy=board.cache_hierarchy.l1icaches.prefetcher.table_replacement_policy
tag_prefetch=true
throttle_control_percentage=0
use_cache_line_address=true
use_requestor_id=true
use_virtual_addresses=false

[board.cache_hierarchy.l1icaches.prefetcher.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1icaches.prefetcher.table_indexing_policy]
type=StridePrefetcherHashedSetAssociative
assoc=4
entry_size=1
eventq_index=0
size=64

[board.cache_hierarchy.l1icaches.prefetcher.table_replacement_policy]
type=RandomRP
eventq_index=0

[board.cache_hierarchy.l1icaches.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.l1icaches.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=8
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.l1icaches.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1icaches.tags.power_state
replacement_policy=board.cache_hierarchy.l1icaches.replacement_policy
sequential_access=false
size=65536
system=board
tag_latency=1
warmup_percentage=0

[board.cache_hierarchy.l1icaches.tags.indexing_policy]
type=TaggedSetAssociative
assoc=8
entry_size=64
eventq_index=0
size=65536

[board.cache_hierarchy.l1icaches.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.membus]
type=CoherentXBar
children=badaddr_responder power_state snoop_filter
clk_domain=board.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
header_latency=1
max_outstanding_snoops=512
max_routing_table_size=512
point_of_coherency=true
point_of_unification=true
power_model=
power_state=board.cache_hierarchy.membus.power_state
response_latency=2
snoop_filter=board.cache_hierarchy.membus.snoop_filter
snoop_response_latency=4
system=board
use_default_range=false
width=64
cpu_side_ports=board.system_port board.cache_hierarchy.l1icaches.mem_side board.cache_hierarchy.l1dcaches.mem_side board.cache_hierarchy.iptw_caches.mem_side board.cache_hierarchy.dptw_caches.mem_side
default=board.cache_hierarchy.membus.badaddr_responder.pio
mem_side_ports=board.memory.mem_ctrl.port

[board.cache_hierarchy.membus.badaddr_responder]
type=IsaFake
children=power_state
clk_domain=board.clk_domain
eventq_index=0
fake_mem=false
pio_addr=0
pio_latency=100000
pio_size=8
power_model=
power_state=board.cache_hierarchy.membus.badaddr_responder.power_state
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=board
update_data=false
warn_access=
pio=board.cache_hierarchy.membus.default

[board.cache_hierarchy.membus.badaddr_responder.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.membus.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=board

[board.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=board.clk_domain.voltage_domain

[board.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0

[board.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=board.clk_domain
transition_latency=100000000

[board.memory]
type=SubSystem
children=mem_ctrl
eventq_index=0
thermal_domain=Null

[board.memory.mem_ctrl]
type=MemCtrl
children=dram power_state
clk_domain=board.clk_domain
command_window=10000
disable_sanity_check=false
dram=board.memory.mem_ctrl.dram
eventq_index=0
mem_sched_policy=frfcfs
min_reads_per_switch=16
min_writes_per_switch=16
power_model=
power_state=board.memory.mem_ctrl.power_state
qos_policy=Null
qos_priorities=1
qos_priority_escalation=false
qos_q_policy=fifo
qos_requestors=               
qos_syncro_scheduler=false
qos_turnaround_policy=Null
static_backend_latency=10000
static_frontend_latency=10000
system=board
write_high_thresh_perc=85
write_low_thresh_perc=50
port=board.cache_hierarchy.membus.mem_side_ports[0]

[board.memory.mem_ctrl.dram]
type=DRAMInterface
children=power_state
IDD0=0.048
IDD02=0.003
IDD2N=0.034
IDD2N2=0.0
IDD2P0=0.0
IDD2P02=0.0
IDD2P1=0.025
IDD2P12=0.0
IDD3N=0.043000000000000003
IDD3N2=0.003
IDD3P0=0.0
IDD3P02=0.0
IDD3P1=0.037
IDD3P12=0.0
IDD4R=0.135
IDD4R2=0.0
IDD4W=0.123
IDD4W2=0.0
IDD5=0.25
IDD52=0.0
IDD6=0.03
IDD62=0.0
VDD=1.2
VDD2=2.5
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=4
banks_per_rank=16
beats_per_clock=2
burst_length=8
clk_domain=board.clk_domain
collect_stats=true
conf_table_reported=true
data_clock_sync=false
device_bus_width=8
device_rowbuffer_size=1024
device_size=1073741824
devices_per_rank=8
dll=true
enable_dram_powerdown=false
eventq_index=0
image_file=
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
null=false
page_policy=open_adaptive
power_model=
power_state=board.memory.mem_ctrl.dram.power_state
range=0:1073741824
ranks_per_channel=2
read_buffer_size=64
tAAD=833
tBURST=3332
tBURST_MAX=3332
tBURST_MIN=3332
tCCD_L=5000
tCCD_L_WR=5000
tCK=833
tCL=14160
tCS=1666
tCWL=14160
tPPD=0
tRAS=32000
tRCD=14160
tRCD_WR=14160
tREFI=7800000
tRFC=350000
tRP=14160
tRRD=3332
tRRD_L=4900
tRTP=7500
tRTW=1666
tWR=15000
tWTR=5000
tWTR_L=5000
tXAW=21000
tXP=6000
tXPDLL=0
tXS=340000
tXSDLL=0
two_cycle_activate=false
write_buffer_size=128
writeable=true

[board.memory.mem_ctrl.dram.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.memory.mem_ctrl.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.processor]
type=SubSystem
children=cores
eventq_index=0
thermal_domain=Null

[board.processor.cores]
type=SubSystem
children=core
eventq_index=0
thermal_domain=Null

[board.processor.cores.core]
type=BaseTimingSimpleCPU
children=decoder interrupts isa mmu power_state tracer workload
branchPred=Null
checker=Null
clk_domain=board.clk_domain
cpu_id=0
decoder=board.processor.cores.core.decoder
do_checkpoint_insts=true
do_statistics_insts=true
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=board.processor.cores.core.interrupts
isa=board.processor.cores.core.isa
max_insts_all_threads=0
max_insts_any_thread=0
mmu=board.processor.cores.core.mmu
numThreads=1
power_gating_on_idle=false
power_model=
power_state=board.processor.cores.core.power_state
progress_interval=0
pwr_gating_latency=300
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=board
tracer=board.processor.cores.core.tracer
workload=board.processor.cores.core.workload
dcache_port=board.cache_hierarchy.l1dcaches.cpu_side
icache_port=board.cache_hierarchy.l1icaches.cpu_side

[board.processor.cores.core.decoder]
type=ArmDecoder
dvm_enabled=false
eventq_index=0
isa=board.processor.cores.core.isa

[board.processor.cores.core.interrupts]
type=ArmInterrupts
eventq_index=0

[board.processor.cores.core.isa]
type=ArmISA
children=release_se
decoderFlavor=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=15790086
id_aa64dfr1_el1=0
id_aa64isar0_el1=268435456
id_aa64isar1_el1=16846864
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=1052704
id_aa64mmfr2_el1=65552
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=285212672
id_isar6=1
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
id_mmfr4=0
impdef_nop=false
midr=0
mpamidr_el1=3746995439730032896
pmu=Null
release_se=board.processor.cores.core.isa.release_se
sme_vl_se=1
sve_vl_se=1
system=board

[board.processor.cores.core.isa.release_se]
type=ArmRelease
eventq_index=0
extensions=FEAT_AES FEAT_PMULL FEAT_SHA1 FEAT_SHA256 FEAT_CRC32 FEAT_LSE FEAT_RDM FEAT_F32MM FEAT_F64MM FEAT_SVE FEAT_I8MM FEAT_DOTPROD FEAT_FCMA FEAT_JSCVT FEAT_PAuth FEAT_FLAGM FEAT_FLAGM2 FEAT_SME TME

[board.processor.cores.core.mmu]
type=ArmMMU
children=dtb dtb_walker itb itb_walker l2_shared stage2_dtb stage2_dtb_walker stage2_itb stage2_itb_walker
dtb=board.processor.cores.core.mmu.dtb
dtb_walker=board.processor.cores.core.mmu.dtb_walker
eventq_index=0
itb=board.processor.cores.core.mmu.itb
itb_walker=board.processor.cores.core.mmu.itb_walker
release_se=board.processor.cores.core.isa.release_se
stage2_dtb=board.processor.cores.core.mmu.stage2_dtb
stage2_dtb_walker=board.processor.cores.core.mmu.stage2_dtb_walker
stage2_itb=board.processor.cores.core.mmu.stage2_itb
stage2_itb_walker=board.processor.cores.core.mmu.stage2_itb_walker
sys=board

[board.processor.cores.core.mmu.dtb]
type=ArmTLB
children=indexing_policy replacement_policy
assoc=64
entry_type=data
eventq_index=0
indexing_policy=board.processor.cores.core.mmu.dtb.indexing_policy
is_stage2=false
next_level=board.processor.cores.core.mmu.l2_shared
partial_levels=
replacement_policy=board.processor.cores.core.mmu.dtb.replacement_policy
size=64
sys=board

[board.processor.cores.core.mmu.dtb.indexing_policy]
type=TLBSetAssociative
assoc=64
eventq_index=0
num_entries=64

[board.processor.cores.core.mmu.dtb.replacement_policy]
type=LRURP
eventq_index=0

[board.processor.cores.core.mmu.dtb_walker]
type=ArmTableWalker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
power_model=
power_state=board.processor.cores.core.mmu.dtb_walker.power_state
sys=board
port=board.cache_hierarchy.dptw_caches.cpu_side

[board.processor.cores.core.mmu.dtb_walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.processor.cores.core.mmu.itb]
type=ArmTLB
children=indexing_policy replacement_policy
assoc=64
entry_type=instruction
eventq_index=0
indexing_policy=board.processor.cores.core.mmu.itb.indexing_policy
is_stage2=false
next_level=board.processor.cores.core.mmu.l2_shared
partial_levels=
replacement_policy=board.processor.cores.core.mmu.itb.replacement_policy
size=64
sys=board

[board.processor.cores.core.mmu.itb.indexing_policy]
type=TLBSetAssociative
assoc=64
eventq_index=0
num_entries=64

[board.processor.cores.core.mmu.itb.replacement_policy]
type=LRURP
eventq_index=0

[board.processor.cores.core.mmu.itb_walker]
type=ArmTableWalker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
power_model=
power_state=board.processor.cores.core.mmu.itb_walker.power_state
sys=board
port=board.cache_hierarchy.iptw_caches.cpu_side

[board.processor.cores.core.mmu.itb_walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.processor.cores.core.mmu.l2_shared]
type=ArmTLB
children=indexing_policy replacement_policy
assoc=5
entry_type=unified
eventq_index=0
indexing_policy=board.processor.cores.core.mmu.l2_shared.indexing_policy
is_stage2=false
next_level=Null
partial_levels=L2
replacement_policy=board.processor.cores.core.mmu.l2_shared.replacement_policy
size=1280
sys=board

[board.processor.cores.core.mmu.l2_shared.indexing_policy]
type=TLBSetAssociative
assoc=5
eventq_index=0
num_entries=1280

[board.processor.cores.core.mmu.l2_shared.replacement_policy]
type=LRURP
eventq_index=0

[board.processor.cores.core.mmu.stage2_dtb]
type=ArmTLB
children=indexing_policy replacement_policy
assoc=32
entry_type=data
eventq_index=0
indexing_policy=board.processor.cores.core.mmu.stage2_dtb.indexing_policy
is_stage2=true
next_level=Null
partial_levels=
replacement_policy=board.processor.cores.core.mmu.stage2_dtb.replacement_policy
size=32
sys=board

[board.processor.cores.core.mmu.stage2_dtb.indexing_policy]
type=TLBSetAssociative
assoc=32
eventq_index=0
num_entries=32

[board.processor.cores.core.mmu.stage2_dtb.replacement_policy]
type=LRURP
eventq_index=0

[board.processor.cores.core.mmu.stage2_dtb_walker]
type=ArmTableWalker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
power_model=
power_state=board.processor.cores.core.mmu.stage2_dtb_walker.power_state
sys=board

[board.processor.cores.core.mmu.stage2_dtb_walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.processor.cores.core.mmu.stage2_itb]
type=ArmTLB
children=indexing_policy replacement_policy
assoc=32
entry_type=instruction
eventq_index=0
indexing_policy=board.processor.cores.core.mmu.stage2_itb.indexing_policy
is_stage2=true
next_level=Null
partial_levels=
replacement_policy=board.processor.cores.core.mmu.stage2_itb.replacement_policy
size=32
sys=board

[board.processor.cores.core.mmu.stage2_itb.indexing_policy]
type=TLBSetAssociative
assoc=32
eventq_index=0
num_entries=32

[board.processor.cores.core.mmu.stage2_itb.replacement_policy]
type=LRURP
eventq_index=0

[board.processor.cores.core.mmu.stage2_itb_walker]
type=ArmTableWalker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
power_model=
power_state=board.processor.cores.core.mmu.stage2_itb_walker.power_state
sys=board

[board.processor.cores.core.mmu.stage2_itb_walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.processor.cores.core.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=ON CLK_GATED OFF

[board.processor.cores.core.tracer]
type=ExeTracer
children=disassembler
disassembler=board.processor.cores.core.tracer.disassembler
eventq_index=0

[board.processor.cores.core.tracer.disassembler]
type=InstDisassembler
eventq_index=0

[board.processor.cores.core.workload]
type=Process
cmd=gem5/arm-hello64-static
cwd=learn-you-a-gem5
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/gem5/arm-hello64-static
gid=100
input=cin
kvmInSE=false
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=0
release=5.1.0
simpoint=0
system=board
uid=100
useArchPT=false
zeroPages=true

[board.workload]
type=ArmEmuLinux
eventq_index=0
remote_gdb_port=#7000
wait_for_remote_gdb=false

[root]
type=Root
children=board
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000