[board]
type=System
children=cache_hierarchy clk_domain dvfs_handler memory processor workload
auto_unlink_shared_backstore=false
cache_line_size=64
eventq_index=0
exit_on_work_items=true
external_memory_ranges=
init_param=0
m5ops_base=4294901760
mem_mode=timing
mem_ranges=2147483648:5368709120
memories=board.memory.mem_ctrl.dram
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
readfile=
redirect_paths=
shadow_rom_ranges=
shared_backstore=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
workload=board.workload
system_port=board.cache_hierarchy.membus.cpu_side_ports[0]

[board.cache_hierarchy]
type=SubSystem
children=dptw_caches iptw_caches l1dcaches l1icaches l2bus l2cache membus
eventq_index=0
thermal_domain=Null

[board.cache_hierarchy.dptw_caches]
type=Cache
children=power_state replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=20
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.dptw_caches.power_state
prefetcher=Null
replace_expansions=true
replacement_policy=board.cache_hierarchy.dptw_caches.replacement_policy
response_latency=1
sequential_access=false
size=8192
system=board
tag_latency=1
tags=board.cache_hierarchy.dptw_caches.tags
tgts_per_mshr=12
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=false
cpu_side=board.processor.cores.core.mmu.dtb.walker.port
mem_side=board.cache_hierarchy.l2bus.cpu_side_ports[3]

[board.cache_hierarchy.dptw_caches.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.dptw_caches.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.dptw_caches.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=4
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.dptw_caches.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.dptw_caches.tags.power_state
replacement_policy=board.cache_hierarchy.dptw_caches.replacement_policy
sequential_access=false
size=8192
system=board
tag_latency=1
warmup_percentage=0

[board.cache_hierarchy.dptw_caches.tags.indexing_policy]
type=TaggedSetAssociative
assoc=4
entry_size=64
eventq_index=0
size=8192

[board.cache_hierarchy.dptw_caches.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.iptw_caches]
type=Cache
children=power_state replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=20
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.iptw_caches.power_state
prefetcher=Null
replace_expansions=true
replacement_policy=board.cache_hierarchy.iptw_caches.replacement_policy
response_latency=1
sequential_access=false
size=8192
system=board
tag_latency=1
tags=board.cache_hierarchy.iptw_caches.tags
tgts_per_mshr=12
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=false
cpu_side=board.processor.cores.core.mmu.itb.walker.port
mem_side=board.cache_hierarchy.l2bus.cpu_side_ports[2]

[board.cache_hierarchy.iptw_caches.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.iptw_caches.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.iptw_caches.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=4
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.iptw_caches.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.iptw_caches.tags.power_state
replacement_policy=board.cache_hierarchy.iptw_caches.replacement_policy
sequential_access=false
size=8192
system=board
tag_latency=1
warmup_percentage=0

[board.cache_hierarchy.iptw_caches.tags.indexing_policy]
type=TaggedSetAssociative
assoc=4
entry_size=64
eventq_index=0
size=8192

[board.cache_hierarchy.iptw_caches.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1dcaches]
type=Cache
children=power_state prefetcher replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=16
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1dcaches.power_state
prefetcher=board.cache_hierarchy.l1dcaches.prefetcher
replace_expansions=true
replacement_policy=board.cache_hierarchy.l1dcaches.replacement_policy
response_latency=1
sequential_access=false
size=16384
system=board
tag_latency=1
tags=board.cache_hierarchy.l1dcaches.tags
tgts_per_mshr=20
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=false
cpu_side=board.processor.cores.core.dcache_port
mem_side=board.cache_hierarchy.l2bus.cpu_side_ports[1]

[board.cache_hierarchy.l1dcaches.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1dcaches.prefetcher]
type=StridePrefetcher
children=power_state table_indexing_policy table_replacement_policy
block_size=64
cache_snoop=false
clk_domain=board.clk_domain
confidence_counter_bits=3
confidence_threshold=50
degree=4
distance=0
eventq_index=0
initial_confidence=4
latency=1
max_prefetch_requests_with_pending_translation=32
on_data=true
on_inst=false
on_miss=false
on_read=true
on_write=true
page_bytes=4096
power_model=
power_state=board.cache_hierarchy.l1dcaches.prefetcher.power_state
prefetch_on_access=false
prefetch_on_pf_hit=true
queue_filter=true
queue_size=32
queue_squash=true
sys=board
table_assoc=4
table_entries=64
table_indexing_policy=board.cache_hierarchy.l1dcaches.prefetcher.table_indexing_policy
table_replacement_policy=board.cache_hierarchy.l1dcaches.prefetcher.table_replacement_policy
tag_prefetch=true
throttle_control_percentage=0
use_cache_line_address=true
use_requestor_id=true
use_virtual_addresses=false

[board.cache_hierarchy.l1dcaches.prefetcher.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1dcaches.prefetcher.table_indexing_policy]
type=StridePrefetcherHashedSetAssociative
assoc=4
entry_size=1
eventq_index=0
size=64

[board.cache_hierarchy.l1dcaches.prefetcher.table_replacement_policy]
type=RandomRP
eventq_index=0

[board.cache_hierarchy.l1dcaches.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.l1dcaches.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=8
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.l1dcaches.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1dcaches.tags.power_state
replacement_policy=board.cache_hierarchy.l1dcaches.replacement_policy
sequential_access=false
size=16384
system=board
tag_latency=1
warmup_percentage=0

[board.cache_hierarchy.l1dcaches.tags.indexing_policy]
type=TaggedSetAssociative
assoc=8
entry_size=64
eventq_index=0
size=16384

[board.cache_hierarchy.l1dcaches.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1icaches]
type=Cache
children=power_state prefetcher replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=1
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=16
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1icaches.power_state
prefetcher=board.cache_hierarchy.l1icaches.prefetcher
replace_expansions=true
replacement_policy=board.cache_hierarchy.l1icaches.replacement_policy
response_latency=1
sequential_access=false
size=16384
system=board
tag_latency=1
tags=board.cache_hierarchy.l1icaches.tags
tgts_per_mshr=20
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=false
cpu_side=board.processor.cores.core.icache_port
mem_side=board.cache_hierarchy.l2bus.cpu_side_ports[0]

[board.cache_hierarchy.l1icaches.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1icaches.prefetcher]
type=StridePrefetcher
children=power_state table_indexing_policy table_replacement_policy
block_size=64
cache_snoop=false
clk_domain=board.clk_domain
confidence_counter_bits=3
confidence_threshold=50
degree=4
distance=0
eventq_index=0
initial_confidence=4
latency=1
max_prefetch_requests_with_pending_translation=32
on_data=true
on_inst=false
on_miss=false
on_read=true
on_write=true
page_bytes=4096
power_model=
power_state=board.cache_hierarchy.l1icaches.prefetcher.power_state
prefetch_on_access=false
prefetch_on_pf_hit=true
queue_filter=true
queue_size=32
queue_squash=true
sys=board
table_assoc=4
table_entries=64
table_indexing_policy=board.cache_hierarchy.l1icaches.prefetcher.table_indexing_policy
table_replacement_policy=board.cache_hierarchy.l1icaches.prefetcher.table_replacement_policy
tag_prefetch=true
throttle_control_percentage=0
use_cache_line_address=true
use_requestor_id=true
use_virtual_addresses=false

[board.cache_hierarchy.l1icaches.prefetcher.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l1icaches.prefetcher.table_indexing_policy]
type=StridePrefetcherHashedSetAssociative
assoc=4
entry_size=1
eventq_index=0
size=64

[board.cache_hierarchy.l1icaches.prefetcher.table_replacement_policy]
type=RandomRP
eventq_index=0

[board.cache_hierarchy.l1icaches.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.l1icaches.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=8
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.l1icaches.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l1icaches.tags.power_state
replacement_policy=board.cache_hierarchy.l1icaches.replacement_policy
sequential_access=false
size=16384
system=board
tag_latency=1
warmup_percentage=0

[board.cache_hierarchy.l1icaches.tags.indexing_policy]
type=TaggedSetAssociative
assoc=8
entry_size=64
eventq_index=0
size=16384

[board.cache_hierarchy.l1icaches.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l2bus]
type=CoherentXBar
children=power_state snoop_filter
clk_domain=board.clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
header_latency=1
max_outstanding_snoops=512
max_routing_table_size=512
point_of_coherency=false
point_of_unification=true
power_model=
power_state=board.cache_hierarchy.l2bus.power_state
response_latency=1
snoop_filter=board.cache_hierarchy.l2bus.snoop_filter
snoop_response_latency=1
system=board
use_default_range=false
width=32
cpu_side_ports=board.cache_hierarchy.l1icaches.mem_side board.cache_hierarchy.l1dcaches.mem_side board.cache_hierarchy.iptw_caches.mem_side board.cache_hierarchy.dptw_caches.mem_side
mem_side_ports=board.cache_hierarchy.l2cache.cpu_side

[board.cache_hierarchy.l2bus.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l2bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=board

[board.cache_hierarchy.l2cache]
type=Cache
children=power_state prefetcher replacement_policy tags
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=board.clk_domain
clusivity=mostly_incl
compressor=Null
data_latency=10
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
move_contractions=true
mshrs=20
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l2cache.power_state
prefetcher=board.cache_hierarchy.l2cache.prefetcher
replace_expansions=true
replacement_policy=board.cache_hierarchy.l2cache.replacement_policy
response_latency=1
sequential_access=false
size=262144
system=board
tag_latency=10
tags=board.cache_hierarchy.l2cache.tags
tgts_per_mshr=12
warmup_percentage=0
write_allocator=Null
write_buffers=8
writeback_clean=false
cpu_side=board.cache_hierarchy.l2bus.mem_side_ports[0]
mem_side=board.cache_hierarchy.membus.cpu_side_ports[1]

[board.cache_hierarchy.l2cache.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l2cache.prefetcher]
type=StridePrefetcher
children=power_state table_indexing_policy table_replacement_policy
block_size=64
cache_snoop=false
clk_domain=board.clk_domain
confidence_counter_bits=3
confidence_threshold=50
degree=4
distance=0
eventq_index=0
initial_confidence=4
latency=1
max_prefetch_requests_with_pending_translation=32
on_data=true
on_inst=false
on_miss=false
on_read=true
on_write=true
page_bytes=4096
power_model=
power_state=board.cache_hierarchy.l2cache.prefetcher.power_state
prefetch_on_access=false
prefetch_on_pf_hit=true
queue_filter=true
queue_size=32
queue_squash=true
sys=board
table_assoc=4
table_entries=64
table_indexing_policy=board.cache_hierarchy.l2cache.prefetcher.table_indexing_policy
table_replacement_policy=board.cache_hierarchy.l2cache.prefetcher.table_replacement_policy
tag_prefetch=true
throttle_control_percentage=0
use_cache_line_address=true
use_requestor_id=true
use_virtual_addresses=false

[board.cache_hierarchy.l2cache.prefetcher.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.l2cache.prefetcher.table_indexing_policy]
type=StridePrefetcherHashedSetAssociative
assoc=4
entry_size=1
eventq_index=0
size=64

[board.cache_hierarchy.l2cache.prefetcher.table_replacement_policy]
type=RandomRP
eventq_index=0

[board.cache_hierarchy.l2cache.replacement_policy]
type=LRURP
eventq_index=0

[board.cache_hierarchy.l2cache.tags]
type=BaseSetAssoc
children=indexing_policy power_state
assoc=16
block_size=64
clk_domain=board.clk_domain
entry_size=64
eventq_index=0
indexing_policy=board.cache_hierarchy.l2cache.tags.indexing_policy
partitioning_manager=Null
power_model=
power_state=board.cache_hierarchy.l2cache.tags.power_state
replacement_policy=board.cache_hierarchy.l2cache.replacement_policy
sequential_access=false
size=262144
system=board
tag_latency=10
warmup_percentage=0

[board.cache_hierarchy.l2cache.tags.indexing_policy]
type=TaggedSetAssociative
assoc=16
entry_size=64
eventq_index=0
size=262144

[board.cache_hierarchy.l2cache.tags.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.membus]
type=CoherentXBar
children=badaddr_responder power_state snoop_filter
clk_domain=board.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
header_latency=1
max_outstanding_snoops=512
max_routing_table_size=512
point_of_coherency=true
point_of_unification=true
power_model=
power_state=board.cache_hierarchy.membus.power_state
response_latency=2
snoop_filter=board.cache_hierarchy.membus.snoop_filter
snoop_response_latency=4
system=board
use_default_range=false
width=64
cpu_side_ports=board.system_port board.cache_hierarchy.l2cache.mem_side
default=board.cache_hierarchy.membus.badaddr_responder.pio
mem_side_ports=board.memory.mem_ctrl.port

[board.cache_hierarchy.membus.badaddr_responder]
type=IsaFake
children=power_state
clk_domain=board.clk_domain
eventq_index=0
fake_mem=false
pio_addr=0
pio_latency=100000
pio_size=8
power_model=
power_state=board.cache_hierarchy.membus.badaddr_responder.power_state
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=board
update_data=false
warn_access=
pio=board.cache_hierarchy.membus.default

[board.cache_hierarchy.membus.badaddr_responder.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.membus.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.cache_hierarchy.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=board

[board.clk_domain]
type=SrcClockDomain
children=voltage_domain
clock=333
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=board.clk_domain.voltage_domain

[board.clk_domain.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0

[board.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=board.clk_domain
transition_latency=100000000

[board.memory]
type=SubSystem
children=mem_ctrl
eventq_index=0
thermal_domain=Null

[board.memory.mem_ctrl]
type=MemCtrl
children=dram power_state
clk_domain=board.clk_domain
command_window=10000
disable_sanity_check=false
dram=board.memory.mem_ctrl.dram
eventq_index=0
mem_sched_policy=frfcfs
min_reads_per_switch=16
min_writes_per_switch=16
power_model=
power_state=board.memory.mem_ctrl.power_state
qos_policy=Null
qos_priorities=1
qos_priority_escalation=false
qos_q_policy=fifo
qos_requestors=               
qos_syncro_scheduler=false
qos_turnaround_policy=Null
static_backend_latency=10000
static_frontend_latency=10000
system=board
write_high_thresh_perc=85
write_low_thresh_perc=50
port=board.cache_hierarchy.membus.mem_side_ports[0]

[board.memory.mem_ctrl.dram]
type=DRAMInterface
children=power_state
IDD0=0.048
IDD02=0.003
IDD2N=0.034
IDD2N2=0.0
IDD2P0=0.0
IDD2P02=0.0
IDD2P1=0.025
IDD2P12=0.0
IDD3N=0.043000000000000003
IDD3N2=0.003
IDD3P0=0.0
IDD3P02=0.0
IDD3P1=0.037
IDD3P12=0.0
IDD4R=0.135
IDD4R2=0.0
IDD4W=0.123
IDD4W2=0.0
IDD5=0.25
IDD52=0.0
IDD6=0.03
IDD62=0.0
VDD=1.2
VDD2=2.5
activation_limit=4
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=4
banks_per_rank=16
beats_per_clock=2
burst_length=8
clk_domain=board.clk_domain
collect_stats=true
conf_table_reported=true
data_clock_sync=false
device_bus_width=8
device_rowbuffer_size=1024
device_size=1073741824
devices_per_rank=8
dll=true
enable_dram_powerdown=false
eventq_index=0
image_file=
in_addr_map=true
kvm_map=true
max_accesses_per_row=16
null=false
page_policy=open_adaptive
power_model=
power_state=board.memory.mem_ctrl.dram.power_state
range=2147483648:5368709120
ranks_per_channel=2
read_buffer_size=64
tAAD=833
tBURST=3332
tBURST_MAX=3332
tBURST_MIN=3332
tCCD_L=5000
tCCD_L_WR=5000
tCK=833
tCL=14160
tCS=1666
tCWL=14160
tPPD=0
tRAS=32000
tRCD=14160
tRCD_WR=14160
tREFI=7800000
tRFC=350000
tRP=14160
tRRD=3332
tRRD_L=4900
tRTP=7500
tRTW=1666
tWR=15000
tWTR=5000
tWTR_L=5000
tXAW=21000
tXP=6000
tXPDLL=0
tXS=340000
tXSDLL=0
two_cycle_activate=false
write_buffer_size=128
writeable=true

[board.memory.mem_ctrl.dram.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.memory.mem_ctrl.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.processor]
type=SubSystem
children=cores
eventq_index=0
thermal_domain=Null

[board.processor.cores]
type=SubSystem
children=core
eventq_index=0
thermal_domain=Null

[board.processor.cores.core]
type=BaseMinorCPU
children=branchPred decoder executeFuncUnits interrupts isa mmu power_state tracer workload
branchPred=board.processor.cores.core.branchPred
checker=Null
clk_domain=board.clk_domain
cpu_id=-1
decodeCycleInput=true
decodeInputBufferSize=3
decodeInputWidth=2
decodeToExecuteForwardDelay=1
decoder=board.processor.cores.core.decoder
do_checkpoint_insts=true
do_statistics_insts=true
enableIdling=true
eventq_index=0
executeAllowEarlyMemoryIssue=true
executeBranchDelay=1
executeCommitLimit=2
executeCycleInput=true
executeFuncUnits=board.processor.cores.core.executeFuncUnits
executeInputBufferSize=7
executeInputWidth=2
executeIssueLimit=2
executeLSQMaxStoreBufferStoresPerCycle=2
executeLSQRequestsQueueSize=1
executeLSQStoreBufferSize=5
executeLSQTransfersQueueSize=2
executeMaxAccessesInMemory=2
executeMemoryCommitLimit=1
executeMemoryIssueLimit=1
executeMemoryWidth=0
executeSetTraceTimeOnCommit=true
executeSetTraceTimeOnIssue=false
fetch1FetchLimit=1
fetch1LineSnapWidth=0
fetch1LineWidth=0
fetch1ToFetch2BackwardDelay=1
fetch1ToFetch2ForwardDelay=1
fetch2CycleInput=true
fetch2InputBufferSize=2
fetch2ToDecodeForwardDelay=1
function_trace=false
function_trace_start=0
interrupts=board.processor.cores.core.interrupts
isa=board.processor.cores.core.isa
max_insts_all_threads=0
max_insts_any_thread=0
mmu=board.processor.cores.core.mmu
numThreads=1
power_gating_on_idle=false
power_model=
power_state=board.processor.cores.core.power_state
progress_interval=0
pwr_gating_latency=300
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=board
threadPolicy=RoundRobin
tracer=board.processor.cores.core.tracer
workload=board.processor.cores.core.workload
dcache_port=board.cache_hierarchy.l1dcaches.cpu_side
icache_port=board.cache_hierarchy.l1icaches.cpu_side

[board.processor.cores.core.branchPred]
type=LocalBP
children=btb indirectBranchPred ras
btb=board.processor.cores.core.branchPred.btb
eventq_index=0
indirectBranchPred=board.processor.cores.core.branchPred.indirectBranchPred
instShiftAmt=0
localCtrBits=2
localPredictorSize=2048
numThreads=1
ras=board.processor.cores.core.branchPred.ras
requiresBTBHit=false
speculativeHistUpdate=true
takenOnlyHistory=false

[board.processor.cores.core.branchPred.btb]
type=SimpleBTB
children=btbIndexingPolicy btbReplPolicy power_state
associativity=1
btbIndexingPolicy=board.processor.cores.core.branchPred.btb.btbIndexingPolicy
btbReplPolicy=board.processor.cores.core.branchPred.btb.btbReplPolicy
clk_domain=board.clk_domain
eventq_index=0
instShiftAmt=0
numEntries=4096
numThreads=1
power_model=
power_state=board.processor.cores.core.branchPred.btb.power_state
tagBits=16

[board.processor.cores.core.branchPred.btb.btbIndexingPolicy]
type=BTBSetAssociative
assoc=1
eventq_index=0
numThreads=1
num_entries=4096
set_shift=0
tag_bits=64

[board.processor.cores.core.branchPred.btb.btbReplPolicy]
type=LRURP
eventq_index=0

[board.processor.cores.core.branchPred.btb.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.processor.cores.core.branchPred.indirectBranchPred]
type=SimpleIndirectPredictor
eventq_index=0
indirectGHRBits=13
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=0
numThreads=1
speculativePathLength=256

[board.processor.cores.core.branchPred.ras]
type=ReturnAddrStack
eventq_index=0
numEntries=16
numThreads=1

[board.processor.cores.core.decoder]
type=RiscvDecoder
eventq_index=0
isa=board.processor.cores.core.isa

[board.processor.cores.core.executeFuncUnits]
type=MinorFUPool
children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 funcUnits7
eventq_index=0
funcUnits=board.processor.cores.core.executeFuncUnits.funcUnits0 board.processor.cores.core.executeFuncUnits.funcUnits1 board.processor.cores.core.executeFuncUnits.funcUnits2 board.processor.cores.core.executeFuncUnits.funcUnits3 board.processor.cores.core.executeFuncUnits.funcUnits4 board.processor.cores.core.executeFuncUnits.funcUnits5 board.processor.cores.core.executeFuncUnits.funcUnits6 board.processor.cores.core.executeFuncUnits.funcUnits7

[board.processor.cores.core.executeFuncUnits.funcUnits0]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits0.opClasses
opLat=3
timings=board.processor.cores.core.executeFuncUnits.funcUnits0.timings

[board.processor.cores.core.executeFuncUnits.funcUnits0.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits0.opClasses.opClasses

[board.processor.cores.core.executeFuncUnits.funcUnits0.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu

[board.processor.cores.core.executeFuncUnits.funcUnits0.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits0.timings.opClasses
srcRegsRelativeLats=2
suppress=false

[board.processor.cores.core.executeFuncUnits.funcUnits0.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=

[board.processor.cores.core.executeFuncUnits.funcUnits1]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits1.opClasses
opLat=3
timings=board.processor.cores.core.executeFuncUnits.funcUnits1.timings

[board.processor.cores.core.executeFuncUnits.funcUnits1.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits1.opClasses.opClasses

[board.processor.cores.core.executeFuncUnits.funcUnits1.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntAlu

[board.processor.cores.core.executeFuncUnits.funcUnits1.timings]
type=MinorFUTiming
children=opClasses
description=Int
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits1.timings.opClasses
srcRegsRelativeLats=2
suppress=false

[board.processor.cores.core.executeFuncUnits.funcUnits1.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=

[board.processor.cores.core.executeFuncUnits.funcUnits2]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits2.opClasses
opLat=3
timings=board.processor.cores.core.executeFuncUnits.funcUnits2.timings

[board.processor.cores.core.executeFuncUnits.funcUnits2.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits2.opClasses.opClasses

[board.processor.cores.core.executeFuncUnits.funcUnits2.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntMult

[board.processor.cores.core.executeFuncUnits.funcUnits2.timings]
type=MinorFUTiming
children=opClasses
description=Mul
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits2.timings.opClasses
srcRegsRelativeLats=0
suppress=false

[board.processor.cores.core.executeFuncUnits.funcUnits2.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=

[board.processor.cores.core.executeFuncUnits.funcUnits3]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=9
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits3.opClasses
opLat=9
timings=

[board.processor.cores.core.executeFuncUnits.funcUnits3.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits3.opClasses.opClasses

[board.processor.cores.core.executeFuncUnits.funcUnits3.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=IntDiv

[board.processor.cores.core.executeFuncUnits.funcUnits4]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses
opLat=6
timings=board.processor.cores.core.executeFuncUnits.funcUnits4.timings

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses]
type=MinorOpClassSet
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 opClasses28 opClasses29 opClasses30 opClasses31 opClasses32 opClasses33 opClasses34 opClasses35 opClasses36 opClasses37 opClasses38 opClasses39 opClasses40 opClasses41 opClasses42 opClasses43 opClasses44 opClasses45 opClasses46 opClasses47 opClasses48 opClasses49 opClasses50
eventq_index=0
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses00 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses01 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses02 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses03 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses04 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses05 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses06 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses07 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses08 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses09 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses10 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses11 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses12 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses13 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses14 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses15 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses16 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses17 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses18 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses19 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses20 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses21 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses22 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses23 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses24 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses25 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses26 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses27 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses28 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses29 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses30 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses31 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses32 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses33 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses34 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses35 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses36 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses37 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses38 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses39 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses40 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses41 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses42 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses43 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses44 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses45 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses46 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses47 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses48 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses49 board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses50

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses00]
type=MinorOpClass
eventq_index=0
opClass=FloatAdd

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses01]
type=MinorOpClass
eventq_index=0
opClass=FloatCmp

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses02]
type=MinorOpClass
eventq_index=0
opClass=FloatCvt

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
opClass=FloatMisc

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
opClass=FloatMult

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
opClass=FloatMultAcc

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
opClass=FloatDiv

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
opClass=FloatSqrt

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
opClass=SimdAdd

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
opClass=SimdAddAcc

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
opClass=SimdAlu

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
opClass=SimdCmp

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
opClass=SimdCvt

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
opClass=SimdMisc

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
opClass=SimdMult

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses15]
type=MinorOpClass
eventq_index=0
opClass=SimdMultAcc

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses16]
type=MinorOpClass
eventq_index=0
opClass=SimdMatMultAcc

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses17]
type=MinorOpClass
eventq_index=0
opClass=SimdShift

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses18]
type=MinorOpClass
eventq_index=0
opClass=SimdShiftAcc

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses19]
type=MinorOpClass
eventq_index=0
opClass=SimdDiv

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses20]
type=MinorOpClass
eventq_index=0
opClass=SimdSqrt

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses21]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAdd

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses22]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatAlu

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses23]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCmp

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses24]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCvt

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses25]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatDiv

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses26]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMisc

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses27]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMult

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses28]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMultAcc

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses29]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatMatMultAcc

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses30]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatSqrt

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses31]
type=MinorOpClass
eventq_index=0
opClass=SimdReduceAdd

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses32]
type=MinorOpClass
eventq_index=0
opClass=SimdReduceAlu

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses33]
type=MinorOpClass
eventq_index=0
opClass=SimdReduceCmp

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses34]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatReduceAdd

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses35]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatReduceCmp

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses36]
type=MinorOpClass
eventq_index=0
opClass=SimdAes

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses37]
type=MinorOpClass
eventq_index=0
opClass=SimdAesMix

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses38]
type=MinorOpClass
eventq_index=0
opClass=SimdSha1Hash

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses39]
type=MinorOpClass
eventq_index=0
opClass=SimdSha1Hash2

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses40]
type=MinorOpClass
eventq_index=0
opClass=SimdSha256Hash

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses41]
type=MinorOpClass
eventq_index=0
opClass=SimdSha256Hash2

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses42]
type=MinorOpClass
eventq_index=0
opClass=SimdShaSigma2

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses43]
type=MinorOpClass
eventq_index=0
opClass=SimdShaSigma3

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses44]
type=MinorOpClass
eventq_index=0
opClass=Matrix

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses45]
type=MinorOpClass
eventq_index=0
opClass=MatrixMov

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses46]
type=MinorOpClass
eventq_index=0
opClass=MatrixOP

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses47]
type=MinorOpClass
eventq_index=0
opClass=SimdExt

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses48]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatExt

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses49]
type=MinorOpClass
eventq_index=0
opClass=SimdFloatCvt

[board.processor.cores.core.executeFuncUnits.funcUnits4.opClasses.opClasses50]
type=MinorOpClass
eventq_index=0
opClass=SimdConfig

[board.processor.cores.core.executeFuncUnits.funcUnits4.timings]
type=MinorFUTiming
children=opClasses
description=FloatSimd
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits4.timings.opClasses
srcRegsRelativeLats=2
suppress=false

[board.processor.cores.core.executeFuncUnits.funcUnits4.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=

[board.processor.cores.core.executeFuncUnits.funcUnits5]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits5.opClasses
opLat=3
timings=board.processor.cores.core.executeFuncUnits.funcUnits5.timings

[board.processor.cores.core.executeFuncUnits.funcUnits5.opClasses]
type=MinorOpClassSet
children=opClasses
eventq_index=0
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits5.opClasses.opClasses

[board.processor.cores.core.executeFuncUnits.funcUnits5.opClasses.opClasses]
type=MinorOpClass
eventq_index=0
opClass=SimdPredAlu

[board.processor.cores.core.executeFuncUnits.funcUnits5.timings]
type=MinorFUTiming
children=opClasses
description=Pred
eventq_index=0
extraAssumedLat=0
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits5.timings.opClasses
srcRegsRelativeLats=2
suppress=false

[board.processor.cores.core.executeFuncUnits.funcUnits5.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=

[board.processor.cores.core.executeFuncUnits.funcUnits6]
type=MinorFU
children=opClasses timings
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses
opLat=1
timings=board.processor.cores.core.executeFuncUnits.funcUnits6.timings

[board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses]
type=MinorOpClassSet
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14
eventq_index=0
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses00 board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses01 board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses02 board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses03 board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses04 board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses05 board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses06 board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses07 board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses08 board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses09 board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses10 board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses11 board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses12 board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses13 board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses14

[board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses00]
type=MinorOpClass
eventq_index=0
opClass=MemRead

[board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses01]
type=MinorOpClass
eventq_index=0
opClass=MemWrite

[board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses02]
type=MinorOpClass
eventq_index=0
opClass=FloatMemRead

[board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses03]
type=MinorOpClass
eventq_index=0
opClass=FloatMemWrite

[board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses04]
type=MinorOpClass
eventq_index=0
opClass=SimdUnitStrideLoad

[board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses05]
type=MinorOpClass
eventq_index=0
opClass=SimdUnitStrideStore

[board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses06]
type=MinorOpClass
eventq_index=0
opClass=SimdUnitStrideMaskLoad

[board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses07]
type=MinorOpClass
eventq_index=0
opClass=SimdUnitStrideMaskStore

[board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses08]
type=MinorOpClass
eventq_index=0
opClass=SimdStridedLoad

[board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses09]
type=MinorOpClass
eventq_index=0
opClass=SimdStridedStore

[board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses10]
type=MinorOpClass
eventq_index=0
opClass=SimdIndexedLoad

[board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses11]
type=MinorOpClass
eventq_index=0
opClass=SimdIndexedStore

[board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses12]
type=MinorOpClass
eventq_index=0
opClass=SimdUnitStrideFaultOnlyFirstLoad

[board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses13]
type=MinorOpClass
eventq_index=0
opClass=SimdWholeRegisterLoad

[board.processor.cores.core.executeFuncUnits.funcUnits6.opClasses.opClasses14]
type=MinorOpClass
eventq_index=0
opClass=SimdWholeRegisterStore

[board.processor.cores.core.executeFuncUnits.funcUnits6.timings]
type=MinorFUTiming
children=opClasses
description=Mem
eventq_index=0
extraAssumedLat=2
extraCommitLat=0
extraCommitLatExpr=Null
mask=0
match=0
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits6.timings.opClasses
srcRegsRelativeLats=1
suppress=false

[board.processor.cores.core.executeFuncUnits.funcUnits6.timings.opClasses]
type=MinorOpClassSet
eventq_index=0
opClasses=

[board.processor.cores.core.executeFuncUnits.funcUnits7]
type=MinorFU
children=opClasses
cantForwardFromFUIndices=
eventq_index=0
issueLat=1
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits7.opClasses
opLat=1
timings=

[board.processor.cores.core.executeFuncUnits.funcUnits7.opClasses]
type=MinorOpClassSet
children=opClasses0 opClasses1
eventq_index=0
opClasses=board.processor.cores.core.executeFuncUnits.funcUnits7.opClasses.opClasses0 board.processor.cores.core.executeFuncUnits.funcUnits7.opClasses.opClasses1

[board.processor.cores.core.executeFuncUnits.funcUnits7.opClasses.opClasses0]
type=MinorOpClass
eventq_index=0
opClass=IprAccess

[board.processor.cores.core.executeFuncUnits.funcUnits7.opClasses.opClasses1]
type=MinorOpClass
eventq_index=0
opClass=InstPrefetch

[board.processor.cores.core.interrupts]
type=RiscvInterrupts
eventq_index=0
local_interrupt_ids=
nmi_cause=0

[board.processor.cores.core.isa]
type=RiscvISA
elen=64
enable_Smrnmi=false
enable_Zcd=true
enable_Zicbom_fs=true
enable_Zicboz_fs=true
enable_rvv=true
eventq_index=0
privilege_mode_set=MSU
riscv_type=RV64
vlen=256
wfi_resume_on_pending=false

[board.processor.cores.core.mmu]
type=RiscvMMU
children=dtb itb pma_checker pmp
dtb=board.processor.cores.core.mmu.dtb
eventq_index=0
itb=board.processor.cores.core.mmu.itb
pma_checker=board.processor.cores.core.mmu.pma_checker
pmp=board.processor.cores.core.mmu.pmp

[board.processor.cores.core.mmu.dtb]
type=RiscvTLB
children=walker
entry_type=data
eventq_index=0
next_level=Null
pma_checker=board.processor.cores.core.mmu.pma_checker
pmp=board.processor.cores.core.mmu.pmp
size=64
walker=board.processor.cores.core.mmu.dtb.walker

[board.processor.cores.core.mmu.dtb.walker]
type=RiscvPagetableWalker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
num_squash_per_cycle=4
pma_checker=board.processor.cores.core.mmu.pma_checker
pmp=board.processor.cores.core.mmu.pmp
power_model=
power_state=board.processor.cores.core.mmu.dtb.walker.power_state
system=board
port=board.cache_hierarchy.dptw_caches.cpu_side

[board.processor.cores.core.mmu.dtb.walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.processor.cores.core.mmu.itb]
type=RiscvTLB
children=walker
entry_type=instruction
eventq_index=0
next_level=Null
pma_checker=board.processor.cores.core.mmu.pma_checker
pmp=board.processor.cores.core.mmu.pmp
size=64
walker=board.processor.cores.core.mmu.itb.walker

[board.processor.cores.core.mmu.itb.walker]
type=RiscvPagetableWalker
children=power_state
clk_domain=board.clk_domain
eventq_index=0
num_squash_per_cycle=4
pma_checker=board.processor.cores.core.mmu.pma_checker
pmp=board.processor.cores.core.mmu.pmp
power_model=
power_state=board.processor.cores.core.mmu.itb.walker.power_state
system=board
port=board.cache_hierarchy.iptw_caches.cpu_side

[board.processor.cores.core.mmu.itb.walker.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=

[board.processor.cores.core.mmu.pma_checker]
type=PMAChecker
eventq_index=0
misaligned=
uncacheable=

[board.processor.cores.core.mmu.pmp]
type=PMP
eventq_index=0
pmp_entries=16

[board.processor.cores.core.power_state]
type=PowerState
clk_gate_bins=20
clk_gate_max=1000000000000
clk_gate_min=1000
default_state=UNDEFINED
eventq_index=0
leaders=
possible_states=ON CLK_GATED OFF

[board.processor.cores.core.tracer]
type=ExeTracer
children=disassembler
disassembler=board.processor.cores.core.tracer.disassembler
eventq_index=0

[board.processor.cores.core.tracer.disassembler]
type=InstDisassembler
eventq_index=0

[board.processor.cores.core.workload]
type=Process
cmd=/homes/iws/namiel/.cache/gem5/riscv-print-this Hello, gem5! 2
cwd=/local1/namiel/learn-you-a-gem5
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/homes/iws/namiel/.cache/gem5/riscv-print-this
gid=100
input=cin
kvmInSE=false
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=0
release=5.1.0
simpoint=0
system=board
uid=100
useArchPT=false
zeroPages=true

[board.workload]
type=RiscvEmuLinux
eventq_index=0
remote_gdb_port=#7000
wait_for_remote_gdb=false

[root]
type=Root
children=board
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000