---------- Begin Simulation Statistics ----------
simSeconds 0.002433 # Number of seconds simulated (Second)
simTicks 2432803428 # Number of ticks simulated (Tick)
finalTick 2432803428 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 42.27 # Real time elapsed on the host (Second)
hostTickRate 57552608 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3427184 # Number of bytes of host memory used (Byte)
simInsts 9115640 # Number of instructions simulated (Count)
simOps 18229832 # Number of ops (including micro ops) simulated (Count)
hostInstRate 215647 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 431260 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.demandHits::processor.cores.core.data 4048373 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.demandHits::total 4048373 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::processor.cores.core.data 4048373 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.overallHits::total 4048373 # number of overall hits (Count)
board.cache_hierarchy.l1d-cache-0.demandMisses::processor.cores.core.data 2730 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1d-cache-0.demandMisses::total 2730 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1d-cache-0.overallMisses::processor.cores.core.data 2730 # number of overall misses (Count)
board.cache_hierarchy.l1d-cache-0.overallMisses::total 2730 # number of overall misses (Count)
board.cache_hierarchy.l1d-cache-0.demandMissLatency::processor.cores.core.data 111202686 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.demandMissLatency::total 111202686 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.overallMissLatency::processor.cores.core.data 111202686 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.overallMissLatency::total 111202686 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.demandAccesses::processor.cores.core.data 4051103 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandAccesses::total 4051103 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::processor.cores.core.data 4051103 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.overallAccesses::total 4051103 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1d-cache-0.demandMissRate::processor.cores.core.data 0.000674 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.demandMissRate::total 0.000674 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.overallMissRate::processor.cores.core.data 0.000674 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.overallMissRate::total 0.000674 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.demandAvgMissLatency::processor.cores.core.data 40733.584615 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.demandAvgMissLatency::total 40733.584615 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.overallAvgMissLatency::processor.cores.core.data 40733.584615 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.overallAvgMissLatency::total 40733.584615 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1d-cache-0.writebacks::writebacks 497 # number of writebacks (Count)
board.cache_hierarchy.l1d-cache-0.writebacks::total 497 # number of writebacks (Count)
board.cache_hierarchy.l1d-cache-0.demandMshrHits::processor.cores.core.data 1473 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.demandMshrHits::total 1473 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.overallMshrHits::processor.cores.core.data 1473 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.overallMshrHits::total 1473 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.demandMshrMisses::processor.cores.core.data 1257 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.demandMshrMisses::total 1257 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.overallMshrMisses::cache_hierarchy.l1d-cache-0.prefetcher 777 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.overallMshrMisses::processor.cores.core.data 1257 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.overallMshrMisses::total 2034 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.demandMshrMissLatency::processor.cores.core.data 52078203 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.demandMshrMissLatency::total 52078203 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.overallMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 29034964 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.overallMshrMissLatency::processor.cores.core.data 52078203 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.overallMshrMissLatency::total 81113167 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.demandMshrMissRate::processor.cores.core.data 0.000310 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.demandMshrMissRate::total 0.000310 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.overallMshrMissRate::cache_hierarchy.l1d-cache-0.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.overallMshrMissRate::processor.cores.core.data 0.000310 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.overallMshrMissRate::total 0.000502 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.demandAvgMshrMissLatency::processor.cores.core.data 41430.551313 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.demandAvgMshrMissLatency::total 41430.551313 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.overallAvgMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 37368.036036 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.overallAvgMshrMissLatency::processor.cores.core.data 41430.551313 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.overallAvgMshrMissLatency::total 39878.646509 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.replacements 1523 # number of replacements (Count)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMisses::cache_hierarchy.l1d-cache-0.prefetcher 777 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMisses::total 777 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 29034964 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMissLatency::total 29034964 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMissRate::cache_hierarchy.l1d-cache-0.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 37368.036036 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.HardPFReq.avgMshrMissLatency::total 37368.036036 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.hits::processor.cores.core.data 10 # number of LockedRMWReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.hits::total 10 # number of LockedRMWReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.misses::processor.cores.core.data 2 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.misses::total 2 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.missLatency::processor.cores.core.data 64935 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.missLatency::total 64935 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.accesses::processor.cores.core.data 12 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.accesses::total 12 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.missRate::processor.cores.core.data 0.166667 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.missRate::total 0.166667 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.avgMissLatency::processor.cores.core.data 32467.500000 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.avgMissLatency::total 32467.500000 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.mshrMisses::processor.cores.core.data 2 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.mshrMisses::total 2 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.mshrMissLatency::processor.cores.core.data 155178 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.mshrMissLatency::total 155178 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.mshrMissRate::processor.cores.core.data 0.166667 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.mshrMissRate::total 0.166667 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.avgMshrMissLatency::processor.cores.core.data 77589 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.LockedRMWReadReq.avgMshrMissLatency::total 77589 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.LockedRMWWriteReq.hits::processor.cores.core.data 12 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWWriteReq.hits::total 12 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWWriteReq.accesses::processor.cores.core.data 12 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.LockedRMWWriteReq.accesses::total 12 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::processor.cores.core.data 2031723 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.hits::total 2031723 # number of ReadReq hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.misses::processor.cores.core.data 2475 # number of ReadReq misses (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.misses::total 2475 # number of ReadReq misses (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.missLatency::processor.cores.core.data 99447120 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.ReadReq.missLatency::total 99447120 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::processor.cores.core.data 2034198 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.accesses::total 2034198 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.missRate::processor.cores.core.data 0.001217 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.ReadReq.missRate::total 0.001217 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.ReadReq.avgMissLatency::processor.cores.core.data 40180.654545 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.ReadReq.avgMissLatency::total 40180.654545 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrHits::processor.cores.core.data 1460 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrHits::total 1460 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMisses::processor.cores.core.data 1015 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMisses::total 1015 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMissLatency::processor.cores.core.data 40646313 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMissLatency::total 40646313 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMissRate::processor.cores.core.data 0.000499 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.ReadReq.mshrMissRate::total 0.000499 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.ReadReq.avgMshrMissLatency::processor.cores.core.data 40045.628571 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.ReadReq.avgMshrMissLatency::total 40045.628571 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::processor.cores.core.data 2016650 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.hits::total 2016650 # number of WriteReq hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.misses::processor.cores.core.data 255 # number of WriteReq misses (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.misses::total 255 # number of WriteReq misses (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.missLatency::processor.cores.core.data 11755566 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.WriteReq.missLatency::total 11755566 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::processor.cores.core.data 2016905 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.accesses::total 2016905 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.missRate::processor.cores.core.data 0.000126 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.WriteReq.missRate::total 0.000126 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.WriteReq.avgMissLatency::processor.cores.core.data 46100.258824 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.WriteReq.avgMissLatency::total 46100.258824 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrHits::processor.cores.core.data 13 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrHits::total 13 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrMisses::processor.cores.core.data 242 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrMisses::total 242 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrMissLatency::processor.cores.core.data 11431890 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrMissLatency::total 11431890 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrMissRate::processor.cores.core.data 0.000120 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.WriteReq.mshrMissRate::total 0.000120 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1d-cache-0.WriteReq.avgMshrMissLatency::processor.cores.core.data 47239.214876 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.WriteReq.avgMshrMissLatency::total 47239.214876 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.prefetcher.demandMshrMisses 1257 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIssued 2318 # number of hwpf issued (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUnused 290 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUseful 381 # number of useful prefetch (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.accuracy 0.164366 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.coverage 0.232601 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInCache 726 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInMSHR 815 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfLate 1541 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfIdentified 2761 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfBufferHit 347 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedDemand 21 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfSpanPage 471 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.pfUsefulSpanPage 101 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1d-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1d-cache-0.tags.tagsInUse 508.027091 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1d-cache-0.tags.totalRefs 4050431 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.sampledRefs 2035 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1d-cache-0.tags.avgRefs 1990.383784 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1d-cache-0.tags.warmupTick 133866 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1d-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 198.304762 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupancies::processor.cores.core.data 309.722329 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.387314 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::processor.cores.core.data 0.604926 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.avgOccs::total 0.992240 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1022 186 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.occupanciesTaskId::1024 326 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1022::3 186 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::0 52 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ageTaskId_1024::3 274 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1022 0.363281 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.ratioOccsTaskId::1024 0.636719 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1d-cache-0.tags.tagAccesses 32411051 # Number of tag accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.dataAccesses 32411051 # Number of data accesses (Count)
board.cache_hierarchy.l1d-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.demandHits::processor.cores.core.inst 24912 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1i-cache-0.demandHits::total 24912 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1i-cache-0.overallHits::processor.cores.core.inst 24912 # number of overall hits (Count)
board.cache_hierarchy.l1i-cache-0.overallHits::total 24912 # number of overall hits (Count)
board.cache_hierarchy.l1i-cache-0.demandMisses::processor.cores.core.inst 1956 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1i-cache-0.demandMisses::total 1956 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1i-cache-0.overallMisses::processor.cores.core.inst 1956 # number of overall misses (Count)
board.cache_hierarchy.l1i-cache-0.overallMisses::total 1956 # number of overall misses (Count)
board.cache_hierarchy.l1i-cache-0.demandMissLatency::processor.cores.core.inst 90661248 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.demandMissLatency::total 90661248 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.overallMissLatency::processor.cores.core.inst 90661248 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.overallMissLatency::total 90661248 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.demandAccesses::processor.cores.core.inst 26868 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.demandAccesses::total 26868 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::processor.cores.core.inst 26868 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.overallAccesses::total 26868 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1i-cache-0.demandMissRate::processor.cores.core.inst 0.072800 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.demandMissRate::total 0.072800 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.overallMissRate::processor.cores.core.inst 0.072800 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.overallMissRate::total 0.072800 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.demandAvgMissLatency::processor.cores.core.inst 46350.331288 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.demandAvgMissLatency::total 46350.331288 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.overallAvgMissLatency::processor.cores.core.inst 46350.331288 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.overallAvgMissLatency::total 46350.331288 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1i-cache-0.writebacks::writebacks 929 # number of writebacks (Count)
board.cache_hierarchy.l1i-cache-0.writebacks::total 929 # number of writebacks (Count)
board.cache_hierarchy.l1i-cache-0.demandMshrHits::processor.cores.core.inst 513 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.demandMshrHits::total 513 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.overallMshrHits::processor.cores.core.inst 513 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.overallMshrHits::total 513 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.demandMshrMisses::processor.cores.core.inst 1443 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.demandMshrMisses::total 1443 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.overallMshrMisses::processor.cores.core.inst 1443 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.overallMshrMisses::total 1443 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.demandMshrMissLatency::processor.cores.core.inst 70276653 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.demandMshrMissLatency::total 70276653 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.overallMshrMissLatency::processor.cores.core.inst 70276653 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.overallMshrMissLatency::total 70276653 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.demandMshrMissRate::processor.cores.core.inst 0.053707 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.demandMshrMissRate::total 0.053707 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.overallMshrMissRate::processor.cores.core.inst 0.053707 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.overallMshrMissRate::total 0.053707 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.demandAvgMshrMissLatency::processor.cores.core.inst 48701.769231 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.demandAvgMshrMissLatency::total 48701.769231 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.overallAvgMshrMissLatency::processor.cores.core.inst 48701.769231 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.overallAvgMshrMissLatency::total 48701.769231 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.replacements 929 # number of replacements (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.hits::processor.cores.core.inst 24912 # number of ReadReq hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.hits::total 24912 # number of ReadReq hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.misses::processor.cores.core.inst 1956 # number of ReadReq misses (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.misses::total 1956 # number of ReadReq misses (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.missLatency::processor.cores.core.inst 90661248 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.ReadReq.missLatency::total 90661248 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::processor.cores.core.inst 26868 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.accesses::total 26868 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.missRate::processor.cores.core.inst 0.072800 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.ReadReq.missRate::total 0.072800 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.ReadReq.avgMissLatency::processor.cores.core.inst 46350.331288 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.ReadReq.avgMissLatency::total 46350.331288 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrHits::processor.cores.core.inst 513 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrHits::total 513 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMisses::processor.cores.core.inst 1443 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMisses::total 1443 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMissLatency::processor.cores.core.inst 70276653 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMissLatency::total 70276653 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMissRate::processor.cores.core.inst 0.053707 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.ReadReq.mshrMissRate::total 0.053707 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1i-cache-0.ReadReq.avgMshrMissLatency::processor.cores.core.inst 48701.769231 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.ReadReq.avgMshrMissLatency::total 48701.769231 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.prefetcher.demandMshrMisses 1443 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1i-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1i-cache-0.tags.tagsInUse 509.492851 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1i-cache-0.tags.totalRefs 26354 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.sampledRefs 1442 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1i-cache-0.tags.avgRefs 18.276006 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1i-cache-0.tags.warmupTick 69930 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1i-cache-0.tags.occupancies::processor.cores.core.inst 509.492851 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::processor.cores.core.inst 0.995103 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.avgOccs::total 0.995103 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1i-cache-0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::0 247 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ageTaskId_1024::3 265 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1i-cache-0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1i-cache-0.tags.tagAccesses 216386 # Number of tag accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.dataAccesses 216386 # Number of data accesses (Count)
board.cache_hierarchy.l1i-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.demandHits::cache_hierarchy.l1d-cache-0.prefetcher 223 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2-cache-0.demandHits::processor.cores.core.inst 59 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2-cache-0.demandHits::processor.cores.core.data 292 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2-cache-0.demandHits::total 574 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2-cache-0.overallHits::cache_hierarchy.l1d-cache-0.prefetcher 223 # number of overall hits (Count)
board.cache_hierarchy.l2-cache-0.overallHits::processor.cores.core.inst 59 # number of overall hits (Count)
board.cache_hierarchy.l2-cache-0.overallHits::processor.cores.core.data 292 # number of overall hits (Count)
board.cache_hierarchy.l2-cache-0.overallHits::total 574 # number of overall hits (Count)
board.cache_hierarchy.l2-cache-0.demandMisses::cache_hierarchy.l1d-cache-0.prefetcher 554 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2-cache-0.demandMisses::processor.cores.core.inst 1383 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2-cache-0.demandMisses::processor.cores.core.data 966 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2-cache-0.demandMisses::total 2903 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2-cache-0.overallMisses::cache_hierarchy.l1d-cache-0.prefetcher 554 # number of overall misses (Count)
board.cache_hierarchy.l2-cache-0.overallMisses::processor.cores.core.inst 1383 # number of overall misses (Count)
board.cache_hierarchy.l2-cache-0.overallMisses::processor.cores.core.data 966 # number of overall misses (Count)
board.cache_hierarchy.l2-cache-0.overallMisses::total 2903 # number of overall misses (Count)
board.cache_hierarchy.l2-cache-0.demandMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 27559465 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMissLatency::processor.cores.core.inst 69037893 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMissLatency::processor.cores.core.data 50167449 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMissLatency::total 146764807 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 27559465 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMissLatency::processor.cores.core.inst 69037893 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMissLatency::processor.cores.core.data 50167449 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMissLatency::total 146764807 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandAccesses::cache_hierarchy.l1d-cache-0.prefetcher 777 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.demandAccesses::processor.cores.core.inst 1442 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.demandAccesses::processor.cores.core.data 1258 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.demandAccesses::total 3477 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.overallAccesses::cache_hierarchy.l1d-cache-0.prefetcher 777 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.overallAccesses::processor.cores.core.inst 1442 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.overallAccesses::processor.cores.core.data 1258 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.overallAccesses::total 3477 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2-cache-0.demandMissRate::cache_hierarchy.l1d-cache-0.prefetcher 0.712999 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMissRate::processor.cores.core.inst 0.959085 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMissRate::processor.cores.core.data 0.767886 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMissRate::total 0.834915 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMissRate::cache_hierarchy.l1d-cache-0.prefetcher 0.712999 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMissRate::processor.cores.core.inst 0.959085 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMissRate::processor.cores.core.data 0.767886 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMissRate::total 0.834915 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandAvgMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 49746.326715 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMissLatency::processor.cores.core.inst 49918.939262 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMissLatency::processor.cores.core.data 51933.177019 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMissLatency::total 50556.254564 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 49746.326715 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMissLatency::processor.cores.core.inst 49918.939262 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMissLatency::processor.cores.core.data 51933.177019 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMissLatency::total 50556.254564 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2-cache-0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2-cache-0.writebacks::writebacks 6 # number of writebacks (Count)
board.cache_hierarchy.l2-cache-0.writebacks::total 6 # number of writebacks (Count)
board.cache_hierarchy.l2-cache-0.demandMshrHits::cache_hierarchy.l1d-cache-0.prefetcher 162 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.demandMshrHits::processor.cores.core.data 3 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.demandMshrHits::total 165 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.overallMshrHits::cache_hierarchy.l1d-cache-0.prefetcher 162 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.overallMshrHits::processor.cores.core.data 3 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.overallMshrHits::total 165 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMisses::cache_hierarchy.l1d-cache-0.prefetcher 392 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMisses::processor.cores.core.inst 1383 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMisses::processor.cores.core.data 963 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMisses::total 2738 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::cache_hierarchy.l1d-cache-0.prefetcher 392 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::cache_hierarchy.l2-cache-0.prefetcher 465 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::processor.cores.core.inst 1383 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::processor.cores.core.data 963 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.overallMshrMisses::total 3203 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.demandMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 21825419 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMshrMissLatency::processor.cores.core.inst 68577687 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMshrMissLatency::processor.cores.core.data 49792824 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMshrMissLatency::total 140195930 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 21825419 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::cache_hierarchy.l2-cache-0.prefetcher 21754792 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::processor.cores.core.inst 68577687 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::processor.cores.core.data 49792824 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.overallMshrMissLatency::total 161950722 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.demandMshrMissRate::cache_hierarchy.l1d-cache-0.prefetcher 0.504505 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMshrMissRate::processor.cores.core.inst 0.959085 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMshrMissRate::processor.cores.core.data 0.765501 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandMshrMissRate::total 0.787460 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::cache_hierarchy.l1d-cache-0.prefetcher 0.504505 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::cache_hierarchy.l2-cache-0.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::processor.cores.core.inst 0.959085 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::processor.cores.core.data 0.765501 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.overallMshrMissRate::total 0.921196 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2-cache-0.demandAvgMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 55677.089286 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMshrMissLatency::processor.cores.core.inst 49586.180043 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMshrMissLatency::processor.cores.core.data 51705.943925 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.demandAvgMshrMissLatency::total 51203.772827 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 55677.089286 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::cache_hierarchy.l2-cache-0.prefetcher 46784.498925 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::processor.cores.core.inst 49586.180043 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::processor.cores.core.data 51705.943925 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.overallAvgMshrMissLatency::total 50562.198564 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.replacements 41 # number of replacements (Count)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMisses::cache_hierarchy.l2-cache-0.prefetcher 465 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMisses::total 465 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMissLatency::cache_hierarchy.l2-cache-0.prefetcher 21754792 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMissLatency::total 21754792 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMissRate::cache_hierarchy.l2-cache-0.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.HardPFReq.avgMshrMissLatency::cache_hierarchy.l2-cache-0.prefetcher 46784.498925 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.HardPFReq.avgMshrMissLatency::total 46784.498925 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadExReq.hits::processor.cores.core.data 36 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.hits::total 36 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.misses::processor.cores.core.data 207 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.misses::total 207 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.missLatency::processor.cores.core.data 11194794 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadExReq.missLatency::total 11194794 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadExReq.accesses::processor.cores.core.data 243 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.accesses::total 243 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.missRate::processor.cores.core.data 0.851852 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadExReq.missRate::total 0.851852 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadExReq.avgMissLatency::processor.cores.core.data 54081.130435 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadExReq.avgMissLatency::total 54081.130435 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrHits::processor.cores.core.data 1 # number of ReadExReq MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrHits::total 1 # number of ReadExReq MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrMisses::processor.cores.core.data 206 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrMisses::total 206 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrMissLatency::processor.cores.core.data 11112210 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrMissLatency::total 11112210 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrMissRate::processor.cores.core.data 0.847737 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadExReq.mshrMissRate::total 0.847737 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadExReq.avgMshrMissLatency::processor.cores.core.data 53942.766990 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadExReq.avgMshrMissLatency::total 53942.766990 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.hits::cache_hierarchy.l1d-cache-0.prefetcher 223 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.hits::processor.cores.core.inst 59 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.hits::processor.cores.core.data 256 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.hits::total 538 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.misses::cache_hierarchy.l1d-cache-0.prefetcher 554 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.misses::processor.cores.core.inst 1383 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.misses::processor.cores.core.data 759 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.misses::total 2696 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missLatency::cache_hierarchy.l1d-cache-0.prefetcher 27559465 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missLatency::processor.cores.core.inst 69037893 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missLatency::processor.cores.core.data 38972655 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missLatency::total 135570013 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.accesses::cache_hierarchy.l1d-cache-0.prefetcher 777 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.accesses::processor.cores.core.inst 1442 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.accesses::processor.cores.core.data 1015 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.accesses::total 3234 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missRate::cache_hierarchy.l1d-cache-0.prefetcher 0.712999 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missRate::processor.cores.core.inst 0.959085 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missRate::processor.cores.core.data 0.747783 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.missRate::total 0.833643 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 49746.326715 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMissLatency::processor.cores.core.inst 49918.939262 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMissLatency::processor.cores.core.data 51347.371542 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMissLatency::total 50285.613131 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrHits::cache_hierarchy.l1d-cache-0.prefetcher 162 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrHits::processor.cores.core.data 2 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrHits::total 164 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMisses::cache_hierarchy.l1d-cache-0.prefetcher 392 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMisses::processor.cores.core.inst 1383 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMisses::processor.cores.core.data 757 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMisses::total 2532 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 21825419 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissLatency::processor.cores.core.inst 68577687 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissLatency::processor.cores.core.data 38680614 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissLatency::total 129083720 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissRate::cache_hierarchy.l1d-cache-0.prefetcher 0.504505 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissRate::processor.cores.core.inst 0.959085 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissRate::processor.cores.core.data 0.745813 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.mshrMissRate::total 0.782931 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.l1d-cache-0.prefetcher 55677.089286 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMshrMissLatency::processor.cores.core.inst 49586.180043 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMshrMissLatency::processor.cores.core.data 51097.244386 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.ReadSharedReq.avgMshrMissLatency::total 50980.932070 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2-cache-0.UpgradeReq.hits::processor.cores.core.data 1 # number of UpgradeReq hits (Count)
board.cache_hierarchy.l2-cache-0.UpgradeReq.hits::total 1 # number of UpgradeReq hits (Count)
board.cache_hierarchy.l2-cache-0.UpgradeReq.accesses::processor.cores.core.data 1 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.UpgradeReq.accesses::total 1 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.WritebackClean.hits::writebacks 929 # number of WritebackClean hits (Count)
board.cache_hierarchy.l2-cache-0.WritebackClean.hits::total 929 # number of WritebackClean hits (Count)
board.cache_hierarchy.l2-cache-0.WritebackClean.accesses::writebacks 929 # number of WritebackClean accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.WritebackClean.accesses::total 929 # number of WritebackClean accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.WritebackDirty.hits::writebacks 497 # number of WritebackDirty hits (Count)
board.cache_hierarchy.l2-cache-0.WritebackDirty.hits::total 497 # number of WritebackDirty hits (Count)
board.cache_hierarchy.l2-cache-0.WritebackDirty.accesses::writebacks 497 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.WritebackDirty.accesses::total 497 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.l2-cache-0.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.prefetcher.demandMshrMisses 2738 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIssued 1277 # number of hwpf issued (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUnused 1 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUseful 226 # number of useful prefetch (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.accuracy 0.176977 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.coverage 0.076248 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInCache 353 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInMSHR 459 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfLate 812 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfIdentified 1498 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfBufferHit 120 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedDemand 56 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfSpanPage 190 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.pfUsefulSpanPage 35 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2-cache-0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2-cache-0.tags.tagsInUse 2898.619262 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2-cache-0.tags.totalRefs 6229 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.sampledRefs 3209 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2-cache-0.tags.avgRefs 1.941103 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2-cache-0.tags.warmupTick 69264 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2-cache-0.tags.occupancies::writebacks 2.904329 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l1d-cache-0.prefetcher 383.860117 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::cache_hierarchy.l2-cache-0.prefetcher 452.966846 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.cores.core.inst 1130.098781 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupancies::processor.cores.core.data 928.789189 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::writebacks 0.000709 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l1d-cache-0.prefetcher 0.093716 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::cache_hierarchy.l2-cache-0.prefetcher 0.110588 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.cores.core.inst 0.275903 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::processor.cores.core.data 0.226755 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.avgOccs::total 0.707671 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1022 851 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.occupanciesTaskId::1024 2317 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1022::3 851 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::0 248 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ageTaskId_1024::3 2069 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1022 0.207764 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.ratioOccsTaskId::1024 0.565674 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2-cache-0.tags.tagAccesses 98089 # Number of tag accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.dataAccesses 98089 # Number of data accesses (Count)
board.cache_hierarchy.l2-cache-0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.transDist::ReadResp 3234 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::WritebackDirty 503 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::WritebackClean 929 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::CleanEvict 1061 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::HardPFReq 573 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::UpgradeReq 1 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::UpgradeResp 1 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::ReadExReq 243 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::ReadExResp 243 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.transDist::ReadSharedReq 3235 # Transaction distribution (Count)
board.cache_hierarchy.l2buses.pktCount_board.cache_hierarchy.l1i-cache-0.mem_side_port::board.cache_hierarchy.l2-cache-0.cpu_side_port 3813 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2buses.pktCount_board.cache_hierarchy.l1d-cache-0.mem_side_port::board.cache_hierarchy.l2-cache-0.cpu_side_port 5595 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2buses.pktCount::total 9408 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2buses.pktSize_board.cache_hierarchy.l1i-cache-0.mem_side_port::board.cache_hierarchy.l2-cache-0.cpu_side_port 151680 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2buses.pktSize_board.cache_hierarchy.l1d-cache-0.mem_side_port::board.cache_hierarchy.l2-cache-0.cpu_side_port 162048 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2buses.pktSize::total 313728 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2buses.snoops 615 # Total snoops (Count)
board.cache_hierarchy.l2buses.snoopTraffic 448 # Total snoop traffic (Byte)
board.cache_hierarchy.l2buses.snoopFanout::samples 4093 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::mean 0.003665 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::stdev 0.060434 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::0 4078 99.63% 99.63% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::1 15 0.37% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::max_value 1 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.snoopFanout::total 4093 # Request fanout histogram (Count)
board.cache_hierarchy.l2buses.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2buses.reqLayer0.occupancy 3012227 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2buses.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2buses.respLayer0.occupancy 1440558 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2buses.respLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2buses.respLayer1.occupancy 2033298 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2buses.respLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2buses.snoop_filter.totRequests 5931 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleRequests 2453 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiRequests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.totSnoops 13 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitSingleSnoops 13 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2buses.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.transDist::ReadResp 2996 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WritebackDirty 6 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::CleanEvict 22 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq 206 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp 206 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq 2996 # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2-cache-0.mem_side_port::board.memory.mem_ctrl0.port 3235 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2-cache-0.mem_side_port::board.memory.mem_ctrl1.port 3197 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2-cache-0.mem_side_port::total 6432 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total 6432 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2-cache-0.mem_side_port::board.memory.mem_ctrl0.port 103168 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2-cache-0.mem_side_port::board.memory.mem_ctrl1.port 102144 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2-cache-0.mem_side_port::total 205312 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total 205312 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 3202 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 3202 100.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 3202 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy 589174 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.reqLayer1.occupancy 587467 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer1.occupancy 2619349 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests 3230 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 28 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.avgPriority_writebacks::samples 3.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_cache_hierarchy.l1d-cache-0.prefetcher::samples 193.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_cache_hierarchy.l2-cache-0.prefetcher::samples 235.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores.core.inst::samples 688.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores.core.data::samples 493.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.priorityMinLatency 0.000000017492 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.000000702630 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 3830 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 1609 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 3 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 1609 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 3 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 2.94 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 0.01 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 1609 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 3 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 1099 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 307 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 104 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 54 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 29 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 9 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 5 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 1 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 1 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 102976 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 192 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 42328121.87569805 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 78921.29622566 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 2432620944 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap 1509070.06 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.requestorReadBytes::cache_hierarchy.l1d-cache-0.prefetcher 12352 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::cache_hierarchy.l2-cache-0.prefetcher 15040 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores.core.inst 44032 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores.core.data 31552 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadRate::cache_hierarchy.l1d-cache-0.prefetcher 5077270.057184414938 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::cache_hierarchy.l2-cache-0.prefetcher 6182168.204343717545 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores.core.inst 18099283.934419054538 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores.core.data 12969399.679750863463 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadAccesses::cache_hierarchy.l1d-cache-0.prefetcher 193 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::cache_hierarchy.l2-cache-0.prefetcher 235 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores.core.inst 688 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores.core.data 493 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorWriteAccesses::writebacks 3 # Per-requestor write serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadTotalLat::cache_hierarchy.l1d-cache-0.prefetcher 5430471 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::cache_hierarchy.l2-cache-0.prefetcher 5411350 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores.core.inst 15211606 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores.core.data 11849115 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadAvgLat::cache_hierarchy.l1d-cache-0.prefetcher 28137.16 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::cache_hierarchy.l2-cache-0.prefetcher 23027.02 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores.core.inst 22109.89 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores.core.data 24034.72 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorWriteAvgLat::writebacks 0.00 # Per-requestor write average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.dram.bytesRead::cache_hierarchy.l1d-cache-0.prefetcher 12352 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::cache_hierarchy.l2-cache-0.prefetcher 15040 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores.core.inst 44032 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores.core.data 31552 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::total 102976 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesInstRead::processor.cores.core.inst 44032 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesInstRead::total 44032 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesWritten::writebacks 192 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl0.dram.bytesWritten::total 192 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl0.dram.numReads::cache_hierarchy.l1d-cache-0.prefetcher 193 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::cache_hierarchy.l2-cache-0.prefetcher 235 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores.core.inst 688 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores.core.data 493 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::total 1609 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numWrites::writebacks 3 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numWrites::total 3 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.bwRead::cache_hierarchy.l1d-cache-0.prefetcher 5077270 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::cache_hierarchy.l2-cache-0.prefetcher 6182168 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores.core.inst 18099284 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores.core.data 12969400 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::total 42328122 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwInstRead::processor.cores.core.inst 18099284 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwInstRead::total 18099284 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwWrite::writebacks 78921 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwWrite::total 78921 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::writebacks 78921 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::cache_hierarchy.l1d-cache-0.prefetcher 5077270 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::cache_hierarchy.l2-cache-0.prefetcher 6182168 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores.core.inst 18099284 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores.core.data 12969400 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::total 42407043 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.readBursts 1609 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 39 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 58 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 50 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 91 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 50 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 63 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 111 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 104 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 40 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 75 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 43 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 46 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 33 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 1 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 22 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 94 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 52 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 19 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 37 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 80 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 74 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 89 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 67 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 42 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 64 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 29 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 28 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 24 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 29 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 20 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 16 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 19 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 9757914 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 5361188 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 37902542 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat 6064.58 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat 3332.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat 23556.58 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 1376 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate 85.52 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.bytesPerActivate::samples 222 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::mean 455.783784 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::gmean 307.701445 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::stdev 346.814056 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::0-127 42 18.92% 18.92% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::128-255 30 13.51% 32.43% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::256-383 39 17.57% 50.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::384-511 24 10.81% 60.81% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::512-639 14 6.31% 67.12% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::640-767 17 7.66% 74.77% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::768-895 11 4.95% 79.73% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::896-1023 7 3.15% 82.88% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::1024-1151 38 17.12% 100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::total 222 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.dramBytesRead 102976 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 42.328122 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 0.22 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 0.22 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate 85.52 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 219872.016000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 363382.588800 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 2523470.208000 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 210866931.475201 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 93103555.675201 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 729792686.112003 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 1036869898.075200 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 426.203731 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 2231482729 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 109200000 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 92120699 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 143462.592000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 247760.856000 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 1889859.753600 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 210866931.475201 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 83806118.138400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 736211221.670403 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 1033165354.485600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 424.680984 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 2251190492 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 109200000 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 72412936 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.avgPriority_writebacks::samples 3.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_cache_hierarchy.l1d-cache-0.prefetcher::samples 199.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_cache_hierarchy.l2-cache-0.prefetcher::samples 230.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores.core.inst::samples 694.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores.core.data::samples 470.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.priorityMinLatency 0.000000017492 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.000000754380 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 3801 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 1593 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 3 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 1593 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 3 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 1.98 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 1593 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 3 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 1068 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 296 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 120 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 64 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 26 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 10 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 5 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 3 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 1 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 1 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
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board.memory.mem_ctrl1.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 101952 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 192 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 41907208.29582784 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 78921.29622566 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 2432533365 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap 1524143.71 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.requestorReadBytes::cache_hierarchy.l1d-cache-0.prefetcher 12736 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::cache_hierarchy.l2-cache-0.prefetcher 14720 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores.core.inst 44416 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores.core.data 30080 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadRate::cache_hierarchy.l1d-cache-0.prefetcher 5235112.649635744281 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::cache_hierarchy.l2-cache-0.prefetcher 6050632.710634277202 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores.core.inst 18257126.526870384812 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores.core.data 12364336.408687435091 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadAccesses::cache_hierarchy.l1d-cache-0.prefetcher 199 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::cache_hierarchy.l2-cache-0.prefetcher 230 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores.core.inst 694 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores.core.data 470 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorWriteAccesses::writebacks 3 # Per-requestor write serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadTotalLat::cache_hierarchy.l1d-cache-0.prefetcher 5696801 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::cache_hierarchy.l2-cache-0.prefetcher 5248912 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores.core.inst 15834964 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores.core.data 11772159 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadAvgLat::cache_hierarchy.l1d-cache-0.prefetcher 28627.14 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::cache_hierarchy.l2-cache-0.prefetcher 22821.36 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores.core.inst 22816.95 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores.core.data 25047.15 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorWriteAvgLat::writebacks 0.00 # Per-requestor write average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.dram.bytesRead::cache_hierarchy.l1d-cache-0.prefetcher 12736 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::cache_hierarchy.l2-cache-0.prefetcher 14720 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores.core.inst 44416 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores.core.data 30080 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::total 101952 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::processor.cores.core.inst 44416 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::total 44416 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesWritten::writebacks 192 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl1.dram.bytesWritten::total 192 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl1.dram.numReads::cache_hierarchy.l1d-cache-0.prefetcher 199 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::cache_hierarchy.l2-cache-0.prefetcher 230 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores.core.inst 694 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores.core.data 470 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::total 1593 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numWrites::writebacks 3 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numWrites::total 3 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.bwRead::cache_hierarchy.l1d-cache-0.prefetcher 5235113 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::cache_hierarchy.l2-cache-0.prefetcher 6050633 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores.core.inst 18257127 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores.core.data 12364336 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::total 41907208 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::processor.cores.core.inst 18257127 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::total 18257127 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwWrite::writebacks 78921 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwWrite::total 78921 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::writebacks 78921 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::cache_hierarchy.l1d-cache-0.prefetcher 5235113 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::cache_hierarchy.l2-cache-0.prefetcher 6050633 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores.core.inst 18257127 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores.core.data 12364336 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::total 41986130 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.readBursts 1593 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 36 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 61 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 52 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 94 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 53 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 69 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 106 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 108 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 32 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 78 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 41 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 45 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 31 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 1 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 21 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 89 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 48 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 10 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 37 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 76 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 69 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 87 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 63 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 46 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 61 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 31 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 32 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 30 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 31 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 23 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 16 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 16 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 10688080 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 5307876 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 38552836 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat 6709.40 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat 3332.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat 24201.40 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 1360 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate 85.37 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.bytesPerActivate::samples 222 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::mean 452.324324 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::gmean 306.629743 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::stdev 344.999552 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::0-127 41 18.47% 18.47% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::128-255 38 17.12% 35.59% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::256-383 28 12.61% 48.20% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::384-511 28 12.61% 60.81% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::512-639 22 9.91% 70.72% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::640-767 14 6.31% 77.03% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::768-895 7 3.15% 80.18% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::896-1023 3 1.35% 81.53% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::1024-1151 41 18.47% 100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::total 222 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.dramBytesRead 101952 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 41.907208 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 0.22 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 0.22 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate 85.37 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 230787.648000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 379899.979200 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 2515241.500800 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 210866931.475201 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 90888979.860001 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 731321530.329603 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 1036203370.792800 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 425.929756 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 2236181389 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 109200000 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 87422039 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 132546.960000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 231243.465600 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 1854202.022400 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 210866931.475201 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 81504109.310400 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 737800425.734403 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 1032389458.968000 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 424.362054 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 2256058671 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 109200000 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 67544757 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles 7305717 # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.cpi 0.801449 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores.core.ipc 1.247741 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores.core.instsAdded 18384001 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.cores.core.nonSpecInstsAdded 68 # Number of non-speculative instructions added to the IQ (Count)
board.processor.cores.core.instsIssued 18316902 # Number of instructions issued (Count)
board.processor.cores.core.squashedInstsIssued 1768 # Number of squashed instructions issued (Count)
board.processor.cores.core.squashedInstsExamined 154231 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
board.processor.cores.core.squashedOperandsExamined 340289 # Number of squashed operands that are examined and possibly removed from graph (Count)
board.processor.cores.core.squashedNonSpecRemoved 32 # Number of squashed non-spec instructions that were removed (Count)
board.processor.cores.core.numIssuedDist::samples 7200343 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::mean 2.543893 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::stdev 1.275164 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::0 135418 1.88% 1.88% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::1 1755204 24.38% 26.26% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::2 1508089 20.94% 47.20% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::3 2247455 31.21% 78.42% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::4 1015336 14.10% 92.52% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::5 510292 7.09% 99.60% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::6 15230 0.21% 99.82% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::7 7581 0.11% 99.92% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::8 5738 0.08% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::total 7200343 # Number of insts issued each cycle (Count)
board.processor.cores.core.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntAlu 7606 69.86% 69.86% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntMult 0 0.00% 69.86% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntDiv 0 0.00% 69.86% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatAdd 0 0.00% 69.86% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCmp 0 0.00% 69.86% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCvt 0 0.00% 69.86% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMult 0 0.00% 69.86% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMultAcc 0 0.00% 69.86% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatDiv 0 0.00% 69.86% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMisc 0 0.00% 69.86% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatSqrt 0 0.00% 69.86% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAdd 0 0.00% 69.86% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAddAcc 0 0.00% 69.86% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAlu 15 0.14% 69.99% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCmp 0 0.00% 69.99% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCvt 12 0.11% 70.10% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMisc 4 0.04% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMult 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMultAcc 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMatMultAcc 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShift 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShiftAcc 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdDiv 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSqrt 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAdd 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAlu 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCmp 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCvt 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatDiv 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMisc 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMult 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMultAcc 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMatMultAcc 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatSqrt 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAdd 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAlu 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceCmp 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceAdd 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceCmp 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAes 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAesMix 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash2 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash2 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma2 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma3 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdPredAlu 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::Matrix 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MatrixMov 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MatrixOP 0 0.00% 70.14% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemRead 2780 25.53% 95.67% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemWrite 427 3.92% 99.60% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemRead 9 0.08% 99.68% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemWrite 35 0.32% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statIssuedInstType_0::No_OpClass 2918 0.02% 0.02% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntAlu 10236068 55.88% 55.90% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntMult 1752 0.01% 55.91% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntDiv 1543 0.01% 55.92% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatAdd 737 0.00% 55.92% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCmp 0 0.00% 55.92% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCvt 0 0.00% 55.92% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMult 0 0.00% 55.92% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 55.92% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatDiv 0 0.00% 55.92% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMisc 0 0.00% 55.92% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatSqrt 0 0.00% 55.92% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAdd 512 0.00% 55.92% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 55.92% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAlu 1686 0.01% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCmp 4 0.00% 55.93% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCvt 1304 0.01% 55.94% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMisc 1164 0.01% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMult 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShift 521 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdDiv 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSqrt 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAes 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAesMix 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::Matrix 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MatrixMov 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MatrixOP 0 0.00% 55.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemRead 6045408 33.00% 88.95% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemWrite 2019835 11.03% 99.98% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemRead 2034 0.01% 99.99% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemWrite 1416 0.01% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::total 18316902 # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.issueRate 2.507201 # Inst issue rate ((Count/Cycle))
board.processor.cores.core.fuBusy 10888 # FU busy when requested (Count)
board.processor.cores.core.fuBusyRate 0.000594 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.cores.core.intInstQueueReads 43826992 # Number of integer instruction queue reads (Count)
board.processor.cores.core.intInstQueueWrites 18520631 # Number of integer instruction queue writes (Count)
board.processor.cores.core.intInstQueueWakeupAccesses 18295905 # Number of integer instruction queue wakeup accesses (Count)
board.processor.cores.core.fpInstQueueReads 19811 # Number of floating instruction queue reads (Count)
board.processor.cores.core.fpInstQueueWrites 18778 # Number of floating instruction queue writes (Count)
board.processor.cores.core.fpInstQueueWakeupAccesses 9069 # Number of floating instruction queue wakeup accesses (Count)
board.processor.cores.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.cores.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.cores.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.cores.core.intAluAccesses 18314984 # Number of integer alu accesses (Count)
board.processor.cores.core.fpAluAccesses 9888 # Number of floating point alu accesses (Count)
board.processor.cores.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.numSquashedInsts 8463 # Number of squashed instructions skipped in execute (Count)
board.processor.cores.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.cores.core.timesIdled 909 # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
board.processor.cores.core.idleCycles 105374 # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
board.processor.cores.core.MemDepUnit__0.insertedLoads 6063991 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.insertedStores 2028720 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingLoads 4024174 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingStores 1012408 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.branchPred.lookups_0::NoBranch 514 0.05% 0.05% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::Return 1649 0.16% 0.21% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallDirect 1898 0.18% 0.39% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallIndirect 227 0.02% 0.41% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectCond 1042597 99.28% 99.69% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectUncond 2618 0.25% 99.94% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectCond 0 0.00% 99.94% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectUncond 659 0.06% 100.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::total 1050162 # Number of BP lookups (Count)
board.processor.cores.core.branchPred.squashes_0::NoBranch 474 1.83% 1.83% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::Return 783 3.02% 4.84% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallDirect 1141 4.39% 9.23% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallIndirect 113 0.44% 9.67% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectCond 22108 85.13% 94.80% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectUncond 908 3.50% 98.29% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectCond 0 0.00% 98.29% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectUncond 443 1.71% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::total 25970 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.corrected_0::NoBranch 89 2.11% 2.11% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::Return 1 0.02% 2.13% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallDirect 319 7.55% 9.69% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallIndirect 103 2.44% 12.12% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectCond 3283 77.74% 89.87% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectUncond 279 6.61% 96.47% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectCond 0 0.00% 96.47% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectUncond 149 3.53% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::total 4223 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.committed_0::NoBranch 40 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::Return 866 0.08% 0.09% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::CallDirect 757 0.07% 0.16% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::CallIndirect 114 0.01% 0.17% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::DirectCond 1020488 99.64% 99.81% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::DirectUncond 1710 0.17% 99.98% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::IndirectCond 0 0.00% 99.98% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::IndirectUncond 216 0.02% 100.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::total 1024191 # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.mispredicted_0::NoBranch 40 1.10% 1.10% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::Return 0 0.00% 1.10% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallDirect 179 4.94% 6.05% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallIndirect 99 2.73% 8.78% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectCond 3024 83.51% 92.29% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectUncond 145 4.00% 96.30% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectCond 0 0.00% 96.30% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectUncond 134 3.70% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::total 3621 # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.targetProvider_0::NoTarget 22931 2.18% 2.18% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::BTB 1025434 97.65% 99.83% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::RAS 1649 0.16% 99.99% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::Indirect 148 0.01% 100.00% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::total 1050162 # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetWrong_0::NoBranch 2446 61.52% 61.52% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::Return 1513 38.05% 99.57% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallDirect 1 0.03% 99.60% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallIndirect 16 0.40% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::total 3976 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.condPredicted 1043111 # Number of conditional branches predicted (Count)
board.processor.cores.core.branchPred.condPredictedTaken 1023335 # Number of conditional branches predicted as taken (Count)
board.processor.cores.core.branchPred.condIncorrect 4223 # Number of conditional branches incorrect (Count)
board.processor.cores.core.branchPred.predTakenBTBMiss 814 # Number of branches predicted taken but missed in BTB (Count)
board.processor.cores.core.branchPred.NotTakenMispredicted 2692 # Number branches predicted 'not taken' but turned out to be taken (Count)
board.processor.cores.core.branchPred.TakenMispredicted 1531 # Number branches predicted taken but are actually not taken (Count)
board.processor.cores.core.branchPred.BTBLookups 1050162 # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.BTBUpdates 2350 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.BTBHits 1034539 # Number of BTB hits (Count)
board.processor.cores.core.branchPred.BTBHitRatio 0.985123 # BTB Hit Ratio (Ratio)
board.processor.cores.core.branchPred.BTBMispredicted 1335 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.cores.core.branchPred.indirectLookups 886 # Number of indirect predictor lookups. (Count)
board.processor.cores.core.branchPred.indirectHits 148 # Number of indirect target hits. (Count)
board.processor.cores.core.branchPred.indirectMisses 738 # Number of indirect misses. (Count)
board.processor.cores.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.cores.core.branchPred.btb.lookups::NoBranch 514 0.05% 0.05% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::Return 1649 0.16% 0.21% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallDirect 1898 0.18% 0.39% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallIndirect 227 0.02% 0.41% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectCond 1042597 99.28% 99.69% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectUncond 2618 0.25% 99.94% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectCond 0 0.00% 99.94% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectUncond 659 0.06% 100.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::total 1050162 # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.misses::NoBranch 154 0.99% 0.99% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::Return 1646 10.54% 11.52% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallDirect 509 3.26% 14.78% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallIndirect 227 1.45% 16.23% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectCond 12030 77.00% 93.23% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectUncond 398 2.55% 95.78% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectCond 0 0.00% 95.78% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectUncond 659 4.22% 100.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::total 15623 # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.updates::NoBranch 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::Return 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallDirect 319 13.57% 13.57% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallIndirect 0 0.00% 13.57% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectCond 1752 74.55% 88.13% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectUncond 279 11.87% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectCond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectUncond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::total 2350 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.mispredict::NoBranch 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::Return 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallDirect 319 13.57% 13.57% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallIndirect 0 0.00% 13.57% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectCond 1752 74.55% 88.13% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectUncond 279 11.87% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectCond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectUncond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::total 2350 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.branchPred.indirectBranchPred.lookups 886 # Number of lookups (Count)
board.processor.cores.core.branchPred.indirectBranchPred.hits 148 # Number of hits of a tag (Count)
board.processor.cores.core.branchPred.indirectBranchPred.misses 738 # Number of misses (Count)
board.processor.cores.core.branchPred.indirectBranchPred.targetRecords 252 # Number of targets that where recorded/installed in the cache (Count)
board.processor.cores.core.branchPred.indirectBranchPred.indirectRecords 1138 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.cores.core.branchPred.indirectBranchPred.speculativeOverflows 6 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.cores.core.branchPred.ras.pushes 2908 # Number of times a PC was pushed onto the RAS (Count)
board.processor.cores.core.branchPred.ras.pops 2903 # Number of times a PC was poped from the RAS (Count)
board.processor.cores.core.branchPred.ras.squashes 2037 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.cores.core.branchPred.ras.used 866 # Number of times the RAS is the provider (Count)
board.processor.cores.core.branchPred.ras.correct 866 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.cores.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.cores.core.commit.commitSquashedInsts 152183 # The number of squashed insts skipped by commit (Count)
board.processor.cores.core.commit.commitNonSpecStalls 36 # The number of times commit has been forced to stall to communicate backwards (Count)
board.processor.cores.core.commit.branchMispredicts 3845 # The number of times a branch was mispredicted (Count)
board.processor.cores.core.commit.numCommittedDist::samples 7177989 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::mean 2.539685 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::stdev 2.670926 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::0 1129658 15.74% 15.74% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::1 3008002 41.91% 57.64% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::2 1007941 14.04% 71.69% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::3 7711 0.11% 71.79% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::4 3331 0.05% 71.84% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::5 998350 13.91% 85.75% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::6 2578 0.04% 85.78% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::7 1071 0.01% 85.80% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::8 1019347 14.20% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::total 7177989 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.cores.core.commit.membars 24 # Number of memory barriers committed (Count)
board.processor.cores.core.commit.functionCalls 871 # Number of function calls committed. (Count)
board.processor.cores.core.commit.committedInstType_0::No_OpClass 1311 0.01% 0.01% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntAlu 10171777 55.80% 55.80% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntMult 1701 0.01% 55.81% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntDiv 1418 0.01% 55.82% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatAdd 398 0.00% 55.82% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCmp 0 0.00% 55.82% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCvt 0 0.00% 55.82% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMult 0 0.00% 55.82% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 55.82% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatDiv 0 0.00% 55.82% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMisc 0 0.00% 55.82% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatSqrt 0 0.00% 55.82% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAdd 396 0.00% 55.83% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 55.83% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAlu 872 0.00% 55.83% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCmp 4 0.00% 55.83% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCvt 918 0.01% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMisc 972 0.01% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMult 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShift 190 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdDiv 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSqrt 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAes 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAesMix 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::Matrix 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MatrixMov 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MatrixOP 0 0.00% 55.84% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemRead 6031950 33.09% 88.93% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemWrite 2015797 11.06% 99.99% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemRead 1009 0.01% 99.99% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemWrite 1119 0.01% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::total 18229832 # Class of committed instruction (Count)
board.processor.cores.core.commit.commitEligibleSamples 1019347 # number cycles where commit BW limit reached (Cycle)
board.processor.cores.core.commitStats0.numInsts 9115640 # Number of instructions committed (thread level) (Count)
board.processor.cores.core.commitStats0.numOps 18229832 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores.core.commitStats0.numInstsNotNOP 9115640 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores.core.commitStats0.numOpsNotNOP 18229832 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores.core.commitStats0.cpi 0.801449 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores.core.commitStats0.ipc 1.247741 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores.core.commitStats0.numMemRefs 8049875 # Number of memory references committed (Count)
board.processor.cores.core.commitStats0.numFpInsts 6242 # Number of float instructions (Count)
board.processor.cores.core.commitStats0.numIntInsts 18224138 # Number of integer instructions (Count)
board.processor.cores.core.commitStats0.numLoadInsts 6032959 # Number of load instructions (Count)
board.processor.cores.core.commitStats0.numStoreInsts 2016916 # Number of store instructions (Count)
board.processor.cores.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores.core.commitStats0.committedInstType::No_OpClass 1311 0.01% 0.01% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntAlu 10171777 55.80% 55.80% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntMult 1701 0.01% 55.81% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntDiv 1418 0.01% 55.82% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatAdd 398 0.00% 55.82% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCmp 0 0.00% 55.82% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCvt 0 0.00% 55.82% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMult 0 0.00% 55.82% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 55.82% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatDiv 0 0.00% 55.82% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMisc 0 0.00% 55.82% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 55.82% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAdd 396 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAlu 872 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCmp 4 0.00% 55.83% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCvt 918 0.01% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMisc 972 0.01% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMult 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShift 190 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdDiv 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAes 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::Matrix 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixMov 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixOP 0 0.00% 55.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemRead 6031950 33.09% 88.93% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemWrite 2015797 11.06% 99.99% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemRead 1009 0.01% 99.99% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemWrite 1119 0.01% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::total 18229832 # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedControl::IsControl 1024191 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsDirectControl 1022955 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsIndirectControl 1196 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCondControl 1020488 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsUncondControl 3663 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCall 871 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsReturn 866 # Class of control type instructions committed (Count)
board.processor.cores.core.decode.idleCycles 1046814 # Number of cycles decode is idle (Cycle)
board.processor.cores.core.decode.blockedCycles 3835085 # Number of cycles decode is blocked (Cycle)
board.processor.cores.core.decode.runCycles 61398 # Number of cycles decode is running (Cycle)
board.processor.cores.core.decode.unblockCycles 2251972 # Number of cycles decode is unblocking (Cycle)
board.processor.cores.core.decode.squashCycles 5074 # Number of cycles decode is squashing (Cycle)
board.processor.cores.core.decode.branchResolved 1020973 # Number of times decode resolved a branch (Count)
board.processor.cores.core.decode.branchMispred 637 # Number of times decode detected a branch misprediction (Count)
board.processor.cores.core.decode.decodedInsts 18454011 # Number of instructions handled by decode (Count)
board.processor.cores.core.decode.squashedInsts 3260 # Number of squashed instructions handled by decode (Count)
board.processor.cores.core.executeStats0.numInsts 18308439 # Number of executed instructions (Count)
board.processor.cores.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores.core.executeStats0.numBranches 1028956 # Number of branches executed (Count)
board.processor.cores.core.executeStats0.numLoadInsts 6046356 # Number of load instructions executed (Count)
board.processor.cores.core.executeStats0.numStoreInsts 2020767 # Number of stores executed (Count)
board.processor.cores.core.executeStats0.instRate 2.506043 # Inst execution rate ((Count/Cycle))
board.processor.cores.core.executeStats0.numCCRegReads 5141136 # Number of times the CC registers were read (Count)
board.processor.cores.core.executeStats0.numCCRegWrites 8103340 # Number of times the CC registers were written (Count)
board.processor.cores.core.executeStats0.numFpRegReads 13213 # Number of times the floating registers were read (Count)
board.processor.cores.core.executeStats0.numFpRegWrites 7259 # Number of times the floating registers were written (Count)
board.processor.cores.core.executeStats0.numIntRegReads 22344528 # Number of times the integer registers were read (Count)
board.processor.cores.core.executeStats0.numIntRegWrites 14230012 # Number of times the integer registers were written (Count)
board.processor.cores.core.executeStats0.numMemRefs 8067123 # Number of memory refs (Count)
board.processor.cores.core.executeStats0.numMiscRegReads 10128749 # Number of times the Misc registers were read (Count)
board.processor.cores.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores.core.fetch.predictedBranches 1027231 # Number of branches that fetch has predicted taken (Count)
board.processor.cores.core.fetch.cycles 7150228 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.cores.core.fetch.squashCycles 11394 # Number of cycles fetch has spent squashing (Cycle)
board.processor.cores.core.fetch.miscStallCycles 267 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs (Cycle)
board.processor.cores.core.fetch.pendingTrapStallCycles 1986 # Number of stall cycles due to pending traps (Cycle)
board.processor.cores.core.fetch.cacheLines 26868 # Number of cache lines fetched (Count)
board.processor.cores.core.fetch.icacheSquashes 978 # Number of outstanding Icache misses that were squashed (Count)
board.processor.cores.core.fetch.nisnDist::samples 7200343 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::mean 2.576090 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::stdev 3.337667 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::0 4112277 57.11% 57.11% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::1 3951 0.05% 57.17% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::2 513960 7.14% 64.31% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::3 4391 0.06% 64.37% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::4 498656 6.93% 71.29% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::5 5480 0.08% 71.37% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::6 503272 6.99% 78.36% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::7 4813 0.07% 78.42% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::8 1553543 21.58% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::total 7200343 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetchStats0.numInsts 9277295 # Number of instructions fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.fetchRate 1.269868 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores.core.fetchStats0.numBranches 1050162 # Number of branches fetched (Count)
board.processor.cores.core.fetchStats0.branchRate 0.143745 # Number of branch fetches per cycle (Ratio)
board.processor.cores.core.fetchStats0.icacheStallCycles 42165 # ICache total stall cycles (Cycle)
board.processor.cores.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.cores.core.iew.squashCycles 5074 # Number of cycles IEW is squashing (Cycle)
board.processor.cores.core.iew.blockCycles 52912 # Number of cycles IEW is blocking (Cycle)
board.processor.cores.core.iew.unblockCycles 975 # Number of cycles IEW is unblocking (Cycle)
board.processor.cores.core.iew.dispatchedInsts 18384069 # Number of instructions dispatched to IQ (Count)
board.processor.cores.core.iew.dispSquashedInsts 149 # Number of squashed instructions skipped by dispatch (Count)
board.processor.cores.core.iew.dispLoadInsts 6063991 # Number of dispatched load instructions (Count)
board.processor.cores.core.iew.dispStoreInsts 2028720 # Number of dispatched store instructions (Count)
board.processor.cores.core.iew.dispNonSpecInsts 23 # Number of dispatched non-speculative instructions (Count)
board.processor.cores.core.iew.iqFullEvents 266 # Number of times the IQ has become full, causing a stall (Count)
board.processor.cores.core.iew.lsqFullEvents 538 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.cores.core.iew.memOrderViolationEvents 1112 # Number of memory order violations (Count)
board.processor.cores.core.iew.predictedTakenIncorrect 1669 # Number of branches that were predicted taken incorrectly (Count)
board.processor.cores.core.iew.predictedNotTakenIncorrect 2747 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.cores.core.iew.branchMispredicts 4416 # Number of branch mispredicts detected at execute (Count)
board.processor.cores.core.iew.instsToCommit 18307579 # Cumulative count of insts sent to commit (Count)
board.processor.cores.core.iew.writebackCount 18304974 # Cumulative count of insts written-back (Count)
board.processor.cores.core.iew.producerInst 14476867 # Number of instructions producing a value (Count)
board.processor.cores.core.iew.consumerInst 15617430 # Number of instructions consuming a value (Count)
board.processor.cores.core.iew.wbRate 2.505568 # Insts written-back per cycle ((Count/Cycle))
board.processor.cores.core.iew.wbFanout 0.926969 # Average fanout of values written-back ((Count/Count))
board.processor.cores.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.cores.core.lsq0.forwLoads 4011970 # Number of loads that had data forwarded from stores (Count)
board.processor.cores.core.lsq0.squashedLoads 31032 # Number of loads squashed (Count)
board.processor.cores.core.lsq0.ignoredResponses 20 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.cores.core.lsq0.memOrderViolation 1112 # Number of memory ordering violations (Count)
board.processor.cores.core.lsq0.squashedStores 11804 # Number of stores squashed (Count)
board.processor.cores.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.cores.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.cores.core.lsq0.loadToUse::samples 6032959 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::mean 2.037536 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::stdev 2.582861 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::0-9 6031184 99.97% 99.97% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::10-19 324 0.01% 99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::20-29 17 0.00% 99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::30-39 9 0.00% 99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::40-49 10 0.00% 99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::50-59 3 0.00% 99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::60-69 7 0.00% 99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::70-79 9 0.00% 99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::80-89 9 0.00% 99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::90-99 16 0.00% 99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::100-109 11 0.00% 99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::110-119 17 0.00% 99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::120-129 27 0.00% 99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::130-139 620 0.01% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::140-149 307 0.01% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::150-159 48 0.00% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::160-169 16 0.00% 99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::170-179 57 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::180-189 227 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::190-199 9 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::200-209 7 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::210-219 2 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::220-229 6 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::230-239 8 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::240-249 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::250-259 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::overflows 7 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::max_value 1200 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::total 6032959 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.mmu.dtb.rdAccesses 6046397 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrAccesses 2020771 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.dtb.rdMisses 320 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrMisses 73 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.itb.wrAccesses 27147 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.itb.wrMisses 426 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON 2432803428 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.rename.squashCycles 5074 # Number of cycles rename is squashing (Cycle)
board.processor.cores.core.rename.idleCycles 1303311 # Number of cycles rename is idle (Cycle)
board.processor.cores.core.rename.blockCycles 79979 # Number of cycles rename is blocking (Cycle)
board.processor.cores.core.rename.serializeStallCycles 1893 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.cores.core.rename.runCycles 2054897 # Number of cycles rename is running (Cycle)
board.processor.cores.core.rename.unblockCycles 3755189 # Number of cycles rename is unblocking (Cycle)
board.processor.cores.core.rename.renamedInsts 18429059 # Number of instructions processed by rename (Count)
board.processor.cores.core.rename.ROBFullEvents 1621 # Number of times rename has blocked due to ROB full (Count)
board.processor.cores.core.rename.IQFullEvents 11936 # Number of times rename has blocked due to IQ full (Count)
board.processor.cores.core.rename.LQFullEvents 3482428 # Number of times rename has blocked due to LQ full (Count)
board.processor.cores.core.rename.SQFullEvents 7892 # Number of times rename has blocked due to SQ full (Count)
board.processor.cores.core.rename.renamedOperands 35769953 # Number of destination operands rename has renamed (Count)
board.processor.cores.core.rename.lookups 67481136 # Number of register rename lookups that rename has made (Count)
board.processor.cores.core.rename.intLookups 22512389 # Number of integer rename lookups (Count)
board.processor.cores.core.rename.fpLookups 21629 # Number of floating rename lookups (Count)
board.processor.cores.core.rename.committedMaps 35403234 # Number of HB maps that are committed (Count)
board.processor.cores.core.rename.undoneMaps 366710 # Number of HB maps that are undone due to squashing (Count)
board.processor.cores.core.rename.serializing 74 # count of serializing insts renamed (Count)
board.processor.cores.core.rename.tempSerializing 59 # count of temporary serializing insts renamed (Count)
board.processor.cores.core.rename.skidInsts 8766142 # count of insts added to the skid buffer (Count)
board.processor.cores.core.rob.reads 24538746 # The number of ROB reads (Count)
board.processor.cores.core.rob.writes 36786500 # The number of ROB writes (Count)
board.processor.cores.core.thread_0.numInsts 9115640 # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps 18229832 # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.cores.core.workload.numSyscalls 34 # Number of system calls (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------