---------- Begin Simulation Statistics ----------
simSeconds 0.012707 # Number of seconds simulated (Second)
simTicks 12706524423 # Number of ticks simulated (Tick)
finalTick 12706524423 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 21.23 # Real time elapsed on the host (Second)
hostTickRate 598479513 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 1501384 # Number of bytes of host memory used (Byte)
simInsts 33954673 # Number of instructions simulated (Count)
simOps 33954687 # Number of ops (including micro ops) simulated (Count)
hostInstRate 1599260 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 1599260 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 12706524423 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 12706524423 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 12706524423 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 12706524423 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.demandHits::processor.cores.core.data 15339674 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.demandHits::total 15339674 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::processor.cores.core.data 15339674 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::total 15339674 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.demandMisses::processor.cores.core.data 65910 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.demandMisses::total 65910 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::processor.cores.core.data 65910 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::total 65910 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.demandAccesses::processor.cores.core.data 15405584 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandAccesses::total 15405584 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::processor.cores.core.data 15405584 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::total 15405584 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandMissRate::processor.cores.core.data 0.004278 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMissRate::total 0.004278 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::processor.cores.core.data 0.004278 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::total 0.004278 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.writebacks::writebacks 2020 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.writebacks::total 2020 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.replacements 65401 # number of replacements (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.hits::processor.cores.core.data 12 # number of LoadLockedReq hits (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.hits::total 12 # number of LoadLockedReq hits (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.misses::processor.cores.core.data 2 # number of LoadLockedReq misses (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.misses::total 2 # number of LoadLockedReq misses (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.accesses::processor.cores.core.data 14 # number of LoadLockedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.accesses::total 14 # number of LoadLockedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.LoadLockedReq.missRate::processor.cores.core.data 0.142857 # miss rate for LoadLockedReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.LoadLockedReq.missRate::total 0.142857 # miss rate for LoadLockedReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.hits::processor.cores.core.data 13249475 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.hits::total 13249475 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::processor.cores.core.data 63887 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::total 63887 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::processor.cores.core.data 13313362 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::total 13313362 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::processor.cores.core.data 0.004799 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::total 0.004799 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.StoreCondReq.hits::processor.cores.core.data 14 # number of StoreCondReq hits (Count)
board.cache_hierarchy.l1dcaches.StoreCondReq.hits::total 14 # number of StoreCondReq hits (Count)
board.cache_hierarchy.l1dcaches.StoreCondReq.accesses::processor.cores.core.data 14 # number of StoreCondReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.StoreCondReq.accesses::total 14 # number of StoreCondReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.SwapReq.hits::processor.cores.core.data 24 # number of SwapReq hits (Count)
board.cache_hierarchy.l1dcaches.SwapReq.hits::total 24 # number of SwapReq hits (Count)
board.cache_hierarchy.l1dcaches.SwapReq.misses::processor.cores.core.data 1 # number of SwapReq misses (Count)
board.cache_hierarchy.l1dcaches.SwapReq.misses::total 1 # number of SwapReq misses (Count)
board.cache_hierarchy.l1dcaches.SwapReq.accesses::processor.cores.core.data 25 # number of SwapReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.SwapReq.accesses::total 25 # number of SwapReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.SwapReq.missRate::processor.cores.core.data 0.040000 # miss rate for SwapReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.SwapReq.missRate::total 0.040000 # miss rate for SwapReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.hits::processor.cores.core.data 2090199 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.hits::total 2090199 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::processor.cores.core.data 2023 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::total 2023 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::processor.cores.core.data 2092222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::total 2092222 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::processor.cores.core.data 0.000967 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::total 0.000967 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.power_state.pwrStateResidencyTicks::UNDEFINED 12706524423 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 12706524423 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.tags.tagsInUse 511.367636 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches.tags.totalRefs 15405637 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.sampledRefs 65913 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.avgRefs 233.726837 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches.tags.warmupTick 3663 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches.tags.occupancies::processor.cores.core.data 511.367636 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::processor.cores.core.data 0.998765 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::total 0.998765 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::0 140 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::1 370 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::4 2 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.tagAccesses 123311009 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches.tags.dataAccesses 123311009 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 12706524423 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.demandHits::processor.cores.core.inst 38157375 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.demandHits::total 38157375 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.overallHits::processor.cores.core.inst 38157375 # number of overall hits (Count)
board.cache_hierarchy.l1icaches.overallHits::total 38157375 # number of overall hits (Count)
board.cache_hierarchy.l1icaches.demandMisses::processor.cores.core.inst 343 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.demandMisses::total 343 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::processor.cores.core.inst 343 # number of overall misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::total 343 # number of overall misses (Count)
board.cache_hierarchy.l1icaches.demandAccesses::processor.cores.core.inst 38157718 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandAccesses::total 38157718 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::processor.cores.core.inst 38157718 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::total 38157718 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandMissRate::processor.cores.core.inst 0.000009 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMissRate::total 0.000009 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::processor.cores.core.inst 0.000009 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::total 0.000009 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.writebacks::writebacks 3 # number of writebacks (Count)
board.cache_hierarchy.l1icaches.writebacks::total 3 # number of writebacks (Count)
board.cache_hierarchy.l1icaches.replacements 3 # number of replacements (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::processor.cores.core.inst 38157375 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::total 38157375 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::processor.cores.core.inst 343 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::total 343 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.accesses::processor.cores.core.inst 38157718 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.accesses::total 38157718 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.missRate::processor.cores.core.inst 0.000009 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.missRate::total 0.000009 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.power_state.pwrStateResidencyTicks::UNDEFINED 12706524423 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.prefetcher.demandMshrMisses 0 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.coverage nan # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 12706524423 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.tags.tagsInUse 255.956352 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches.tags.totalRefs 38157718 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.sampledRefs 343 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.avgRefs 111246.991254 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches.tags.occupancies::processor.cores.core.inst 255.956352 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::processor.cores.core.inst 0.499915 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::total 0.499915 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.occupanciesTaskId::1024 340 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::0 81 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::1 6 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::4 253 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ratioOccsTaskId::1024 0.664062 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches.tags.tagAccesses 305262087 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches.tags.dataAccesses 305262087 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 12706524423 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.transDist::ReadResp 64232 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WritebackDirty 2020 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WritebackClean 3 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::CleanEvict 63381 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq 2024 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp 2024 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq 64232 # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::board.memory.mem_ctrl.port 689 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::total 689 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::board.memory.mem_ctrl.port 197227 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::total 197227 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total 197916 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::board.memory.mem_ctrl.port 22144 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::total 22144 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::board.memory.mem_ctrl.port 4347712 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::total 4347712 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total 4369856 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 66256 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 66256 100.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 66256 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 12706524423 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 12706524423 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests 131660 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 65404 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl.priorityMinLatency 0.000000000000 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl.priorityMaxLatency 0.000000000000 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl.numStayReadState 0 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl.readReqs 0 # Number of read requests accepted (Count)
board.memory.mem_ctrl.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl.readBursts 0 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl.avgRdQLen 0.00 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.rdQLenPdf::0 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl.bytesReadSys 0 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl.avgRdBWSys 0.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.totGap 0 # Total gap between requests (Tick)
board.memory.mem_ctrl.avgGap nan # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.inst 21952 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.data 4218432 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::total 4240384 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::processor.cores.core.inst 21952 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::total 21952 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesWritten::writebacks 129280 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl.dram.bytesWritten::total 129280 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.inst 343 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.data 65913 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::total 66256 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numWrites::writebacks 2020 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numWrites::total 2020 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.inst 1727616 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.data 331989446 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::total 333717062 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::processor.cores.core.inst 1727616 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::total 1727616 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwWrite::writebacks 10174301 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwWrite::total 10174301 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::writebacks 10174301 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.inst 1727616 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.data 331989446 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::total 343891363 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.readBursts 0 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.totQLat 0 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl.dram.totBusLat 0 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl.dram.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl.dram.avgQLat nan # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgBusLat nan # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgMemAccLat nan # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.readRowHits 0 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl.dram.readRowHitRate nan # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl.dram.dramBytesRead 0 # Total bytes read (Byte)
board.memory.mem_ctrl.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl.dram.avgRdBW 0 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl.dram.busUtil 0.00 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl.dram.busUtilRead 0.00 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl.dram.pageHitRate nan # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl.dram.power_state.pwrStateResidencyTicks::UNDEFINED 12706524423 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl.dram.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preBackEnergy 4879305600 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.totalEnergy 4879305600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.averagePower 384.000017 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::IDLE 12706524423 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.actEnergy 0 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preEnergy 0 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.readEnergy 0 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.refreshEnergy 0 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actBackEnergy 0 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preBackEnergy 4879305600 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.totalEnergy 4879305600 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.averagePower 384.000017 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::IDLE 12706524423 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::REF 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.power_state.pwrStateResidencyTicks::UNDEFINED 12706524423 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles 38157732 # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.cpi 1.123784 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores.core.ipc 0.889851 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores.core.commitStats0.numInsts 33954692 # Number of instructions committed (thread level) (Count)
board.processor.cores.core.commitStats0.numOps 33954706 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores.core.commitStats0.cpi 1.123784 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores.core.commitStats0.ipc 0.889851 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.cores.core.commitStats0.numFpInsts 12 # Number of float instructions (Count)
board.processor.cores.core.commitStats0.numIntInsts 33944279 # Number of integer instructions (Count)
board.processor.cores.core.commitStats0.numLoadInsts 13313376 # Number of load instructions (Count)
board.processor.cores.core.commitStats0.numStoreInsts 2092266 # Number of store instructions (Count)
board.processor.cores.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores.core.commitStats0.committedInstType::No_OpClass 44 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntAlu 15508964 45.68% 45.68% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntMult 3040030 8.95% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntDiv 26 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatAdd 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCmp 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCvt 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMult 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatDiv 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMisc 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAdd 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAlu 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCmp 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCvt 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMisc 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMult 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShift 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdDiv 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAes 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::Matrix 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixMov 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixOP 0 0.00% 54.63% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemRead 13313401 39.21% 93.84% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemWrite 2092229 6.16% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemWrite 12 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::total 33954706 # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedControl::IsControl 1052786 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsDirectControl 1052583 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsIndirectControl 203 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCondControl 1042043 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsUncondControl 10743 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCall 172 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsReturn 167 # Class of control type instructions committed (Count)
board.processor.cores.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.cores.core.exec_context.thread_0.numCallsReturns 339 # Number of times a function call or return occured (Count)
board.processor.cores.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.cores.core.exec_context.thread_0.numIdleCycles 0.003003 # Number of idle cycles (Cycle)
board.processor.cores.core.exec_context.thread_0.numBusyCycles 38157731.996997 # Number of busy cycles (Cycle)
board.processor.cores.core.exec_context.thread_0.notIdleFraction 1.000000 # Percentage of non-idle cycles (Ratio)
board.processor.cores.core.exec_context.thread_0.idleFraction 0.000000 # Percentage of idle cycles (Ratio)
board.processor.cores.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.cores.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.cores.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.cores.core.executeStats0.numStoreInsts 15405642 # Number of stores executed (Count)
board.processor.cores.core.executeStats0.instRate 0 # Inst execution rate ((Count/Cycle))
board.processor.cores.core.executeStats0.numFpAluAccesses 12 # Number of float alu accesses (Count)
board.processor.cores.core.executeStats0.numFpRegReads 12 # Number of times the floating registers were read (Count)
board.processor.cores.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.cores.core.executeStats0.numIntAluAccesses 33944279 # Number of integer alu accesses (Count)
board.processor.cores.core.executeStats0.numIntRegReads 45217314 # Number of times the integer registers were read (Count)
board.processor.cores.core.executeStats0.numIntRegWrites 30809810 # Number of times the integer registers were written (Count)
board.processor.cores.core.executeStats0.numMemRefs 15405642 # Number of memory refs (Count)
board.processor.cores.core.executeStats0.numMiscRegReads 52 # Number of times the Misc registers were read (Count)
board.processor.cores.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores.core.fetchStats0.numInsts 33954692 # Number of instructions fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.numOps 33954706 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.fetchRate 0.889851 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores.core.fetchStats0.numBranches 1052786 # Number of branches fetched (Count)
board.processor.cores.core.fetchStats0.branchRate 0.027590 # Number of branch fetches per cycle (Ratio)
board.processor.cores.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores.core.mmu.dtb.readHits 0 # read hits (Count)
board.processor.cores.core.mmu.dtb.readMisses 0 # read misses (Count)
board.processor.cores.core.mmu.dtb.readAccesses 0 # read accesses (Count)
board.processor.cores.core.mmu.dtb.writeHits 0 # write hits (Count)
board.processor.cores.core.mmu.dtb.writeMisses 0 # write misses (Count)
board.processor.cores.core.mmu.dtb.writeAccesses 0 # write accesses (Count)
board.processor.cores.core.mmu.dtb.hits 0 # Total TLB (read and write) hits (Count)
board.processor.cores.core.mmu.dtb.misses 0 # Total TLB (read and write) misses (Count)
board.processor.cores.core.mmu.dtb.accesses 0 # Total TLB (read and write) accesses (Count)
board.processor.cores.core.mmu.dtb.walker.num_4kb_walks 0 # Completed page walks with 4KB pages (Count)
board.processor.cores.core.mmu.dtb.walker.num_64kb_walks 0 # Completed page walks with 64KB pages (Count)
board.processor.cores.core.mmu.dtb.walker.num_2mb_walks 0 # Completed page walks with 2MB pages (Count)
board.processor.cores.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 12706524423 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.readHits 0 # read hits (Count)
board.processor.cores.core.mmu.itb.readMisses 0 # read misses (Count)
board.processor.cores.core.mmu.itb.readAccesses 0 # read accesses (Count)
board.processor.cores.core.mmu.itb.writeHits 0 # write hits (Count)
board.processor.cores.core.mmu.itb.writeMisses 0 # write misses (Count)
board.processor.cores.core.mmu.itb.writeAccesses 0 # write accesses (Count)
board.processor.cores.core.mmu.itb.hits 0 # Total TLB (read and write) hits (Count)
board.processor.cores.core.mmu.itb.misses 0 # Total TLB (read and write) misses (Count)
board.processor.cores.core.mmu.itb.accesses 0 # Total TLB (read and write) accesses (Count)
board.processor.cores.core.mmu.itb.walker.num_4kb_walks 0 # Completed page walks with 4KB pages (Count)
board.processor.cores.core.mmu.itb.walker.num_64kb_walks 0 # Completed page walks with 64KB pages (Count)
board.processor.cores.core.mmu.itb.walker.num_2mb_walks 0 # Completed page walks with 2MB pages (Count)
board.processor.cores.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 12706524423 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON 12706524423 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.cores.core.workload.numSyscalls 14 # Number of system calls (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------