---------- Begin Simulation Statistics ----------
simSeconds 0.010227 # Number of seconds simulated (Second)
simTicks 10227433662 # Number of ticks simulated (Tick)
finalTick 10227433662 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 130.31 # Real time elapsed on the host (Second)
hostTickRate 78486563 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3609148 # Number of bytes of host memory used (Byte)
simInsts 26728147 # Number of instructions simulated (Count)
simOps 41096287 # Number of ops (including micro ops) simulated (Count)
hostInstRate 205115 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 315378 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.demandHits::processor.cores.core.data 13306633 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.demandHits::total 13306633 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::processor.cores.core.data 13306633 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::total 13306633 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.demandMisses::processor.cores.core.data 63682 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.demandMisses::total 63682 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::processor.cores.core.data 63682 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::total 63682 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.demandMissLatency::processor.cores.core.data 317747268 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMissLatency::total 317747268 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::processor.cores.core.data 317747268 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::total 317747268 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandAccesses::processor.cores.core.data 13370315 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandAccesses::total 13370315 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::processor.cores.core.data 13370315 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::total 13370315 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandMissRate::processor.cores.core.data 0.004763 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMissRate::total 0.004763 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::processor.cores.core.data 0.004763 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::total 0.004763 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::processor.cores.core.data 4989.593103 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::total 4989.593103 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::processor.cores.core.data 4989.593103 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::total 4989.593103 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.writebacks::writebacks 66221 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.writebacks::total 66221 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::processor.cores.core.data 140 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::total 140 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::processor.cores.core.data 140 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::total 140 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::processor.cores.core.data 63542 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::total 63542 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::cache_hierarchy.l1dcaches.prefetcher 4487 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::processor.cores.core.data 63542 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::total 68029 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::processor.cores.core.data 291744963 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::total 291744963 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 34655136 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::processor.cores.core.data 291744963 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::total 326400099 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::processor.cores.core.data 0.004752 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::total 0.004752 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::cache_hierarchy.l1dcaches.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::processor.cores.core.data 0.004752 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::total 0.005088 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::processor.cores.core.data 4591.372053 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::total 4591.372053 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 7723.453532 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::processor.cores.core.data 4591.372053 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::total 4797.955269 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.replacements 67773 # number of replacements (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches.prefetcher 4487 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::total 4487 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 34655136 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::total 34655136 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 7723.453532 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::total 7723.453532 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.hits::processor.cores.core.data 11214096 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.hits::total 11214096 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::processor.cores.core.data 63104 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::total 63104 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::processor.cores.core.data 306963396 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::total 306963396 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::processor.cores.core.data 11277200 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::total 11277200 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::processor.cores.core.data 0.005596 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::total 0.005596 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::processor.cores.core.data 4864.404729 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::total 4864.404729 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.mshrHits::processor.cores.core.data 112 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrHits::total 112 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::processor.cores.core.data 62992 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::total 62992 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::processor.cores.core.data 281352033 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::total 281352033 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::processor.cores.core.data 0.005586 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::total 0.005586 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::processor.cores.core.data 4466.472457 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::total 4466.472457 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.hits::processor.cores.core.data 2092537 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.hits::total 2092537 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::processor.cores.core.data 578 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::total 578 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::processor.cores.core.data 10783872 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::total 10783872 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::processor.cores.core.data 2093115 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::total 2093115 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::processor.cores.core.data 0.000276 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::total 0.000276 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::processor.cores.core.data 18657.217993 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::total 18657.217993 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.mshrHits::processor.cores.core.data 28 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrHits::total 28 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::processor.cores.core.data 550 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::total 550 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::processor.cores.core.data 10392930 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::total 10392930 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::processor.cores.core.data 0.000263 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::total 0.000263 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::processor.cores.core.data 18896.236364 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::total 18896.236364 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.prefetcher.demandMshrMisses 63542 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIssued 12192 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUnused 1862 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUseful 2594 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches.prefetcher.accuracy 0.212762 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.coverage 0.039222 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInCache 7602 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInMSHR 103 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfLate 7705 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIdentified 12192 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfSpanPage 568 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulSpanPage 397 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.tags.tagsInUse 255.679171 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches.tags.totalRefs 13374662 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.sampledRefs 68029 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.avgRefs 196.602361 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches.tags.warmupTick 132534 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches.tags.occupancies::cache_hierarchy.l1dcaches.prefetcher 14.751305 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.occupancies::processor.cores.core.data 240.927866 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::cache_hierarchy.l1dcaches.prefetcher 0.057622 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::processor.cores.core.data 0.941124 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::total 0.998747 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1022 189 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1024 67 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1022::0 43 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1022::1 146 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::0 63 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::1 2 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::4 2 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1022 0.738281 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1024 0.261719 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.tagAccesses 107030549 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches.tags.dataAccesses 107030549 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.demandHits::processor.cores.core.inst 3155320 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.demandHits::total 3155320 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.overallHits::processor.cores.core.inst 3155320 # number of overall hits (Count)
board.cache_hierarchy.l1icaches.overallHits::total 3155320 # number of overall hits (Count)
board.cache_hierarchy.l1icaches.demandMisses::processor.cores.core.inst 735 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.demandMisses::total 735 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::processor.cores.core.inst 735 # number of overall misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::total 735 # number of overall misses (Count)
board.cache_hierarchy.l1icaches.demandMissLatency::processor.cores.core.inst 38241387 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMissLatency::total 38241387 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::processor.cores.core.inst 38241387 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::total 38241387 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandAccesses::processor.cores.core.inst 3156055 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandAccesses::total 3156055 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::processor.cores.core.inst 3156055 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::total 3156055 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandMissRate::processor.cores.core.inst 0.000233 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMissRate::total 0.000233 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::processor.cores.core.inst 0.000233 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::total 0.000233 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMissLatency::processor.cores.core.inst 52029.097959 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMissLatency::total 52029.097959 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::processor.cores.core.inst 52029.097959 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::total 52029.097959 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.demandMshrHits::processor.cores.core.inst 92 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1icaches.demandMshrHits::total 92 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1icaches.overallMshrHits::processor.cores.core.inst 92 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1icaches.overallMshrHits::total 92 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1icaches.demandMshrMisses::processor.cores.core.inst 643 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMisses::total 643 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::processor.cores.core.inst 643 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::total 643 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::processor.cores.core.inst 34541424 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::total 34541424 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::processor.cores.core.inst 34541424 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::total 34541424 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissRate::processor.cores.core.inst 0.000204 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMshrMissRate::total 0.000204 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::processor.cores.core.inst 0.000204 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::total 0.000204 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::processor.cores.core.inst 53719.166407 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::total 53719.166407 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::processor.cores.core.inst 53719.166407 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::total 53719.166407 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.replacements 386 # number of replacements (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::processor.cores.core.inst 3155320 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::total 3155320 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::processor.cores.core.inst 735 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::total 735 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::processor.cores.core.inst 38241387 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::total 38241387 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.accesses::processor.cores.core.inst 3156055 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.accesses::total 3156055 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.missRate::processor.cores.core.inst 0.000233 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.missRate::total 0.000233 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::processor.cores.core.inst 52029.097959 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::total 52029.097959 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.mshrHits::processor.cores.core.inst 92 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrHits::total 92 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::processor.cores.core.inst 643 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::total 643 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::processor.cores.core.inst 34541424 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::total 34541424 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::processor.cores.core.inst 0.000204 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::total 0.000204 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::processor.cores.core.inst 53719.166407 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::total 53719.166407 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.prefetcher.demandMshrMisses 643 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.tags.tagsInUse 255.785728 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches.tags.totalRefs 3155962 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.sampledRefs 642 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.avgRefs 4915.828660 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches.tags.warmupTick 69930 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches.tags.occupancies::processor.cores.core.inst 255.785728 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::processor.cores.core.inst 0.999163 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::total 0.999163 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.occupanciesTaskId::1024 256 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::0 123 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::1 4 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::4 129 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches.tags.tagAccesses 25249082 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches.tags.dataAccesses 25249082 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2bus.transDist::ReadResp 68121 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::WritebackDirty 66221 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::CleanEvict 1938 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::HardPFReq 2063 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::ReadExReq 550 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::ReadExResp 550 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::ReadSharedReq 68122 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 1671 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 203831 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount::total 205502 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 41088 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 8592000 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize::total 8633088 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.snoops 2063 # Total snoops (Count)
board.cache_hierarchy.l2bus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.l2bus.snoopFanout::samples 70735 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::mean 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::stdev 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::0 70735 100.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::total 70735 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2bus.reqLayer0.occupancy 90411442 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer0.occupancy 641358 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer1.occupancy 67960971 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.snoop_filter.totRequests 136831 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2bus.snoop_filter.hitSingleRequests 68159 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2bus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2bus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2bus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2bus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2cache.demandHits::cache_hierarchy.l1dcaches.prefetcher 4309 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores.core.inst 15 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores.core.data 63278 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::total 67602 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.overallHits::cache_hierarchy.l1dcaches.prefetcher 4309 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores.core.inst 15 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores.core.data 63278 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::total 67602 # number of overall hits (Count)
board.cache_hierarchy.l2cache.demandMisses::cache_hierarchy.l1dcaches.prefetcher 178 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores.core.inst 628 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores.core.data 264 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::total 1070 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.overallMisses::cache_hierarchy.l1dcaches.prefetcher 178 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::processor.cores.core.inst 628 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::processor.cores.core.data 264 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::total 1070 # number of overall misses (Count)
board.cache_hierarchy.l2cache.demandMissLatency::cache_hierarchy.l1dcaches.prefetcher 12697851 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores.core.inst 34056243 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores.core.data 17552097 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::total 64306191 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::cache_hierarchy.l1dcaches.prefetcher 12697851 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores.core.inst 34056243 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores.core.data 17552097 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::total 64306191 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.demandAccesses::cache_hierarchy.l1dcaches.prefetcher 4487 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores.core.inst 643 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores.core.data 63542 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::total 68672 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::cache_hierarchy.l1dcaches.prefetcher 4487 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores.core.inst 643 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores.core.data 63542 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::total 68672 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandMissRate::cache_hierarchy.l1dcaches.prefetcher 0.039670 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores.core.inst 0.976672 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores.core.data 0.004155 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::total 0.015581 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::cache_hierarchy.l1dcaches.prefetcher 0.039670 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores.core.inst 0.976672 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores.core.data 0.004155 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::total 0.015581 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.demandAvgMissLatency::cache_hierarchy.l1dcaches.prefetcher 71336.241573 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores.core.inst 54229.686306 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores.core.data 66485.215909 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::total 60099.243925 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::cache_hierarchy.l1dcaches.prefetcher 71336.241573 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores.core.inst 54229.686306 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores.core.data 66485.215909 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::total 60099.243925 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2cache.demandMshrHits::cache_hierarchy.l1dcaches.prefetcher 136 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::total 136 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::cache_hierarchy.l1dcaches.prefetcher 136 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::total 136 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::cache_hierarchy.l1dcaches.prefetcher 42 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores.core.inst 628 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores.core.data 264 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::total 934 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::cache_hierarchy.l1dcaches.prefetcher 42 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::cache_hierarchy.l2cache.prefetcher 1832 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores.core.inst 628 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores.core.data 264 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::total 2766 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 4275051 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores.core.inst 33847452 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores.core.data 17464185 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::total 55586688 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 4275051 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::cache_hierarchy.l2cache.prefetcher 106180919 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores.core.inst 33847452 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores.core.data 17464185 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::total 161767607 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissRate::cache_hierarchy.l1dcaches.prefetcher 0.009360 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores.core.inst 0.976672 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores.core.data 0.004155 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::total 0.013601 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::cache_hierarchy.l1dcaches.prefetcher 0.009360 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::cache_hierarchy.l2cache.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores.core.inst 0.976672 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores.core.data 0.004155 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::total 0.040278 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 101786.928571 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores.core.inst 53897.216561 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores.core.data 66152.215909 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::total 59514.655246 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 101786.928571 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::cache_hierarchy.l2cache.prefetcher 57959.016921 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores.core.inst 53897.216561 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores.core.data 66152.215909 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::total 58484.312003 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.replacements 0 # number of replacements (Count)
board.cache_hierarchy.l2cache.HardPFReq.mshrMisses::cache_hierarchy.l2cache.prefetcher 1832 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l2cache.HardPFReq.mshrMisses::total 1832 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l2cache.HardPFReq.mshrMissLatency::cache_hierarchy.l2cache.prefetcher 106180919 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.HardPFReq.mshrMissLatency::total 106180919 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.HardPFReq.mshrMissRate::cache_hierarchy.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l2cache.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l2cache.HardPFReq.avgMshrMissLatency::cache_hierarchy.l2cache.prefetcher 57959.016921 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.HardPFReq.avgMshrMissLatency::total 57959.016921 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.hits::processor.cores.core.data 435 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.hits::total 435 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::processor.cores.core.data 115 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::total 115 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::processor.cores.core.data 8429229 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::total 8429229 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.accesses::processor.cores.core.data 550 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.accesses::total 550 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.missRate::processor.cores.core.data 0.209091 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.missRate::total 0.209091 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::processor.cores.core.data 73297.643478 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::total 73297.643478 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::processor.cores.core.data 115 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::total 115 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::processor.cores.core.data 8390934 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::total 8390934 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::processor.cores.core.data 0.209091 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::total 0.209091 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::processor.cores.core.data 72964.643478 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::total 72964.643478 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.hits::cache_hierarchy.l1dcaches.prefetcher 4309 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.hits::processor.cores.core.inst 15 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.hits::processor.cores.core.data 62843 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.hits::total 67167 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.misses::cache_hierarchy.l1dcaches.prefetcher 178 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.misses::processor.cores.core.inst 628 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.misses::processor.cores.core.data 149 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.misses::total 955 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.missLatency::cache_hierarchy.l1dcaches.prefetcher 12697851 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.missLatency::processor.cores.core.inst 34056243 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.missLatency::processor.cores.core.data 9122868 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.missLatency::total 55876962 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.accesses::cache_hierarchy.l1dcaches.prefetcher 4487 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.accesses::processor.cores.core.inst 643 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.accesses::processor.cores.core.data 62992 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.accesses::total 68122 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.missRate::cache_hierarchy.l1dcaches.prefetcher 0.039670 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.missRate::processor.cores.core.inst 0.976672 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.missRate::processor.cores.core.data 0.002365 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.missRate::total 0.014019 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::cache_hierarchy.l1dcaches.prefetcher 71336.241573 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores.core.inst 54229.686306 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores.core.data 61227.302013 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::total 58509.907853 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.mshrHits::cache_hierarchy.l1dcaches.prefetcher 136 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrHits::total 136 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::cache_hierarchy.l1dcaches.prefetcher 42 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores.core.inst 628 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores.core.data 149 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::total 819 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 4275051 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores.core.inst 33847452 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores.core.data 9073251 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::total 47195754 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::cache_hierarchy.l1dcaches.prefetcher 0.009360 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores.core.inst 0.976672 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores.core.data 0.002365 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::total 0.012023 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 101786.928571 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.inst 53897.216561 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.data 60894.302013 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::total 57626.073260 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.WritebackDirty.hits::writebacks 66221 # number of WritebackDirty hits (Count)
board.cache_hierarchy.l2cache.WritebackDirty.hits::total 66221 # number of WritebackDirty hits (Count)
board.cache_hierarchy.l2cache.WritebackDirty.accesses::writebacks 66221 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.WritebackDirty.accesses::total 66221 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2cache.prefetcher.demandMshrMisses 934 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2cache.prefetcher.pfIssued 6880 # number of hwpf issued (Count)
board.cache_hierarchy.l2cache.prefetcher.pfUseful 1692 # number of useful prefetch (Count)
board.cache_hierarchy.l2cache.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2cache.prefetcher.accuracy 0.245930 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2cache.prefetcher.coverage 0.644326 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2cache.prefetcher.pfHitInCache 4869 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2cache.prefetcher.pfHitInMSHR 179 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2cache.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2cache.prefetcher.pfLate 5048 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2cache.prefetcher.pfIdentified 7299 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2cache.prefetcher.pfBufferHit 277 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2cache.prefetcher.pfRemovedDemand 104 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2cache.prefetcher.pfSpanPage 353 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2cache.prefetcher.pfUsefulSpanPage 263 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2cache.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2cache.tags.tagsInUse 2302.403197 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2cache.tags.totalRefs 138526 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2cache.tags.sampledRefs 2765 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2cache.tags.avgRefs 50.099819 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2cache.tags.warmupTick 69264 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2cache.tags.occupancies::cache_hierarchy.l1dcaches.prefetcher 36.607949 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::cache_hierarchy.l2cache.prefetcher 1532.237821 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores.core.inst 502.239433 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores.core.data 231.317994 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::cache_hierarchy.l1dcaches.prefetcher 0.008937 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::cache_hierarchy.l2cache.prefetcher 0.374081 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores.core.inst 0.122617 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores.core.data 0.056474 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::total 0.562110 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.occupanciesTaskId::1022 1874 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2cache.tags.occupanciesTaskId::1024 891 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1022::2 49 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1022::3 541 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1022::4 1284 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1024::0 145 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1024::1 6 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1024::2 1 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1024::3 9 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1024::4 730 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ratioOccsTaskId::1022 0.457520 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2cache.tags.ratioOccsTaskId::1024 0.217529 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2cache.tags.tagAccesses 2192061 # Number of tag accesses (Count)
board.cache_hierarchy.l2cache.tags.dataAccesses 2192061 # Number of data accesses (Count)
board.cache_hierarchy.l2cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.transDist::ReadResp 2650 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq 115 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp 115 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq 2650 # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2cache.mem_side_port::board.memory.mem_ctrl.port 5530 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2cache.mem_side_port::total 5530 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total 5530 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2cache.mem_side_port::board.memory.mem_ctrl.port 176960 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2cache.mem_side_port::total 176960 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total 176960 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops 0 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 2765 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 2765 100.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 2765 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy 1434108 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer2.occupancy 2358189 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer2.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests 2765 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl.avgPriority_cache_hierarchy.l1dcaches.prefetcher::samples 42.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_cache_hierarchy.l2cache.prefetcher::samples 1832.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.inst::samples 627.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.data::samples 264.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.priorityMinLatency 0.000000017492 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl.priorityMaxLatency 0.000000757044 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl.numStayReadState 8001 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl.numStayWriteState 0 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl.readReqs 2765 # Number of read requests accepted (Count)
board.memory.mem_ctrl.writeReqs 0 # Number of write requests accepted (Count)
board.memory.mem_ctrl.readBursts 2765 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl.writeBursts 0 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl.servicedByWrQ 0 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl.avgRdQLen 1.16 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::6 2765 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.rdQLenPdf::0 1693 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::1 691 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::2 96 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::3 67 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::4 50 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::5 45 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::6 37 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::7 37 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::8 36 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::9 11 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::10 2 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::64 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::65 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::66 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::67 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::68 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::69 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::70 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::71 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::72 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl.bytesReadSys 176960 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl.avgRdBWSys 17302483.28644696 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.avgWrBWSys 0.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.totGap 10227383046 # Total gap between requests (Tick)
board.memory.mem_ctrl.avgGap 3698872.71 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl.requestorReadBytes::cache_hierarchy.l1dcaches.prefetcher 2688 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::cache_hierarchy.l2cache.prefetcher 117248 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.inst 40128 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.data 16896 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadRate::cache_hierarchy.l1dcaches.prefetcher 262822.530933371512 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::cache_hierarchy.l2cache.prefetcher 11464068.492141349241 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.inst 3923564.926076760516 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.data 1652027.337295478210 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadAccesses::cache_hierarchy.l1dcaches.prefetcher 42 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::cache_hierarchy.l2cache.prefetcher 1832 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.inst 627 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.data 264 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadTotalLat::cache_hierarchy.l1dcaches.prefetcher 3132737 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::cache_hierarchy.l2cache.prefetcher 62481546 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.inst 16824140 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.data 10289851 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadAvgLat::cache_hierarchy.l1dcaches.prefetcher 74588.98 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::cache_hierarchy.l2cache.prefetcher 34105.65 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.inst 26832.76 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.data 38976.71 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.dram.bytesRead::cache_hierarchy.l1dcaches.prefetcher 2688 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::cache_hierarchy.l2cache.prefetcher 117248 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.inst 40128 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.data 16896 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::total 176960 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::processor.cores.core.inst 40128 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::total 40128 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.numReads::cache_hierarchy.l1dcaches.prefetcher 42 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::cache_hierarchy.l2cache.prefetcher 1832 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.inst 627 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.data 264 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::total 2765 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.bwRead::cache_hierarchy.l1dcaches.prefetcher 262823 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::cache_hierarchy.l2cache.prefetcher 11464068 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.inst 3923565 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.data 1652027 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::total 17302483 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::processor.cores.core.inst 3923565 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::total 3923565 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::cache_hierarchy.l1dcaches.prefetcher 262823 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::cache_hierarchy.l2cache.prefetcher 11464068 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.inst 3923565 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.data 1652027 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::total 17302483 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.readBursts 2765 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl.dram.writeBursts 0 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::0 158 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::1 100 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::2 65 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::3 77 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::4 104 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::5 128 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::6 128 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::7 143 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::8 164 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::9 136 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::10 243 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::11 152 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::12 140 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::13 140 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::14 152 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::15 160 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::16 140 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::17 148 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::18 97 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::19 21 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::20 27 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::21 14 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::22 3 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::24 1 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::25 12 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::26 19 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::27 10 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::28 4 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::29 8 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::30 22 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::31 49 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::0 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::1 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::2 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::3 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::4 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::5 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::6 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::7 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::8 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::9 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::10 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::11 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::12 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::13 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::14 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::15 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::16 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::17 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::18 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::19 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::20 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::21 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::22 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::23 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::24 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::25 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::26 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::27 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::28 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::29 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::30 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::31 0 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.totQLat 44362894 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl.dram.totBusLat 9212980 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl.dram.totMemAccLat 92728274 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl.dram.avgQLat 16044.45 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgBusLat 3332.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgMemAccLat 33536.45 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.readRowHits 1948 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl.dram.writeRowHits 0 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl.dram.readRowHitRate 70.45 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl.dram.writeRowHitRate nan # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl.dram.bytesPerActivate::samples 802 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::mean 217.296758 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::gmean 114.008657 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::stdev 308.351914 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::0-127 555 69.20% 69.20% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::128-255 77 9.60% 78.80% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::256-383 26 3.24% 82.04% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::384-511 13 1.62% 83.67% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::512-639 25 3.12% 86.78% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::640-767 13 1.62% 88.40% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::768-895 8 1.00% 89.40% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::896-1023 9 1.12% 90.52% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::1024-1151 76 9.48% 100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::total 802 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.dramBytesRead 176960 # Total bytes read (Byte)
board.memory.mem_ctrl.dram.dramBytesWritten 0 # Total bytes written (Byte)
board.memory.mem_ctrl.dram.avgRdBW 17.302483 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.avgWrBW 0 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl.dram.busUtil 0.09 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl.dram.busUtilRead 0.09 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl.dram.busUtilWrite 0.00 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl.dram.pageHitRate 70.45 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl.dram.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl.dram.rank0.actEnergy 801519.264000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preEnergy 1390213.692000 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.readEnergy 6006956.256000 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.refreshEnergy 887398336.624806 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actBackEnergy 768849681.062396 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preBackEnergy 2807455000.627223 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.totalEnergy 4471901707.526413 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.averagePower 437.245731 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::IDLE 8579308984 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::REF 459550000 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT 1188574678 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.actEnergy 472490.928000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preEnergy 817610.824800 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.readEnergy 1577168.880000 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.writeEnergy 0 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.refreshEnergy 887398336.624806 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actBackEnergy 678411650.750380 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preBackEnergy 2869889376.883173 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.totalEnergy 4438566634.891133 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.averagePower 433.986353 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::IDLE 8771255299 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::REF 459550000 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT 996628363 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles 30713015 # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.cpi 1.149089 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores.core.ipc 0.870255 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores.core.instsAdded 41327387 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.cores.core.instsIssued 41214729 # Number of instructions issued (Count)
board.processor.cores.core.squashedInstsIssued 698 # Number of squashed instructions issued (Count)
board.processor.cores.core.squashedInstsExamined 231093 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
board.processor.cores.core.squashedOperandsExamined 433689 # Number of squashed operands that are examined and possibly removed from graph (Count)
board.processor.cores.core.numIssuedDist::samples 30645887 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::mean 1.344870 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::stdev 0.778564 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::0 5826212 19.01% 19.01% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::1 8424621 27.49% 46.50% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::2 16395054 53.50% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::max_value 2 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::total 30645887 # Number of insts issued each cycle (Count)
board.processor.cores.core.statFuBusy::No_OpClass 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntAlu 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntMult 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntDiv 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatAdd 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCmp 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCvt 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMult 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatDiv 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMisc 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAdd 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAddAcc 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAlu 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCmp 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCvt 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMisc 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMult 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMultAcc 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShift 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShiftAcc 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdDiv 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSqrt 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAdd 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAlu 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCmp 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCvt 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatDiv 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMisc 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMult 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMatMultAcc 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatSqrt 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAlu 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceAdd 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceCmp 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAes 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAesMix 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash2 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash2 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma2 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma3 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdPredAlu 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::Matrix 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MatrixMov 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MatrixOP 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemRead 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemWrite 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemRead 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemWrite 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IprAccess 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::InstPrefetch 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideLoad 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideStore 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideMaskLoad 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideMaskStore 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStridedLoad 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStridedStore 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdIndexedLoad 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdIndexedStore 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdWholeRegisterLoad 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdWholeRegisterStore 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStrideSegmentedLoad 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStrideSegmentedStore 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdExt 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatExt 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdConfig 0 # attempts to use FU when none available (Count)
board.processor.cores.core.statIssuedInstType_0::No_OpClass 580 0.00% 0.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntAlu 22693113 55.06% 55.06% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntMult 3040040 7.38% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntDiv 57 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatAdd 147 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCmp 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCvt 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMult 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatDiv 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMisc 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatSqrt 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAdd 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAlu 204 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCmp 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCvt 86 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMisc 271 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMult 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShift 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdDiv 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSqrt 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAes 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAesMix 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::Matrix 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MatrixMov 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MatrixOP 0 0.00% 62.44% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemRead 13386537 32.48% 94.92% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemWrite 2093101 5.08% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemRead 105 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemWrite 488 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::total 41214729 # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.issueRate 1.341930 # Inst issue rate ((Count/Cycle))
board.processor.cores.core.fuBusy 0 # FU busy when requested (Count)
board.processor.cores.core.fuBusyRate 0 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.cores.core.intInstQueueReads 113073132 # Number of integer instruction queue reads (Count)
board.processor.cores.core.intInstQueueWrites 41556944 # Number of integer instruction queue writes (Count)
board.processor.cores.core.intInstQueueWakeupAccesses 41191741 # Number of integer instruction queue wakeup accesses (Count)
board.processor.cores.core.fpInstQueueReads 2909 # Number of floating instruction queue reads (Count)
board.processor.cores.core.fpInstQueueWrites 1554 # Number of floating instruction queue writes (Count)
board.processor.cores.core.fpInstQueueWakeupAccesses 1417 # Number of floating instruction queue wakeup accesses (Count)
board.processor.cores.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.cores.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.cores.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.cores.core.intAluAccesses 41212698 # Number of integer alu accesses (Count)
board.processor.cores.core.fpAluAccesses 1451 # Number of floating point alu accesses (Count)
board.processor.cores.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.numRecvResp 13370315 # Number of received responses (Count)
board.processor.cores.core.numRecvRespBytes 65872676 # Number of received response bytes (Byte)
board.processor.cores.core.recvRespAvgBW 2.14 # Average bandwidth of received responses ((Byte/Cycle))
board.processor.cores.core.recvRespAvgSize 4.93 # Average packet size per received response ((Byte/Count))
board.processor.cores.core.recvRespAvgRate 0.44 # Average rate of received responses per cycle ((Count/Cycle))
board.processor.cores.core.recvRespAvgRetryRate 0.00 # Average retry rate per received response ((Count/Count))
board.processor.cores.core.numSendRetryResp 0 # Number of retry responses sent (Count)
board.processor.cores.core.numSquashedInsts 10795 # Number of squashed instructions skipped in execute (Count)
board.processor.cores.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.cores.core.timesIdled 513 # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
board.processor.cores.core.idleCycles 67128 # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
board.processor.cores.core.MemDepUnit__0.insertedLoads 13397269 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.insertedStores 2093821 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingLoads 4053227 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingStores 1009999 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.branchPred.lookups_0::NoBranch 0 0.00% 0.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::Return 348 0.03% 0.03% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallDirect 306 0.03% 0.06% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallIndirect 115 0.01% 0.07% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectCond 1054411 98.89% 98.97% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectUncond 10841 1.02% 99.98% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectCond 0 0.00% 99.98% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectUncond 189 0.02% 100.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::total 1066210 # Number of BP lookups (Count)
board.processor.cores.core.branchPred.squashes_0::NoBranch 0 0.00% 0.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::Return 89 0.74% 0.74% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallDirect 140 1.17% 1.92% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallIndirect 18 0.15% 2.07% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectCond 11256 94.21% 96.28% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectUncond 342 2.86% 99.14% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectCond 0 0.00% 99.14% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectUncond 103 0.86% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::total 11948 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.corrected_0::NoBranch 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::Return 0 0.00% 0.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallDirect 148 1.32% 1.32% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallIndirect 55 0.49% 1.82% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectCond 10764 96.28% 98.09% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectUncond 134 1.20% 99.29% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectCond 0 0.00% 99.29% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectUncond 79 0.71% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::total 11180 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.committed_0::NoBranch 0 0.00% 0.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::Return 259 0.02% 0.02% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::CallDirect 166 0.02% 0.04% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::CallIndirect 97 0.01% 0.05% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::DirectCond 1043154 98.95% 99.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::DirectUncond 10499 1.00% 99.99% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::IndirectCond 0 0.00% 99.99% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::IndirectUncond 86 0.01% 100.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::total 1054261 # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.mispredicted_0::NoBranch 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::Return 0 0.00% 0.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallDirect 106 0.96% 0.96% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallIndirect 54 0.49% 1.45% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectCond 10737 97.03% 98.47% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectUncond 91 0.82% 99.30% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectCond 0 0.00% 99.30% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectUncond 78 0.70% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::total 11066 # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::NoBranch 0 0.00% 0.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::Return 0 0.00% 0.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::CallDirect 0 0.00% 0.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::CallIndirect 0 0.00% 0.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::DirectCond 10456 100.00% 100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::DirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::IndirectCond 0 0.00% 100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::IndirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::total 10456 # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::NoBranch 0 0.00% 0.00% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::Return 0 0.00% 0.00% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::CallDirect 106 17.38% 17.38% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::CallIndirect 54 8.85% 26.23% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::DirectCond 281 46.07% 72.30% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::DirectUncond 91 14.92% 87.21% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::IndirectCond 0 0.00% 87.21% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::IndirectUncond 78 12.79% 100.00% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::total 610 # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.targetProvider_0::NoTarget 3139 0.29% 0.29% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::BTB 1062663 99.67% 99.96% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::RAS 348 0.03% 99.99% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::Indirect 60 0.01% 100.00% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::total 1066210 # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetWrong_0::NoBranch 830 7.43% 7.43% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::Return 10342 92.52% 99.95% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallDirect 0 0.00% 99.95% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallIndirect 6 0.05% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::total 11178 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.condPredicted 1054411 # Number of conditional branches predicted (Count)
board.processor.cores.core.branchPred.condPredictedTaken 1052219 # Number of conditional branches predicted as taken (Count)
board.processor.cores.core.branchPred.condIncorrect 11180 # Number of conditional branches incorrect (Count)
board.processor.cores.core.branchPred.predTakenBTBMiss 389 # Number of branches predicted taken but missed in BTB (Count)
board.processor.cores.core.branchPred.BTBLookups 1066210 # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.BTBUpdates 703 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.BTBHits 1062982 # Number of BTB hits (Count)
board.processor.cores.core.branchPred.BTBHitRatio 0.996972 # BTB Hit Ratio (Ratio)
board.processor.cores.core.branchPred.BTBMispredicted 582 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.cores.core.branchPred.indirectLookups 304 # Number of indirect predictor lookups. (Count)
board.processor.cores.core.branchPred.indirectHits 60 # Number of indirect target hits. (Count)
board.processor.cores.core.branchPred.indirectMisses 244 # Number of indirect misses. (Count)
board.processor.cores.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.cores.core.branchPred.btb.lookups::NoBranch 0 0.00% 0.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::Return 348 0.03% 0.03% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallDirect 306 0.03% 0.06% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallIndirect 115 0.01% 0.07% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectCond 1054411 98.89% 98.97% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectUncond 10841 1.02% 99.98% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectCond 0 0.00% 99.98% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectUncond 189 0.02% 100.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::total 1066210 # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.misses::NoBranch 0 0.00% 0.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::Return 348 10.78% 10.78% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallDirect 193 5.98% 16.76% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallIndirect 115 3.56% 20.32% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectCond 2234 69.21% 89.53% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectUncond 149 4.62% 94.14% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectCond 0 0.00% 94.14% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectUncond 189 5.86% 100.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::total 3228 # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.updates::NoBranch 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::Return 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallDirect 148 21.05% 21.05% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallIndirect 0 0.00% 21.05% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectCond 421 59.89% 80.94% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectUncond 134 19.06% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectCond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectUncond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::total 703 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.mispredict::NoBranch 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::Return 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallDirect 148 21.05% 21.05% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallIndirect 0 0.00% 21.05% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectCond 421 59.89% 80.94% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectUncond 134 19.06% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectCond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectUncond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::total 703 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.branchPred.indirectBranchPred.lookups 304 # Number of lookups (Count)
board.processor.cores.core.branchPred.indirectBranchPred.hits 60 # Number of hits of a tag (Count)
board.processor.cores.core.branchPred.indirectBranchPred.misses 244 # Number of misses (Count)
board.processor.cores.core.branchPred.indirectBranchPred.targetRecords 134 # Number of targets that where recorded/installed in the cache (Count)
board.processor.cores.core.branchPred.indirectBranchPred.indirectRecords 438 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.cores.core.branchPred.indirectBranchPred.speculativeOverflows 1 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.cores.core.branchPred.ras.pushes 510 # Number of times a PC was pushed onto the RAS (Count)
board.processor.cores.core.branchPred.ras.pops 506 # Number of times a PC was poped from the RAS (Count)
board.processor.cores.core.branchPred.ras.squashes 247 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.cores.core.branchPred.ras.used 259 # Number of times the RAS is the provider (Count)
board.processor.cores.core.branchPred.ras.correct 259 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.cores.core.branchPred.ras.incorrect 0 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.cores.core.commit.commitSquashedInsts 230306 # The number of squashed insts skipped by commit (Count)
board.processor.cores.core.commit.branchMispredicts 10926 # The number of times a branch was mispredicted (Count)
board.processor.cores.core.commit.numCommittedDist::samples 30614130 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::mean 1.342396 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::stdev 0.745448 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::0 5059481 16.53% 16.53% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::1 10013011 32.71% 49.23% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::2 15541638 50.77% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::max_value 2 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::total 30614130 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.cores.core.commit.membars 0 # Number of memory barriers committed (Count)
board.processor.cores.core.commit.functionCalls 263 # Number of function calls committed. (Count)
board.processor.cores.core.commit.committedInstType_0::No_OpClass 341 0.00% 0.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntAlu 22647379 55.11% 55.11% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntMult 3040040 7.40% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntDiv 56 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatAdd 146 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCmp 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCvt 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMult 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatDiv 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMisc 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatSqrt 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAdd 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAlu 160 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCmp 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCvt 86 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMisc 270 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMult 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShift 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdDiv 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSqrt 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAes 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAesMix 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::Matrix 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MatrixMov 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MatrixOP 0 0.00% 62.51% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemRead 13314606 32.40% 94.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemWrite 2092642 5.09% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemRead 88 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemWrite 473 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::total 41096287 # Class of committed instruction (Count)
board.processor.cores.core.commit.commitEligibleSamples 15541638 # number cycles where commit BW limit reached (Cycle)
board.processor.cores.core.commitStats0.numInsts 26728147 # Number of instructions committed (thread level) (Count)
board.processor.cores.core.commitStats0.numOps 41096287 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores.core.commitStats0.numInstsNotNOP 26728147 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores.core.commitStats0.numOpsNotNOP 41096287 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores.core.commitStats0.cpi 1.149089 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores.core.commitStats0.ipc 0.870255 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores.core.commitStats0.numMemRefs 15407809 # Number of memory references committed (Count)
board.processor.cores.core.commitStats0.numFpInsts 1372 # Number of float instructions (Count)
board.processor.cores.core.commitStats0.numIntInsts 41095237 # Number of integer instructions (Count)
board.processor.cores.core.commitStats0.numLoadInsts 13314694 # Number of load instructions (Count)
board.processor.cores.core.commitStats0.numStoreInsts 2093115 # Number of store instructions (Count)
board.processor.cores.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores.core.commitStats0.committedInstType::No_OpClass 341 0.00% 0.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntAlu 22647379 55.11% 55.11% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntMult 3040040 7.40% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntDiv 56 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatAdd 146 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCmp 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCvt 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMult 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatDiv 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMisc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAdd 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAlu 160 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCmp 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCvt 86 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMisc 270 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMult 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShift 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdDiv 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAes 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::Matrix 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixMov 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixOP 0 0.00% 62.51% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemRead 13314606 32.40% 94.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemWrite 2092642 5.09% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemRead 88 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemWrite 473 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::total 41096287 # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedControl::IsControl 1054261 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsDirectControl 1053819 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsIndirectControl 442 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCondControl 1043154 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsUncondControl 11107 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCall 263 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsReturn 259 # Class of control type instructions committed (Count)
board.processor.cores.core.decode.idleCycles 3051520 # Number of cycles decode is idle (Cycle)
board.processor.cores.core.decode.blockedCycles 6887255 # Number of cycles decode is blocked (Cycle)
board.processor.cores.core.decode.runCycles 14675865 # Number of cycles decode is running (Cycle)
board.processor.cores.core.decode.unblockCycles 6020254 # Number of cycles decode is unblocking (Cycle)
board.processor.cores.core.decode.squashCycles 10993 # Number of cycles decode is squashing (Cycle)
board.processor.cores.core.decode.branchResolved 1052546 # Number of times decode resolved a branch (Count)
board.processor.cores.core.decode.branchMispred 288 # Number of times decode detected a branch misprediction (Count)
board.processor.cores.core.decode.decodedInsts 41390357 # Number of instructions handled by decode (Count)
board.processor.cores.core.decode.squashedInsts 489 # Number of squashed instructions handled by decode (Count)
board.processor.cores.core.executeStats0.numInsts 41203932 # Number of executed instructions (Count)
board.processor.cores.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores.core.executeStats0.numBranches 1054701 # Number of branches executed (Count)
board.processor.cores.core.executeStats0.numLoadInsts 13376608 # Number of load instructions executed (Count)
board.processor.cores.core.executeStats0.numStoreInsts 2093513 # Number of stores executed (Count)
board.processor.cores.core.executeStats0.instRate 1.341579 # Inst execution rate ((Count/Cycle))
board.processor.cores.core.executeStats0.numCCRegReads 7279264 # Number of times the CC registers were read (Count)
board.processor.cores.core.executeStats0.numCCRegWrites 17453356 # Number of times the CC registers were written (Count)
board.processor.cores.core.executeStats0.numFpRegReads 1744 # Number of times the floating registers were read (Count)
board.processor.cores.core.executeStats0.numFpRegWrites 853 # Number of times the floating registers were written (Count)
board.processor.cores.core.executeStats0.numIntRegReads 61625739 # Number of times the integer registers were read (Count)
board.processor.cores.core.executeStats0.numIntRegWrites 37000685 # Number of times the integer registers were written (Count)
board.processor.cores.core.executeStats0.numMemRefs 15470121 # Number of memory refs (Count)
board.processor.cores.core.executeStats0.numMiscRegReads 17580039 # Number of times the Misc registers were read (Count)
board.processor.cores.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores.core.fetch.predictedBranches 1063071 # Number of branches that fetch has predicted taken (Count)
board.processor.cores.core.fetch.cycles 30606294 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.cores.core.fetch.squashCycles 22550 # Number of cycles fetch has spent squashing (Cycle)
board.processor.cores.core.fetch.miscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs (Cycle)
board.processor.cores.core.fetch.pendingTrapStallCycles 201 # Number of stall cycles due to pending traps (Cycle)
board.processor.cores.core.fetch.cacheLines 3156055 # Number of cache lines fetched (Count)
board.processor.cores.core.fetch.icacheSquashes 232 # Number of outstanding Icache misses that were squashed (Count)
board.processor.cores.core.fetch.nisnDist::samples 30645887 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::mean 1.361480 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::stdev 0.931412 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::0 9756349 31.84% 31.84% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::1 55300 0.18% 32.02% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::2 20834238 67.98% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::max_value 2 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::total 30645887 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetchStats0.numInsts 27184487 # Number of instructions fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.fetchRate 0.885113 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores.core.fetchStats0.numBranches 1066210 # Number of branches fetched (Count)
board.processor.cores.core.fetchStats0.branchRate 0.034715 # Number of branch fetches per cycle (Ratio)
board.processor.cores.core.fetchStats0.icacheStallCycles 28079 # ICache total stall cycles (Cycle)
board.processor.cores.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.cores.core.iew.squashCycles 10993 # Number of cycles IEW is squashing (Cycle)
board.processor.cores.core.iew.blockCycles 20764 # Number of cycles IEW is blocking (Cycle)
board.processor.cores.core.iew.unblockCycles 0 # Number of cycles IEW is unblocking (Cycle)
board.processor.cores.core.iew.dispatchedInsts 41327387 # Number of instructions dispatched to IQ (Count)
board.processor.cores.core.iew.dispSquashedInsts 622 # Number of squashed instructions skipped by dispatch (Count)
board.processor.cores.core.iew.dispLoadInsts 13397269 # Number of dispatched load instructions (Count)
board.processor.cores.core.iew.dispStoreInsts 2093821 # Number of dispatched store instructions (Count)
board.processor.cores.core.iew.dispNonSpecInsts 0 # Number of dispatched non-speculative instructions (Count)
board.processor.cores.core.iew.iqFullEvents 0 # Number of times the IQ has become full, causing a stall (Count)
board.processor.cores.core.iew.lsqFullEvents 0 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.cores.core.iew.memOrderViolationEvents 18 # Number of memory order violations (Count)
board.processor.cores.core.iew.predictedTakenIncorrect 10350 # Number of branches that were predicted taken incorrectly (Count)
board.processor.cores.core.iew.predictedNotTakenIncorrect 606 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.cores.core.iew.branchMispredicts 10956 # Number of branch mispredicts detected at execute (Count)
board.processor.cores.core.iew.instsToCommit 41193787 # Cumulative count of insts sent to commit (Count)
board.processor.cores.core.iew.writebackCount 41193158 # Cumulative count of insts written-back (Count)
board.processor.cores.core.iew.producerInst 31855203 # Number of instructions producing a value (Count)
board.processor.cores.core.iew.consumerInst 46150820 # Number of instructions consuming a value (Count)
board.processor.cores.core.iew.wbRate 1.341228 # Insts written-back per cycle ((Count/Cycle))
board.processor.cores.core.iew.wbFanout 0.690241 # Average fanout of values written-back ((Count/Count))
board.processor.cores.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.cores.core.lsq0.forwLoads 2099287 # Number of loads that had data forwarded from stores (Count)
board.processor.cores.core.lsq0.squashedLoads 82575 # Number of loads squashed (Count)
board.processor.cores.core.lsq0.ignoredResponses 46 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.cores.core.lsq0.memOrderViolation 18 # Number of memory ordering violations (Count)
board.processor.cores.core.lsq0.squashedStores 706 # Number of stores squashed (Count)
board.processor.cores.core.lsq0.rescheduledLoads 0 # Number of loads that were rescheduled (Count)
board.processor.cores.core.lsq0.blockedByCache 0 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.cores.core.lsq0.loadToUse::samples 13314694 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::mean 2.285531 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::stdev 1.317087 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::0-9 13251659 99.53% 99.53% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::10-19 62829 0.47% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::20-29 24 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::40-49 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::90-99 2 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::100-109 2 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::120-129 3 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::130-139 59 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::140-149 15 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::150-159 9 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::160-169 2 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::170-179 1 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::180-189 38 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::190-199 7 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::200-209 3 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::210-219 3 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::220-229 20 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::230-239 8 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::240-249 6 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::overflows 3 0.00% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::max_value 1332 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::total 13314694 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.addedLoadsAndStores 15491090 # Number of loads and stores written to the Load Store Queue (Count)
board.processor.cores.core.mmu.dtb.rdAccesses 13376616 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrAccesses 2093513 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.dtb.rdMisses 171 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrMisses 27 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.itb.wrAccesses 3156094 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.itb.wrMisses 91 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON 10227433662 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.rename.squashCycles 10993 # Number of cycles rename is squashing (Cycle)
board.processor.cores.core.rename.idleCycles 6068768 # Number of cycles rename is idle (Cycle)
board.processor.cores.core.rename.blockCycles 1744097 # Number of cycles rename is blocking (Cycle)
board.processor.cores.core.rename.serializeStallCycles 488 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.cores.core.rename.runCycles 16615804 # Number of cycles rename is running (Cycle)
board.processor.cores.core.rename.unblockCycles 6205737 # Number of cycles rename is unblocking (Cycle)
board.processor.cores.core.rename.renamedInsts 41350124 # Number of instructions processed by rename (Count)
board.processor.cores.core.rename.ROBFullEvents 2204883 # Number of times rename has blocked due to ROB full (Count)
board.processor.cores.core.rename.SQFullEvents 3966 # Number of times rename has blocked due to SQ full (Count)
board.processor.cores.core.rename.renamedOperands 83571352 # Number of destination operands rename has renamed (Count)
board.processor.cores.core.rename.lookups 142599417 # Number of register rename lookups that rename has made (Count)
board.processor.cores.core.rename.intLookups 61894926 # Number of integer rename lookups (Count)
board.processor.cores.core.rename.fpLookups 1852 # Number of floating rename lookups (Count)
board.processor.cores.core.rename.committedMaps 83048018 # Number of HB maps that are committed (Count)
board.processor.cores.core.rename.undoneMaps 523319 # Number of HB maps that are undone due to squashing (Count)
board.processor.cores.core.rename.serializing 22 # count of serializing insts renamed (Count)
board.processor.cores.core.rename.tempSerializing 21 # count of temporary serializing insts renamed (Count)
board.processor.cores.core.rename.skidInsts 10156336 # count of insts added to the skid buffer (Count)
board.processor.cores.core.rename.intReturned 36904843 # count of registers freed and written back to integer free list (Count)
board.processor.cores.core.rename.fpReturned 817 # count of registers freed and written back to floating point free list (Count)
board.processor.cores.core.rob.reads 56398435 # The number of ROB reads (Count)
board.processor.cores.core.rob.writes 82684949 # The number of ROB writes (Count)
board.processor.cores.core.thread_0.numInsts 26728147 # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps 41096287 # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.cores.core.workload.numSyscalls 18 # Number of system calls (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------