---------- Begin Simulation Statistics ----------
simSeconds 0.139576 # Number of seconds simulated (Second)
simTicks 139576403500 # Number of ticks simulated (Tick)
finalTick 140053531500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 1859.57 # Real time elapsed on the host (Second)
hostTickRate 75058271 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 5464260 # Number of bytes of host memory used (Byte)
simInsts 869647571 # Number of instructions simulated (Count)
simOps 1672005370 # Number of ops (including micro ops) simulated (Count)
hostInstRate 467660 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 899134 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches0.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches0.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches1.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches1.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches1.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches1.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches1.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches1.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches1.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches1.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches1.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches1.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches1.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches1.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches1.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches1.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches1.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches1.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches2.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches2.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches2.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches2.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches2.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches2.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches2.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches2.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches2.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches2.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches2.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches2.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches2.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches2.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches2.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches3.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches3.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches3.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches3.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches3.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches3.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches3.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches3.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches3.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches3.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches3.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches3.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches3.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches3.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches3.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches3.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches4.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches4.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches4.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches4.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches4.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches4.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches4.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches4.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches4.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches4.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches4.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches4.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches4.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches4.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches4.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches4.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches5.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches5.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches5.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches5.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches5.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches5.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches5.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches5.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches5.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches5.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches5.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches5.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches5.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches5.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches5.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches5.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches6.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches6.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches6.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches6.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches6.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches6.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches6.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches6.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches6.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches6.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches6.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches6.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches6.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches6.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches6.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches6.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches7.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches7.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches7.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches7.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches7.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches7.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches7.replacements 0 # number of replacements (Count)
board.cache_hierarchy.dptw_caches7.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches7.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches7.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches7.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches7.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches7.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches7.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches7.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches7.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches0.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches0.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches0.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches0.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches0.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches0.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches0.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches0.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches1.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches1.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches1.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches1.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches1.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches1.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches1.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches1.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches1.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches1.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches1.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches1.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches1.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches1.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches1.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches1.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches2.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches2.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches2.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches2.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches2.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches2.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches2.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches2.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches2.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches2.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches2.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches2.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches2.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches2.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches2.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches3.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches3.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches3.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches3.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches3.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches3.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches3.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches3.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches3.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches3.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches3.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches3.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches3.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches3.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches3.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches3.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches4.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches4.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches4.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches4.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches4.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches4.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches4.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches4.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches4.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches4.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches4.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches4.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches4.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches4.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches4.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches4.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches5.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches5.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches5.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches5.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches5.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches5.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches5.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches5.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches5.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches5.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches5.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches5.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches5.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches5.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches5.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches5.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches6.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches6.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches6.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches6.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches6.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches6.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches6.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches6.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches6.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches6.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches6.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches6.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches6.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches6.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches6.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches6.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches7.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches7.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches7.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches7.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches7.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches7.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches7.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iptw_caches7.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches7.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches7.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches7.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches7.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches7.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches7.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches7.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches7.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches0.demandHits::processor.cores0.core.data 57629223 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches0.demandHits::total 57629223 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches0.overallHits::processor.cores0.core.data 57629223 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches0.overallHits::total 57629223 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches0.demandMisses::processor.cores0.core.data 713096 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches0.demandMisses::total 713096 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches0.overallMisses::processor.cores0.core.data 713096 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches0.overallMisses::total 713096 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches0.demandMissLatency::processor.cores0.core.data 30849740985 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.demandMissLatency::total 30849740985 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.overallMissLatency::processor.cores0.core.data 30849740985 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.overallMissLatency::total 30849740985 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.demandAccesses::processor.cores0.core.data 58342319 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches0.demandAccesses::total 58342319 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches0.overallAccesses::processor.cores0.core.data 58342319 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches0.overallAccesses::total 58342319 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches0.demandMissRate::processor.cores0.core.data 0.012223 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches0.demandMissRate::total 0.012223 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches0.overallMissRate::processor.cores0.core.data 0.012223 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches0.overallMissRate::total 0.012223 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches0.demandAvgMissLatency::processor.cores0.core.data 43261.694057 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches0.demandAvgMissLatency::total 43261.694057 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches0.overallAvgMissLatency::processor.cores0.core.data 43261.694057 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.overallAvgMissLatency::total 43261.694057 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches0.writebacks::writebacks 964886 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches0.writebacks::total 964886 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches0.demandMshrHits::processor.cores0.core.data 23225 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches0.demandMshrHits::total 23225 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches0.overallMshrHits::processor.cores0.core.data 23225 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches0.overallMshrHits::total 23225 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches0.demandMshrMisses::processor.cores0.core.data 689871 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.demandMshrMisses::total 689871 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.overallMshrMisses::cache_hierarchy.l1dcaches0.prefetcher 1580995 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.overallMshrMisses::processor.cores0.core.data 689871 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.overallMshrMisses::total 2270866 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.demandMshrMissLatency::processor.cores0.core.data 29440926485 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.demandMshrMissLatency::total 29440926485 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.overallMshrMissLatency::cache_hierarchy.l1dcaches0.prefetcher 81179578080 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.overallMshrMissLatency::processor.cores0.core.data 29440926485 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.overallMshrMissLatency::total 110620504565 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.demandMshrMissRate::processor.cores0.core.data 0.011825 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches0.demandMshrMissRate::total 0.011825 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches0.overallMshrMissRate::cache_hierarchy.l1dcaches0.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches0.overallMshrMissRate::processor.cores0.core.data 0.011825 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches0.overallMshrMissRate::total 0.038923 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches0.demandAvgMshrMissLatency::processor.cores0.core.data 42675.987953 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.demandAvgMshrMissLatency::total 42675.987953 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches0.prefetcher 51347.144096 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.overallAvgMshrMissLatency::processor.cores0.core.data 42675.987953 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.overallAvgMshrMissLatency::total 48712.915938 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.replacements 2192313 # number of replacements (Count)
board.cache_hierarchy.l1dcaches0.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches0.prefetcher 1580995 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.HardPFReq.mshrMisses::total 1580995 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches0.prefetcher 81179578080 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.HardPFReq.mshrMissLatency::total 81179578080 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches0.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches0.prefetcher 51347.144096 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.HardPFReq.avgMshrMissLatency::total 51347.144096 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.misses::processor.cores0.core.data 95 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.misses::total 95 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.missLatency::processor.cores0.core.data 4640000 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.missLatency::total 4640000 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.accesses::processor.cores0.core.data 95 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.accesses::total 95 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.missRate::processor.cores0.core.data 1 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.missRate::total 1 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.avgMissLatency::processor.cores0.core.data 48842.105263 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.avgMissLatency::total 48842.105263 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.mshrMisses::processor.cores0.core.data 95 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.mshrMisses::total 95 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.mshrMissLatency::processor.cores0.core.data 9232500 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.mshrMissLatency::total 9232500 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.mshrMissRate::processor.cores0.core.data 1 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.mshrMissRate::total 1 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.avgMshrMissLatency::processor.cores0.core.data 97184.210526 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.LockedRMWReadReq.avgMshrMissLatency::total 97184.210526 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.LockedRMWWriteReq.hits::processor.cores0.core.data 95 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1dcaches0.LockedRMWWriteReq.hits::total 95 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1dcaches0.LockedRMWWriteReq.accesses::processor.cores0.core.data 95 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches0.LockedRMWWriteReq.accesses::total 95 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.hits::processor.cores0.core.data 47874816 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.hits::total 47874816 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.misses::processor.cores0.core.data 484195 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.misses::total 484195 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.missLatency::processor.cores0.core.data 19620207985 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.ReadReq.missLatency::total 19620207985 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.ReadReq.accesses::processor.cores0.core.data 48359011 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.accesses::total 48359011 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.missRate::processor.cores0.core.data 0.010013 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.ReadReq.missRate::total 0.010013 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.ReadReq.avgMissLatency::processor.cores0.core.data 40521.294076 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.ReadReq.avgMissLatency::total 40521.294076 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.ReadReq.mshrHits::processor.cores0.core.data 19409 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrHits::total 19409 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrMisses::processor.cores0.core.data 464786 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrMisses::total 464786 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrMissLatency::processor.cores0.core.data 18509548485 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrMissLatency::total 18509548485 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrMissRate::processor.cores0.core.data 0.009611 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.ReadReq.mshrMissRate::total 0.009611 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.ReadReq.avgMshrMissLatency::processor.cores0.core.data 39823.808129 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.ReadReq.avgMshrMissLatency::total 39823.808129 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.WriteReq.hits::processor.cores0.core.data 9754407 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches0.WriteReq.hits::total 9754407 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches0.WriteReq.misses::processor.cores0.core.data 228901 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches0.WriteReq.misses::total 228901 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches0.WriteReq.missLatency::processor.cores0.core.data 11229533000 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.WriteReq.missLatency::total 11229533000 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.WriteReq.accesses::processor.cores0.core.data 9983308 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches0.WriteReq.accesses::total 9983308 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches0.WriteReq.missRate::processor.cores0.core.data 0.022928 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.WriteReq.missRate::total 0.022928 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.WriteReq.avgMissLatency::processor.cores0.core.data 49058.470693 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.WriteReq.avgMissLatency::total 49058.470693 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.WriteReq.mshrHits::processor.cores0.core.data 3816 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches0.WriteReq.mshrHits::total 3816 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches0.WriteReq.mshrMisses::processor.cores0.core.data 225085 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.WriteReq.mshrMisses::total 225085 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches0.WriteReq.mshrMissLatency::processor.cores0.core.data 10931378000 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.WriteReq.mshrMissLatency::total 10931378000 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches0.WriteReq.mshrMissRate::processor.cores0.core.data 0.022546 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.WriteReq.mshrMissRate::total 0.022546 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches0.WriteReq.avgMshrMissLatency::processor.cores0.core.data 48565.555235 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.WriteReq.avgMshrMissLatency::total 48565.555235 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches0.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches0.prefetcher.demandMshrMisses 689871 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfIssued 4495416 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfUnused 69326 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfUseful 1488684 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfUsefulButMiss 280 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.accuracy 0.331156 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.coverage 0.683336 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfHitInCache 2811792 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfHitInMSHR 102628 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfHitInWB 1 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfLate 2914421 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfIdentified 4651657 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfBufferHit 110254 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfRemovedDemand 32430 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfRemovedFull 12684 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfSpanPage 724627 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.pfUsefulSpanPage 494333 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches0.tags.tagsInUse 511.820728 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches0.tags.totalRefs 58148312 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches0.tags.sampledRefs 2246397 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches0.tags.avgRefs 25.885145 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches0.tags.occupancies::cache_hierarchy.l1dcaches0.prefetcher 310.861519 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches0.tags.occupancies::processor.cores0.core.data 200.959209 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches0.tags.avgOccs::cache_hierarchy.l1dcaches0.prefetcher 0.607151 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches0.tags.avgOccs::processor.cores0.core.data 0.392498 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches0.tags.avgOccs::total 0.999650 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches0.tags.occupanciesTaskId::1022 425 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches0.tags.occupanciesTaskId::1024 87 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches0.tags.ageTaskId_1022::3 425 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches0.tags.ageTaskId_1024::3 87 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches0.tags.ratioOccsTaskId::1022 0.830078 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches0.tags.ratioOccsTaskId::1024 0.169922 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches0.tags.tagAccesses 468986470 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches0.tags.dataAccesses 468986470 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches1.demandHits::processor.cores1.core.data 58227020 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches1.demandHits::total 58227020 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches1.overallHits::processor.cores1.core.data 58227020 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches1.overallHits::total 58227020 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches1.demandMisses::processor.cores1.core.data 703158 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches1.demandMisses::total 703158 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches1.overallMisses::processor.cores1.core.data 703158 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches1.overallMisses::total 703158 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches1.demandMissLatency::processor.cores1.core.data 30830909495 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.demandMissLatency::total 30830909495 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.overallMissLatency::processor.cores1.core.data 30830909495 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.overallMissLatency::total 30830909495 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.demandAccesses::processor.cores1.core.data 58930178 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches1.demandAccesses::total 58930178 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches1.overallAccesses::processor.cores1.core.data 58930178 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches1.overallAccesses::total 58930178 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches1.demandMissRate::processor.cores1.core.data 0.011932 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches1.demandMissRate::total 0.011932 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches1.overallMissRate::processor.cores1.core.data 0.011932 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches1.overallMissRate::total 0.011932 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches1.demandAvgMissLatency::processor.cores1.core.data 43846.346760 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches1.demandAvgMissLatency::total 43846.346760 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches1.overallAvgMissLatency::processor.cores1.core.data 43846.346760 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.overallAvgMissLatency::total 43846.346760 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches1.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches1.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches1.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches1.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches1.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches1.writebacks::writebacks 1094603 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches1.writebacks::total 1094603 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches1.demandMshrHits::processor.cores1.core.data 27212 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches1.demandMshrHits::total 27212 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches1.overallMshrHits::processor.cores1.core.data 27212 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches1.overallMshrHits::total 27212 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches1.demandMshrMisses::processor.cores1.core.data 675946 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.demandMshrMisses::total 675946 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.overallMshrMisses::cache_hierarchy.l1dcaches1.prefetcher 1850042 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.overallMshrMisses::processor.cores1.core.data 675946 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.overallMshrMisses::total 2525988 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.demandMshrMissLatency::processor.cores1.core.data 29282332995 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.demandMshrMissLatency::total 29282332995 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.overallMshrMissLatency::cache_hierarchy.l1dcaches1.prefetcher 93227772817 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.overallMshrMissLatency::processor.cores1.core.data 29282332995 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.overallMshrMissLatency::total 122510105812 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.demandMshrMissRate::processor.cores1.core.data 0.011470 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches1.demandMshrMissRate::total 0.011470 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches1.overallMshrMissRate::cache_hierarchy.l1dcaches1.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches1.overallMshrMissRate::processor.cores1.core.data 0.011470 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches1.overallMshrMissRate::total 0.042864 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches1.demandAvgMshrMissLatency::processor.cores1.core.data 43320.521158 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.demandAvgMshrMissLatency::total 43320.521158 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches1.prefetcher 50392.246672 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.overallAvgMshrMissLatency::processor.cores1.core.data 43320.521158 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.overallAvgMshrMissLatency::total 48499.876410 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.replacements 2478053 # number of replacements (Count)
board.cache_hierarchy.l1dcaches1.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches1.prefetcher 1850042 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.HardPFReq.mshrMisses::total 1850042 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches1.prefetcher 93227772817 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.HardPFReq.mshrMissLatency::total 93227772817 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches1.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches1.prefetcher 50392.246672 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.HardPFReq.avgMshrMissLatency::total 50392.246672 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.hits::processor.cores1.core.data 436 # number of LockedRMWReadReq hits (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.hits::total 436 # number of LockedRMWReadReq hits (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.misses::processor.cores1.core.data 419 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.misses::total 419 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.missLatency::processor.cores1.core.data 15839000 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.missLatency::total 15839000 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.accesses::processor.cores1.core.data 855 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.accesses::total 855 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.missRate::processor.cores1.core.data 0.490058 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.missRate::total 0.490058 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.avgMissLatency::processor.cores1.core.data 37801.909308 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.avgMissLatency::total 37801.909308 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.mshrMisses::processor.cores1.core.data 419 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.mshrMisses::total 419 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.mshrMissLatency::processor.cores1.core.data 31686500 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.mshrMissLatency::total 31686500 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.mshrMissRate::processor.cores1.core.data 0.490058 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.mshrMissRate::total 0.490058 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.avgMshrMissLatency::processor.cores1.core.data 75624.105012 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.LockedRMWReadReq.avgMshrMissLatency::total 75624.105012 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.LockedRMWWriteReq.hits::processor.cores1.core.data 855 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWWriteReq.hits::total 855 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWWriteReq.accesses::processor.cores1.core.data 855 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches1.LockedRMWWriteReq.accesses::total 855 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.hits::processor.cores1.core.data 48020630 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.hits::total 48020630 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.misses::processor.cores1.core.data 494729 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.misses::total 494729 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.missLatency::processor.cores1.core.data 20341380995 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.ReadReq.missLatency::total 20341380995 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.ReadReq.accesses::processor.cores1.core.data 48515359 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.accesses::total 48515359 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.missRate::processor.cores1.core.data 0.010197 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.ReadReq.missRate::total 0.010197 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.ReadReq.avgMissLatency::processor.cores1.core.data 41116.209066 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.ReadReq.avgMissLatency::total 41116.209066 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.ReadReq.mshrHits::processor.cores1.core.data 22281 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.mshrHits::total 22281 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.mshrMisses::processor.cores1.core.data 472448 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.mshrMisses::total 472448 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.ReadReq.mshrMissLatency::processor.cores1.core.data 19117266495 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.ReadReq.mshrMissLatency::total 19117266495 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.ReadReq.mshrMissRate::processor.cores1.core.data 0.009738 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.ReadReq.mshrMissRate::total 0.009738 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.ReadReq.avgMshrMissLatency::processor.cores1.core.data 40464.276481 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.ReadReq.avgMshrMissLatency::total 40464.276481 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.WriteReq.hits::processor.cores1.core.data 10206390 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches1.WriteReq.hits::total 10206390 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches1.WriteReq.misses::processor.cores1.core.data 208429 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches1.WriteReq.misses::total 208429 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches1.WriteReq.missLatency::processor.cores1.core.data 10489528500 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.WriteReq.missLatency::total 10489528500 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.WriteReq.accesses::processor.cores1.core.data 10414819 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches1.WriteReq.accesses::total 10414819 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches1.WriteReq.missRate::processor.cores1.core.data 0.020013 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.WriteReq.missRate::total 0.020013 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.WriteReq.avgMissLatency::processor.cores1.core.data 50326.626813 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.WriteReq.avgMissLatency::total 50326.626813 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.WriteReq.mshrHits::processor.cores1.core.data 4931 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches1.WriteReq.mshrHits::total 4931 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches1.WriteReq.mshrMisses::processor.cores1.core.data 203498 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.WriteReq.mshrMisses::total 203498 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches1.WriteReq.mshrMissLatency::processor.cores1.core.data 10165066500 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.WriteReq.mshrMissLatency::total 10165066500 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches1.WriteReq.mshrMissRate::processor.cores1.core.data 0.019539 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.WriteReq.mshrMissRate::total 0.019539 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches1.WriteReq.avgMshrMissLatency::processor.cores1.core.data 49951.677658 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.WriteReq.avgMshrMissLatency::total 49951.677658 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches1.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches1.prefetcher.demandMshrMisses 675946 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfIssued 5300022 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfUnused 80318 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfUseful 1743090 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfUsefulButMiss 612 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.accuracy 0.328884 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.coverage 0.720572 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfHitInCache 3319798 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfHitInMSHR 130170 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfHitInWB 12 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfLate 3449980 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfIdentified 5471412 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfBufferHit 118111 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfRemovedDemand 34431 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfRemovedFull 17584 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfSpanPage 901512 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.pfUsefulSpanPage 598194 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches1.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches1.tags.tagsInUse 511.822710 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches1.tags.totalRefs 59780600 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches1.tags.sampledRefs 2503982 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches1.tags.avgRefs 23.874213 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches1.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches1.tags.occupancies::cache_hierarchy.l1dcaches1.prefetcher 323.551982 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches1.tags.occupancies::processor.cores1.core.data 188.270728 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches1.tags.avgOccs::cache_hierarchy.l1dcaches1.prefetcher 0.631937 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches1.tags.avgOccs::processor.cores1.core.data 0.367716 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches1.tags.avgOccs::total 0.999654 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches1.tags.occupanciesTaskId::1022 405 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches1.tags.occupanciesTaskId::1024 107 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches1.tags.ageTaskId_1022::3 405 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches1.tags.ageTaskId_1024::3 107 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches1.tags.ratioOccsTaskId::1022 0.791016 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches1.tags.ratioOccsTaskId::1024 0.208984 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches1.tags.tagAccesses 473959573 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches1.tags.dataAccesses 473959573 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches1.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches2.demandHits::processor.cores2.core.data 58124607 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches2.demandHits::total 58124607 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches2.overallHits::processor.cores2.core.data 58124607 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches2.overallHits::total 58124607 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches2.demandMisses::processor.cores2.core.data 800035 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches2.demandMisses::total 800035 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches2.overallMisses::processor.cores2.core.data 800035 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches2.overallMisses::total 800035 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches2.demandMissLatency::processor.cores2.core.data 32548412986 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.demandMissLatency::total 32548412986 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.overallMissLatency::processor.cores2.core.data 32548412986 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.overallMissLatency::total 32548412986 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.demandAccesses::processor.cores2.core.data 58924642 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches2.demandAccesses::total 58924642 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches2.overallAccesses::processor.cores2.core.data 58924642 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches2.overallAccesses::total 58924642 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches2.demandMissRate::processor.cores2.core.data 0.013577 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches2.demandMissRate::total 0.013577 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches2.overallMissRate::processor.cores2.core.data 0.013577 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches2.overallMissRate::total 0.013577 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches2.demandAvgMissLatency::processor.cores2.core.data 40683.736319 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches2.demandAvgMissLatency::total 40683.736319 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches2.overallAvgMissLatency::processor.cores2.core.data 40683.736319 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.overallAvgMissLatency::total 40683.736319 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches2.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches2.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches2.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches2.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches2.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches2.writebacks::writebacks 1087522 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches2.writebacks::total 1087522 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches2.demandMshrHits::processor.cores2.core.data 24772 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches2.demandMshrHits::total 24772 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches2.overallMshrHits::processor.cores2.core.data 24772 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches2.overallMshrHits::total 24772 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches2.demandMshrMisses::processor.cores2.core.data 775263 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.demandMshrMisses::total 775263 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.overallMshrMisses::cache_hierarchy.l1dcaches2.prefetcher 1950828 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.overallMshrMisses::processor.cores2.core.data 775263 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.overallMshrMisses::total 2726091 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.demandMshrMissLatency::processor.cores2.core.data 31040602986 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.demandMshrMissLatency::total 31040602986 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.overallMshrMissLatency::cache_hierarchy.l1dcaches2.prefetcher 94762508220 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.overallMshrMissLatency::processor.cores2.core.data 31040602986 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.overallMshrMissLatency::total 125803111206 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.demandMshrMissRate::processor.cores2.core.data 0.013157 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches2.demandMshrMissRate::total 0.013157 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches2.overallMshrMissRate::cache_hierarchy.l1dcaches2.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches2.overallMshrMissRate::processor.cores2.core.data 0.013157 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches2.overallMshrMissRate::total 0.046264 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches2.demandAvgMshrMissLatency::processor.cores2.core.data 40038.803588 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.demandAvgMshrMissLatency::total 40038.803588 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches2.prefetcher 48575.532143 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.overallAvgMshrMissLatency::processor.cores2.core.data 40038.803588 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.overallAvgMshrMissLatency::total 46147.803285 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.replacements 2596040 # number of replacements (Count)
board.cache_hierarchy.l1dcaches2.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches2.prefetcher 1950828 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.HardPFReq.mshrMisses::total 1950828 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches2.prefetcher 94762508220 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.HardPFReq.mshrMissLatency::total 94762508220 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches2.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches2.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches2.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches2.prefetcher 48575.532143 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.HardPFReq.avgMshrMissLatency::total 48575.532143 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.LockedRMWReadReq.misses::processor.cores2.core.data 95 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1dcaches2.LockedRMWReadReq.misses::total 95 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1dcaches2.LockedRMWReadReq.missLatency::processor.cores2.core.data 2956500 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.LockedRMWReadReq.missLatency::total 2956500 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.LockedRMWReadReq.accesses::processor.cores2.core.data 95 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches2.LockedRMWReadReq.accesses::total 95 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches2.LockedRMWReadReq.missRate::processor.cores2.core.data 1 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches2.LockedRMWReadReq.missRate::total 1 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches2.LockedRMWReadReq.avgMissLatency::processor.cores2.core.data 31121.052632 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.LockedRMWReadReq.avgMissLatency::total 31121.052632 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.LockedRMWReadReq.mshrMisses::processor.cores2.core.data 95 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.LockedRMWReadReq.mshrMisses::total 95 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.LockedRMWReadReq.mshrMissLatency::processor.cores2.core.data 5865500 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.LockedRMWReadReq.mshrMissLatency::total 5865500 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.LockedRMWReadReq.mshrMissRate::processor.cores2.core.data 1 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches2.LockedRMWReadReq.mshrMissRate::total 1 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches2.LockedRMWReadReq.avgMshrMissLatency::processor.cores2.core.data 61742.105263 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.LockedRMWReadReq.avgMshrMissLatency::total 61742.105263 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.LockedRMWWriteReq.hits::processor.cores2.core.data 95 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1dcaches2.LockedRMWWriteReq.hits::total 95 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1dcaches2.LockedRMWWriteReq.accesses::processor.cores2.core.data 95 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches2.LockedRMWWriteReq.accesses::total 95 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.hits::processor.cores2.core.data 48119225 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.hits::total 48119225 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.misses::processor.cores2.core.data 551674 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.misses::total 551674 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.missLatency::processor.cores2.core.data 22181182986 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.ReadReq.missLatency::total 22181182986 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.ReadReq.accesses::processor.cores2.core.data 48670899 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.accesses::total 48670899 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.missRate::processor.cores2.core.data 0.011335 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches2.ReadReq.missRate::total 0.011335 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches2.ReadReq.avgMissLatency::processor.cores2.core.data 40207.047978 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.ReadReq.avgMissLatency::total 40207.047978 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.ReadReq.mshrHits::processor.cores2.core.data 20285 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.mshrHits::total 20285 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.mshrMisses::processor.cores2.core.data 531389 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.mshrMisses::total 531389 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.ReadReq.mshrMissLatency::processor.cores2.core.data 21004501486 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.ReadReq.mshrMissLatency::total 21004501486 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.ReadReq.mshrMissRate::processor.cores2.core.data 0.010918 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches2.ReadReq.mshrMissRate::total 0.010918 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches2.ReadReq.avgMshrMissLatency::processor.cores2.core.data 39527.542885 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.ReadReq.avgMshrMissLatency::total 39527.542885 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.WriteReq.hits::processor.cores2.core.data 10005382 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches2.WriteReq.hits::total 10005382 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches2.WriteReq.misses::processor.cores2.core.data 248361 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches2.WriteReq.misses::total 248361 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches2.WriteReq.missLatency::processor.cores2.core.data 10367230000 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.WriteReq.missLatency::total 10367230000 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.WriteReq.accesses::processor.cores2.core.data 10253743 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches2.WriteReq.accesses::total 10253743 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches2.WriteReq.missRate::processor.cores2.core.data 0.024221 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches2.WriteReq.missRate::total 0.024221 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches2.WriteReq.avgMissLatency::processor.cores2.core.data 41742.584383 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.WriteReq.avgMissLatency::total 41742.584383 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.WriteReq.mshrHits::processor.cores2.core.data 4487 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches2.WriteReq.mshrHits::total 4487 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches2.WriteReq.mshrMisses::processor.cores2.core.data 243874 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.WriteReq.mshrMisses::total 243874 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches2.WriteReq.mshrMissLatency::processor.cores2.core.data 10036101500 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.WriteReq.mshrMissLatency::total 10036101500 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches2.WriteReq.mshrMissRate::processor.cores2.core.data 0.023784 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches2.WriteReq.mshrMissRate::total 0.023784 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches2.WriteReq.avgMshrMissLatency::processor.cores2.core.data 41152.814568 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.WriteReq.avgMshrMissLatency::total 41152.814568 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches2.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches2.prefetcher.demandMshrMisses 775263 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfIssued 5684250 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfUnused 86090 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfUseful 1840151 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfUsefulButMiss 175 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.accuracy 0.323728 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.coverage 0.703579 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfHitInCache 3613325 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfHitInMSHR 120085 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfHitInWB 12 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfLate 3733422 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfIdentified 5833202 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfBufferHit 102499 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfRemovedDemand 30224 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfRemovedFull 14303 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfSpanPage 902878 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.pfUsefulSpanPage 575446 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches2.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches2.tags.tagsInUse 508.851297 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches2.tags.totalRefs 60758907 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches2.tags.sampledRefs 2671502 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches2.tags.avgRefs 22.743351 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches2.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches2.tags.occupancies::cache_hierarchy.l1dcaches2.prefetcher 316.301632 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches2.tags.occupancies::processor.cores2.core.data 192.549665 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches2.tags.avgOccs::cache_hierarchy.l1dcaches2.prefetcher 0.617777 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches2.tags.avgOccs::processor.cores2.core.data 0.376074 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches2.tags.avgOccs::total 0.993850 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches2.tags.occupanciesTaskId::1022 75 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches2.tags.occupanciesTaskId::1024 437 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches2.tags.ageTaskId_1022::0 8 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches2.tags.ageTaskId_1022::1 48 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches2.tags.ageTaskId_1022::2 19 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches2.tags.ageTaskId_1024::0 60 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches2.tags.ageTaskId_1024::1 279 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches2.tags.ageTaskId_1024::2 98 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches2.tags.ratioOccsTaskId::1022 0.146484 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches2.tags.ratioOccsTaskId::1024 0.853516 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches2.tags.tagAccesses 474070644 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches2.tags.dataAccesses 474070644 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches3.demandHits::processor.cores3.core.data 58071059 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches3.demandHits::total 58071059 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches3.overallHits::processor.cores3.core.data 58071059 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches3.overallHits::total 58071059 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches3.demandMisses::processor.cores3.core.data 819538 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches3.demandMisses::total 819538 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches3.overallMisses::processor.cores3.core.data 819538 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches3.overallMisses::total 819538 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches3.demandMissLatency::processor.cores3.core.data 32830249492 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.demandMissLatency::total 32830249492 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.overallMissLatency::processor.cores3.core.data 32830249492 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.overallMissLatency::total 32830249492 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.demandAccesses::processor.cores3.core.data 58890597 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches3.demandAccesses::total 58890597 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches3.overallAccesses::processor.cores3.core.data 58890597 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches3.overallAccesses::total 58890597 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches3.demandMissRate::processor.cores3.core.data 0.013916 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches3.demandMissRate::total 0.013916 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches3.overallMissRate::processor.cores3.core.data 0.013916 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches3.overallMissRate::total 0.013916 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches3.demandAvgMissLatency::processor.cores3.core.data 40059.459710 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches3.demandAvgMissLatency::total 40059.459710 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches3.overallAvgMissLatency::processor.cores3.core.data 40059.459710 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.overallAvgMissLatency::total 40059.459710 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches3.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches3.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches3.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches3.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches3.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches3.writebacks::writebacks 1090318 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches3.writebacks::total 1090318 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches3.demandMshrHits::processor.cores3.core.data 26254 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches3.demandMshrHits::total 26254 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches3.overallMshrHits::processor.cores3.core.data 26254 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches3.overallMshrHits::total 26254 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches3.demandMshrMisses::processor.cores3.core.data 793284 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.demandMshrMisses::total 793284 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.overallMshrMisses::cache_hierarchy.l1dcaches3.prefetcher 1959617 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.overallMshrMisses::processor.cores3.core.data 793284 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.overallMshrMisses::total 2752901 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.demandMshrMissLatency::processor.cores3.core.data 31234897492 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.demandMshrMissLatency::total 31234897492 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.overallMshrMissLatency::cache_hierarchy.l1dcaches3.prefetcher 95565049424 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.overallMshrMissLatency::processor.cores3.core.data 31234897492 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.overallMshrMissLatency::total 126799946916 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.demandMshrMissRate::processor.cores3.core.data 0.013470 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches3.demandMshrMissRate::total 0.013470 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches3.overallMshrMissRate::cache_hierarchy.l1dcaches3.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches3.overallMshrMissRate::processor.cores3.core.data 0.013470 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches3.overallMshrMissRate::total 0.046746 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches3.demandAvgMshrMissLatency::processor.cores3.core.data 39374.168005 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.demandAvgMshrMissLatency::total 39374.168005 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches3.prefetcher 48767.207788 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.overallAvgMshrMissLatency::processor.cores3.core.data 39374.168005 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.overallAvgMshrMissLatency::total 46060.481985 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.replacements 2601242 # number of replacements (Count)
board.cache_hierarchy.l1dcaches3.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches3.prefetcher 1959617 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.HardPFReq.mshrMisses::total 1959617 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches3.prefetcher 95565049424 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.HardPFReq.mshrMissLatency::total 95565049424 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches3.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches3.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches3.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches3.prefetcher 48767.207788 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.HardPFReq.avgMshrMissLatency::total 48767.207788 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.LockedRMWReadReq.misses::processor.cores3.core.data 95 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1dcaches3.LockedRMWReadReq.misses::total 95 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1dcaches3.LockedRMWReadReq.missLatency::processor.cores3.core.data 1053500 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.LockedRMWReadReq.missLatency::total 1053500 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.LockedRMWReadReq.accesses::processor.cores3.core.data 95 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches3.LockedRMWReadReq.accesses::total 95 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches3.LockedRMWReadReq.missRate::processor.cores3.core.data 1 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches3.LockedRMWReadReq.missRate::total 1 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches3.LockedRMWReadReq.avgMissLatency::processor.cores3.core.data 11089.473684 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.LockedRMWReadReq.avgMissLatency::total 11089.473684 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.LockedRMWReadReq.mshrMisses::processor.cores3.core.data 95 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.LockedRMWReadReq.mshrMisses::total 95 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.LockedRMWReadReq.mshrMissLatency::processor.cores3.core.data 2059500 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.LockedRMWReadReq.mshrMissLatency::total 2059500 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.LockedRMWReadReq.mshrMissRate::processor.cores3.core.data 1 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches3.LockedRMWReadReq.mshrMissRate::total 1 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches3.LockedRMWReadReq.avgMshrMissLatency::processor.cores3.core.data 21678.947368 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.LockedRMWReadReq.avgMshrMissLatency::total 21678.947368 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.LockedRMWWriteReq.hits::processor.cores3.core.data 95 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1dcaches3.LockedRMWWriteReq.hits::total 95 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1dcaches3.LockedRMWWriteReq.accesses::processor.cores3.core.data 95 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches3.LockedRMWWriteReq.accesses::total 95 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.hits::processor.cores3.core.data 48038542 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.hits::total 48038542 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.misses::processor.cores3.core.data 554164 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.misses::total 554164 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.missLatency::processor.cores3.core.data 22233987492 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.ReadReq.missLatency::total 22233987492 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.ReadReq.accesses::processor.cores3.core.data 48592706 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.accesses::total 48592706 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.missRate::processor.cores3.core.data 0.011404 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches3.ReadReq.missRate::total 0.011404 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches3.ReadReq.avgMissLatency::processor.cores3.core.data 40121.674255 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.ReadReq.avgMissLatency::total 40121.674255 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.ReadReq.mshrHits::processor.cores3.core.data 21470 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.mshrHits::total 21470 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.mshrMisses::processor.cores3.core.data 532694 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.mshrMisses::total 532694 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.ReadReq.mshrMissLatency::processor.cores3.core.data 20982877992 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.ReadReq.mshrMissLatency::total 20982877992 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.ReadReq.mshrMissRate::processor.cores3.core.data 0.010962 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches3.ReadReq.mshrMissRate::total 0.010962 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches3.ReadReq.avgMshrMissLatency::processor.cores3.core.data 39390.115136 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.ReadReq.avgMshrMissLatency::total 39390.115136 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.WriteReq.hits::processor.cores3.core.data 10032517 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches3.WriteReq.hits::total 10032517 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches3.WriteReq.misses::processor.cores3.core.data 265374 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches3.WriteReq.misses::total 265374 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches3.WriteReq.missLatency::processor.cores3.core.data 10596262000 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.WriteReq.missLatency::total 10596262000 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.WriteReq.accesses::processor.cores3.core.data 10297891 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches3.WriteReq.accesses::total 10297891 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches3.WriteReq.missRate::processor.cores3.core.data 0.025770 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches3.WriteReq.missRate::total 0.025770 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches3.WriteReq.avgMissLatency::processor.cores3.core.data 39929.540950 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.WriteReq.avgMissLatency::total 39929.540950 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.WriteReq.mshrHits::processor.cores3.core.data 4784 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches3.WriteReq.mshrHits::total 4784 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches3.WriteReq.mshrMisses::processor.cores3.core.data 260590 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.WriteReq.mshrMisses::total 260590 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches3.WriteReq.mshrMissLatency::processor.cores3.core.data 10252019500 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.WriteReq.mshrMissLatency::total 10252019500 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches3.WriteReq.mshrMissRate::processor.cores3.core.data 0.025305 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches3.WriteReq.mshrMissRate::total 0.025305 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches3.WriteReq.avgMshrMissLatency::processor.cores3.core.data 39341.569132 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.WriteReq.avgMshrMissLatency::total 39341.569132 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches3.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches3.prefetcher.demandMshrMisses 793284 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfIssued 5728559 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfUnused 89133 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfUseful 1845048 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfUsefulButMiss 711 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.accuracy 0.322079 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.coverage 0.699324 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfHitInCache 3642950 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfHitInMSHR 125986 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfHitInWB 6 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfLate 3768942 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfIdentified 5886678 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfBufferHit 109649 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfRemovedDemand 33319 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfRemovedFull 13653 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfSpanPage 933438 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.pfUsefulSpanPage 592004 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches3.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches3.tags.tagsInUse 509.635498 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches3.tags.totalRefs 60692131 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches3.tags.sampledRefs 2698136 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches3.tags.avgRefs 22.494096 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches3.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches3.tags.occupancies::cache_hierarchy.l1dcaches3.prefetcher 313.925458 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches3.tags.occupancies::processor.cores3.core.data 195.710040 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches3.tags.avgOccs::cache_hierarchy.l1dcaches3.prefetcher 0.613136 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches3.tags.avgOccs::processor.cores3.core.data 0.382246 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches3.tags.avgOccs::total 0.995382 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches3.tags.occupanciesTaskId::1022 20 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches3.tags.occupanciesTaskId::1024 492 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches3.tags.ageTaskId_1022::1 14 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches3.tags.ageTaskId_1022::2 6 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches3.tags.ageTaskId_1024::0 11 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches3.tags.ageTaskId_1024::1 124 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches3.tags.ageTaskId_1024::2 357 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches3.tags.ratioOccsTaskId::1022 0.039062 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches3.tags.ratioOccsTaskId::1024 0.960938 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches3.tags.tagAccesses 473824919 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches3.tags.dataAccesses 473824919 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches3.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches4.demandHits::processor.cores4.core.data 58666886 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches4.demandHits::total 58666886 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches4.overallHits::processor.cores4.core.data 58666886 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches4.overallHits::total 58666886 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches4.demandMisses::processor.cores4.core.data 751474 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches4.demandMisses::total 751474 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches4.overallMisses::processor.cores4.core.data 751474 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches4.overallMisses::total 751474 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches4.demandMissLatency::processor.cores4.core.data 29288102992 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.demandMissLatency::total 29288102992 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.overallMissLatency::processor.cores4.core.data 29288102992 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.overallMissLatency::total 29288102992 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.demandAccesses::processor.cores4.core.data 59418360 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches4.demandAccesses::total 59418360 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches4.overallAccesses::processor.cores4.core.data 59418360 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches4.overallAccesses::total 59418360 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches4.demandMissRate::processor.cores4.core.data 0.012647 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches4.demandMissRate::total 0.012647 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches4.overallMissRate::processor.cores4.core.data 0.012647 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches4.overallMissRate::total 0.012647 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches4.demandAvgMissLatency::processor.cores4.core.data 38974.206682 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches4.demandAvgMissLatency::total 38974.206682 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches4.overallAvgMissLatency::processor.cores4.core.data 38974.206682 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.overallAvgMissLatency::total 38974.206682 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches4.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches4.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches4.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches4.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches4.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches4.writebacks::writebacks 929951 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches4.writebacks::total 929951 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches4.demandMshrHits::processor.cores4.core.data 25413 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches4.demandMshrHits::total 25413 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches4.overallMshrHits::processor.cores4.core.data 25413 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches4.overallMshrHits::total 25413 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches4.demandMshrMisses::processor.cores4.core.data 726061 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches4.demandMshrMisses::total 726061 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches4.overallMshrMisses::cache_hierarchy.l1dcaches4.prefetcher 1733797 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches4.overallMshrMisses::processor.cores4.core.data 726061 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches4.overallMshrMisses::total 2459858 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches4.demandMshrMissLatency::processor.cores4.core.data 27724818994 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.demandMshrMissLatency::total 27724818994 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.overallMshrMissLatency::cache_hierarchy.l1dcaches4.prefetcher 89977018175 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.overallMshrMissLatency::processor.cores4.core.data 27724818994 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.overallMshrMissLatency::total 117701837169 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.demandMshrMissRate::processor.cores4.core.data 0.012219 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches4.demandMshrMissRate::total 0.012219 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches4.overallMshrMissRate::cache_hierarchy.l1dcaches4.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches4.overallMshrMissRate::processor.cores4.core.data 0.012219 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches4.overallMshrMissRate::total 0.041399 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches4.demandAvgMshrMissLatency::processor.cores4.core.data 38185.247512 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.demandAvgMshrMissLatency::total 38185.247512 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches4.prefetcher 51895.936015 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.overallAvgMshrMissLatency::processor.cores4.core.data 38185.247512 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.overallAvgMshrMissLatency::total 47849.037290 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.replacements 2271598 # number of replacements (Count)
board.cache_hierarchy.l1dcaches4.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches4.prefetcher 1733797 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches4.HardPFReq.mshrMisses::total 1733797 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches4.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches4.prefetcher 89977018175 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.HardPFReq.mshrMissLatency::total 89977018175 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches4.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches4.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches4.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches4.prefetcher 51895.936015 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.HardPFReq.avgMshrMissLatency::total 51895.936015 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.LockedRMWReadReq.misses::processor.cores4.core.data 95 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1dcaches4.LockedRMWReadReq.misses::total 95 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1dcaches4.LockedRMWReadReq.missLatency::processor.cores4.core.data 5461000 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.LockedRMWReadReq.missLatency::total 5461000 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.LockedRMWReadReq.accesses::processor.cores4.core.data 95 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches4.LockedRMWReadReq.accesses::total 95 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches4.LockedRMWReadReq.missRate::processor.cores4.core.data 1 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches4.LockedRMWReadReq.missRate::total 1 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches4.LockedRMWReadReq.avgMissLatency::processor.cores4.core.data 57484.210526 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.LockedRMWReadReq.avgMissLatency::total 57484.210526 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.LockedRMWReadReq.mshrMisses::processor.cores4.core.data 95 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches4.LockedRMWReadReq.mshrMisses::total 95 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches4.LockedRMWReadReq.mshrMissLatency::processor.cores4.core.data 10874500 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.LockedRMWReadReq.mshrMissLatency::total 10874500 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.LockedRMWReadReq.mshrMissRate::processor.cores4.core.data 1 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches4.LockedRMWReadReq.mshrMissRate::total 1 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches4.LockedRMWReadReq.avgMshrMissLatency::processor.cores4.core.data 114468.421053 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.LockedRMWReadReq.avgMshrMissLatency::total 114468.421053 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.LockedRMWWriteReq.hits::processor.cores4.core.data 95 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1dcaches4.LockedRMWWriteReq.hits::total 95 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1dcaches4.LockedRMWWriteReq.accesses::processor.cores4.core.data 95 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches4.LockedRMWWriteReq.accesses::total 95 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.hits::processor.cores4.core.data 49094212 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.hits::total 49094212 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.misses::processor.cores4.core.data 496002 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.misses::total 496002 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.missLatency::processor.cores4.core.data 19602916492 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.ReadReq.missLatency::total 19602916492 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.ReadReq.accesses::processor.cores4.core.data 49590214 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.accesses::total 49590214 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.missRate::processor.cores4.core.data 0.010002 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches4.ReadReq.missRate::total 0.010002 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches4.ReadReq.avgMissLatency::processor.cores4.core.data 39521.849694 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.ReadReq.avgMissLatency::total 39521.849694 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.ReadReq.mshrHits::processor.cores4.core.data 21121 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.mshrHits::total 21121 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.mshrMisses::processor.cores4.core.data 474881 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.mshrMisses::total 474881 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches4.ReadReq.mshrMissLatency::processor.cores4.core.data 18376987494 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.ReadReq.mshrMissLatency::total 18376987494 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.ReadReq.mshrMissRate::processor.cores4.core.data 0.009576 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches4.ReadReq.mshrMissRate::total 0.009576 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches4.ReadReq.avgMshrMissLatency::processor.cores4.core.data 38698.089614 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.ReadReq.avgMshrMissLatency::total 38698.089614 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.WriteReq.hits::processor.cores4.core.data 9572674 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches4.WriteReq.hits::total 9572674 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches4.WriteReq.misses::processor.cores4.core.data 255472 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches4.WriteReq.misses::total 255472 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches4.WriteReq.missLatency::processor.cores4.core.data 9685186500 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.WriteReq.missLatency::total 9685186500 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.WriteReq.accesses::processor.cores4.core.data 9828146 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches4.WriteReq.accesses::total 9828146 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches4.WriteReq.missRate::processor.cores4.core.data 0.025994 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches4.WriteReq.missRate::total 0.025994 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches4.WriteReq.avgMissLatency::processor.cores4.core.data 37910.951102 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.WriteReq.avgMissLatency::total 37910.951102 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.WriteReq.mshrHits::processor.cores4.core.data 4292 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches4.WriteReq.mshrHits::total 4292 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches4.WriteReq.mshrMisses::processor.cores4.core.data 251180 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches4.WriteReq.mshrMisses::total 251180 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches4.WriteReq.mshrMissLatency::processor.cores4.core.data 9347831500 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.WriteReq.mshrMissLatency::total 9347831500 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches4.WriteReq.mshrMissRate::processor.cores4.core.data 0.025557 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches4.WriteReq.mshrMissRate::total 0.025557 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches4.WriteReq.avgMshrMissLatency::processor.cores4.core.data 37215.668047 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.WriteReq.avgMshrMissLatency::total 37215.668047 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches4.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches4.prefetcher.demandMshrMisses 726061 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfIssued 5068824 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfUnused 77696 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfUseful 1631263 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfUsefulButMiss 586 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.accuracy 0.321823 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.coverage 0.691998 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfHitInCache 3209470 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfHitInMSHR 125555 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfHitInWB 2 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfLate 3335027 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfIdentified 5249764 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfBufferHit 127946 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfRemovedDemand 37097 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfRemovedFull 14455 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfSpanPage 858980 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.pfUsefulSpanPage 516808 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches4.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches4.tags.tagsInUse 507.349341 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches4.tags.totalRefs 60179147 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches4.tags.sampledRefs 2400092 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches4.tags.avgRefs 25.073683 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches4.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches4.tags.occupancies::cache_hierarchy.l1dcaches4.prefetcher 312.118881 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches4.tags.occupancies::processor.cores4.core.data 195.230460 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches4.tags.avgOccs::cache_hierarchy.l1dcaches4.prefetcher 0.609607 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches4.tags.avgOccs::processor.cores4.core.data 0.381309 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches4.tags.avgOccs::total 0.990917 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches4.tags.occupanciesTaskId::1022 423 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches4.tags.occupanciesTaskId::1024 89 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches4.tags.ageTaskId_1022::3 423 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches4.tags.ageTaskId_1024::3 89 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches4.tags.ratioOccsTaskId::1022 0.826172 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches4.tags.ratioOccsTaskId::1024 0.173828 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches4.tags.tagAccesses 477748979 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches4.tags.dataAccesses 477748979 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches4.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches5.demandHits::processor.cores5.core.data 58786118 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches5.demandHits::total 58786118 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches5.overallHits::processor.cores5.core.data 58786118 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches5.overallHits::total 58786118 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches5.demandMisses::processor.cores5.core.data 755038 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches5.demandMisses::total 755038 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches5.overallMisses::processor.cores5.core.data 755038 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches5.overallMisses::total 755038 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches5.demandMissLatency::processor.cores5.core.data 29037160993 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.demandMissLatency::total 29037160993 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.overallMissLatency::processor.cores5.core.data 29037160993 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.overallMissLatency::total 29037160993 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.demandAccesses::processor.cores5.core.data 59541156 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches5.demandAccesses::total 59541156 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches5.overallAccesses::processor.cores5.core.data 59541156 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches5.overallAccesses::total 59541156 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches5.demandMissRate::processor.cores5.core.data 0.012681 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches5.demandMissRate::total 0.012681 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches5.overallMissRate::processor.cores5.core.data 0.012681 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches5.overallMissRate::total 0.012681 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches5.demandAvgMissLatency::processor.cores5.core.data 38457.880256 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches5.demandAvgMissLatency::total 38457.880256 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches5.overallAvgMissLatency::processor.cores5.core.data 38457.880256 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.overallAvgMissLatency::total 38457.880256 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches5.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches5.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches5.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches5.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches5.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches5.writebacks::writebacks 927492 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches5.writebacks::total 927492 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches5.demandMshrHits::processor.cores5.core.data 25254 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches5.demandMshrHits::total 25254 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches5.overallMshrHits::processor.cores5.core.data 25254 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches5.overallMshrHits::total 25254 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches5.demandMshrMisses::processor.cores5.core.data 729784 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches5.demandMshrMisses::total 729784 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches5.overallMshrMisses::cache_hierarchy.l1dcaches5.prefetcher 1729861 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches5.overallMshrMisses::processor.cores5.core.data 729784 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches5.overallMshrMisses::total 2459645 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches5.demandMshrMissLatency::processor.cores5.core.data 27492348993 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.demandMshrMissLatency::total 27492348993 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.overallMshrMissLatency::cache_hierarchy.l1dcaches5.prefetcher 88154826594 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.overallMshrMissLatency::processor.cores5.core.data 27492348993 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.overallMshrMissLatency::total 115647175587 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.demandMshrMissRate::processor.cores5.core.data 0.012257 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches5.demandMshrMissRate::total 0.012257 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches5.overallMshrMissRate::cache_hierarchy.l1dcaches5.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches5.overallMshrMissRate::processor.cores5.core.data 0.012257 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches5.overallMshrMissRate::total 0.041310 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches5.demandAvgMshrMissLatency::processor.cores5.core.data 37671.898799 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.demandAvgMshrMissLatency::total 37671.898799 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches5.prefetcher 50960.641690 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.overallAvgMshrMissLatency::processor.cores5.core.data 37671.898799 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.overallAvgMshrMissLatency::total 47017.832080 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.replacements 2270270 # number of replacements (Count)
board.cache_hierarchy.l1dcaches5.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches5.prefetcher 1729861 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches5.HardPFReq.mshrMisses::total 1729861 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches5.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches5.prefetcher 88154826594 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.HardPFReq.mshrMissLatency::total 88154826594 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches5.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches5.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches5.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches5.prefetcher 50960.641690 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.HardPFReq.avgMshrMissLatency::total 50960.641690 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.LockedRMWReadReq.misses::processor.cores5.core.data 95 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1dcaches5.LockedRMWReadReq.misses::total 95 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1dcaches5.LockedRMWReadReq.missLatency::processor.cores5.core.data 3346000 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.LockedRMWReadReq.missLatency::total 3346000 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.LockedRMWReadReq.accesses::processor.cores5.core.data 95 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches5.LockedRMWReadReq.accesses::total 95 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches5.LockedRMWReadReq.missRate::processor.cores5.core.data 1 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches5.LockedRMWReadReq.missRate::total 1 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches5.LockedRMWReadReq.avgMissLatency::processor.cores5.core.data 35221.052632 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.LockedRMWReadReq.avgMissLatency::total 35221.052632 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.LockedRMWReadReq.mshrMisses::processor.cores5.core.data 95 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches5.LockedRMWReadReq.mshrMisses::total 95 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches5.LockedRMWReadReq.mshrMissLatency::processor.cores5.core.data 6644500 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.LockedRMWReadReq.mshrMissLatency::total 6644500 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.LockedRMWReadReq.mshrMissRate::processor.cores5.core.data 1 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches5.LockedRMWReadReq.mshrMissRate::total 1 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches5.LockedRMWReadReq.avgMshrMissLatency::processor.cores5.core.data 69942.105263 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.LockedRMWReadReq.avgMshrMissLatency::total 69942.105263 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.LockedRMWWriteReq.hits::processor.cores5.core.data 95 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1dcaches5.LockedRMWWriteReq.hits::total 95 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1dcaches5.LockedRMWWriteReq.accesses::processor.cores5.core.data 95 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches5.LockedRMWWriteReq.accesses::total 95 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.hits::processor.cores5.core.data 49155953 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.hits::total 49155953 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.misses::processor.cores5.core.data 501342 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.misses::total 501342 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.missLatency::processor.cores5.core.data 19482002495 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.ReadReq.missLatency::total 19482002495 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.ReadReq.accesses::processor.cores5.core.data 49657295 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.accesses::total 49657295 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.missRate::processor.cores5.core.data 0.010096 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches5.ReadReq.missRate::total 0.010096 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches5.ReadReq.avgMissLatency::processor.cores5.core.data 38859.705540 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.ReadReq.avgMissLatency::total 38859.705540 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.ReadReq.mshrHits::processor.cores5.core.data 20801 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.mshrHits::total 20801 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.mshrMisses::processor.cores5.core.data 480541 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.mshrMisses::total 480541 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches5.ReadReq.mshrMissLatency::processor.cores5.core.data 18270468995 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.ReadReq.mshrMissLatency::total 18270468995 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.ReadReq.mshrMissRate::processor.cores5.core.data 0.009677 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches5.ReadReq.mshrMissRate::total 0.009677 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches5.ReadReq.avgMshrMissLatency::processor.cores5.core.data 38020.624661 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.ReadReq.avgMshrMissLatency::total 38020.624661 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.WriteReq.hits::processor.cores5.core.data 9630165 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches5.WriteReq.hits::total 9630165 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches5.WriteReq.misses::processor.cores5.core.data 253696 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches5.WriteReq.misses::total 253696 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches5.WriteReq.missLatency::processor.cores5.core.data 9555158498 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.WriteReq.missLatency::total 9555158498 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.WriteReq.accesses::processor.cores5.core.data 9883861 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches5.WriteReq.accesses::total 9883861 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches5.WriteReq.missRate::processor.cores5.core.data 0.025668 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches5.WriteReq.missRate::total 0.025668 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches5.WriteReq.avgMissLatency::processor.cores5.core.data 37663.812193 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.WriteReq.avgMissLatency::total 37663.812193 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.WriteReq.mshrHits::processor.cores5.core.data 4453 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches5.WriteReq.mshrHits::total 4453 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches5.WriteReq.mshrMisses::processor.cores5.core.data 249243 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches5.WriteReq.mshrMisses::total 249243 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches5.WriteReq.mshrMissLatency::processor.cores5.core.data 9221879998 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.WriteReq.mshrMissLatency::total 9221879998 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches5.WriteReq.mshrMissRate::processor.cores5.core.data 0.025217 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches5.WriteReq.mshrMissRate::total 0.025217 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches5.WriteReq.avgMshrMissLatency::processor.cores5.core.data 36999.554643 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.WriteReq.avgMshrMissLatency::total 36999.554643 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches5.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches5.prefetcher.demandMshrMisses 729784 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfIssued 5066835 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfUnused 78213 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfUseful 1627346 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfUsefulButMiss 824 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.accuracy 0.321176 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.coverage 0.690393 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfHitInCache 3214117 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfHitInMSHR 122850 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfHitInWB 7 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfLate 3336974 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfIdentified 5227867 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfBufferHit 110058 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfRemovedDemand 33450 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfRemovedFull 16454 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfSpanPage 866753 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.pfUsefulSpanPage 514991 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches5.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches5.tags.tagsInUse 504.561713 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches5.tags.totalRefs 60499322 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches5.tags.sampledRefs 2405515 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches5.tags.avgRefs 25.150258 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches5.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches5.tags.occupancies::cache_hierarchy.l1dcaches5.prefetcher 311.163835 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches5.tags.occupancies::processor.cores5.core.data 193.397878 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches5.tags.avgOccs::cache_hierarchy.l1dcaches5.prefetcher 0.607742 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches5.tags.avgOccs::processor.cores5.core.data 0.377730 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches5.tags.avgOccs::total 0.985472 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches5.tags.occupanciesTaskId::1022 426 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches5.tags.occupanciesTaskId::1024 86 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches5.tags.ageTaskId_1022::3 426 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches5.tags.ageTaskId_1024::3 86 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches5.tags.ratioOccsTaskId::1022 0.832031 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches5.tags.ratioOccsTaskId::1024 0.167969 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches5.tags.tagAccesses 478736770 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches5.tags.dataAccesses 478736770 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches5.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches6.demandHits::processor.cores6.core.data 58001640 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches6.demandHits::total 58001640 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches6.overallHits::processor.cores6.core.data 58001640 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches6.overallHits::total 58001640 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches6.demandMisses::processor.cores6.core.data 831925 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches6.demandMisses::total 831925 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches6.overallMisses::processor.cores6.core.data 831925 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches6.overallMisses::total 831925 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches6.demandMissLatency::processor.cores6.core.data 32923563992 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.demandMissLatency::total 32923563992 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.overallMissLatency::processor.cores6.core.data 32923563992 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.overallMissLatency::total 32923563992 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.demandAccesses::processor.cores6.core.data 58833565 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches6.demandAccesses::total 58833565 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches6.overallAccesses::processor.cores6.core.data 58833565 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches6.overallAccesses::total 58833565 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches6.demandMissRate::processor.cores6.core.data 0.014140 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches6.demandMissRate::total 0.014140 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches6.overallMissRate::processor.cores6.core.data 0.014140 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches6.overallMissRate::total 0.014140 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches6.demandAvgMissLatency::processor.cores6.core.data 39575.158809 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches6.demandAvgMissLatency::total 39575.158809 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches6.overallAvgMissLatency::processor.cores6.core.data 39575.158809 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.overallAvgMissLatency::total 39575.158809 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches6.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches6.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches6.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches6.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches6.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches6.writebacks::writebacks 1062311 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches6.writebacks::total 1062311 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches6.demandMshrHits::processor.cores6.core.data 26867 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches6.demandMshrHits::total 26867 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches6.overallMshrHits::processor.cores6.core.data 26867 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches6.overallMshrHits::total 26867 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches6.demandMshrMisses::processor.cores6.core.data 805058 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches6.demandMshrMisses::total 805058 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches6.overallMshrMisses::cache_hierarchy.l1dcaches6.prefetcher 1935169 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches6.overallMshrMisses::processor.cores6.core.data 805058 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches6.overallMshrMisses::total 2740227 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches6.demandMshrMissLatency::processor.cores6.core.data 31268667993 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.demandMshrMissLatency::total 31268667993 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.overallMshrMissLatency::cache_hierarchy.l1dcaches6.prefetcher 95756013422 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.overallMshrMissLatency::processor.cores6.core.data 31268667993 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.overallMshrMissLatency::total 127024681415 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.demandMshrMissRate::processor.cores6.core.data 0.013684 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches6.demandMshrMissRate::total 0.013684 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches6.overallMshrMissRate::cache_hierarchy.l1dcaches6.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches6.overallMshrMissRate::processor.cores6.core.data 0.013684 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches6.overallMshrMissRate::total 0.046576 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches6.demandAvgMshrMissLatency::processor.cores6.core.data 38840.267401 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.demandAvgMshrMissLatency::total 38840.267401 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches6.prefetcher 49481.990163 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.overallAvgMshrMissLatency::processor.cores6.core.data 38840.267401 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.overallAvgMshrMissLatency::total 46355.532376 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.replacements 2562497 # number of replacements (Count)
board.cache_hierarchy.l1dcaches6.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches6.prefetcher 1935169 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches6.HardPFReq.mshrMisses::total 1935169 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches6.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches6.prefetcher 95756013422 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.HardPFReq.mshrMissLatency::total 95756013422 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches6.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches6.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches6.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches6.prefetcher 49481.990163 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.HardPFReq.avgMshrMissLatency::total 49481.990163 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.LockedRMWReadReq.misses::processor.cores6.core.data 94 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1dcaches6.LockedRMWReadReq.misses::total 94 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1dcaches6.LockedRMWReadReq.missLatency::processor.cores6.core.data 3137500 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.LockedRMWReadReq.missLatency::total 3137500 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.LockedRMWReadReq.accesses::processor.cores6.core.data 94 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches6.LockedRMWReadReq.accesses::total 94 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches6.LockedRMWReadReq.missRate::processor.cores6.core.data 1 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches6.LockedRMWReadReq.missRate::total 1 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches6.LockedRMWReadReq.avgMissLatency::processor.cores6.core.data 33377.659574 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.LockedRMWReadReq.avgMissLatency::total 33377.659574 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.LockedRMWReadReq.mshrMisses::processor.cores6.core.data 94 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches6.LockedRMWReadReq.mshrMisses::total 94 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches6.LockedRMWReadReq.mshrMissLatency::processor.cores6.core.data 6228000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.LockedRMWReadReq.mshrMissLatency::total 6228000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.LockedRMWReadReq.mshrMissRate::processor.cores6.core.data 1 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches6.LockedRMWReadReq.mshrMissRate::total 1 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches6.LockedRMWReadReq.avgMshrMissLatency::processor.cores6.core.data 66255.319149 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.LockedRMWReadReq.avgMshrMissLatency::total 66255.319149 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.LockedRMWWriteReq.hits::processor.cores6.core.data 94 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1dcaches6.LockedRMWWriteReq.hits::total 94 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1dcaches6.LockedRMWWriteReq.accesses::processor.cores6.core.data 94 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches6.LockedRMWWriteReq.accesses::total 94 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches6.ReadReq.hits::processor.cores6.core.data 48019714 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches6.ReadReq.hits::total 48019714 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches6.ReadReq.misses::processor.cores6.core.data 565847 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches6.ReadReq.misses::total 565847 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches6.ReadReq.missLatency::processor.cores6.core.data 22369840493 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.ReadReq.missLatency::total 22369840493 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.ReadReq.accesses::processor.cores6.core.data 48585561 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches6.ReadReq.accesses::total 48585561 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches6.ReadReq.missRate::processor.cores6.core.data 0.011646 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches6.ReadReq.missRate::total 0.011646 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches6.ReadReq.avgMissLatency::processor.cores6.core.data 39533.372967 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.ReadReq.avgMissLatency::total 39533.372967 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.ReadReq.mshrHits::processor.cores6.core.data 22498 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches6.ReadReq.mshrHits::total 22498 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches6.ReadReq.mshrMisses::processor.cores6.core.data 543349 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches6.ReadReq.mshrMisses::total 543349 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches6.ReadReq.mshrMissLatency::processor.cores6.core.data 21055208993 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.ReadReq.mshrMissLatency::total 21055208993 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.ReadReq.mshrMissRate::processor.cores6.core.data 0.011183 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches6.ReadReq.mshrMissRate::total 0.011183 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches6.ReadReq.avgMshrMissLatency::processor.cores6.core.data 38750.801038 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.ReadReq.avgMshrMissLatency::total 38750.801038 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.WriteReq.hits::processor.cores6.core.data 9981926 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches6.WriteReq.hits::total 9981926 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches6.WriteReq.misses::processor.cores6.core.data 266078 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches6.WriteReq.misses::total 266078 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches6.WriteReq.missLatency::processor.cores6.core.data 10553723499 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.WriteReq.missLatency::total 10553723499 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.WriteReq.accesses::processor.cores6.core.data 10248004 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches6.WriteReq.accesses::total 10248004 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches6.WriteReq.missRate::processor.cores6.core.data 0.025964 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches6.WriteReq.missRate::total 0.025964 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches6.WriteReq.avgMissLatency::processor.cores6.core.data 39664.021449 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.WriteReq.avgMissLatency::total 39664.021449 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.WriteReq.mshrHits::processor.cores6.core.data 4369 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches6.WriteReq.mshrHits::total 4369 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches6.WriteReq.mshrMisses::processor.cores6.core.data 261709 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches6.WriteReq.mshrMisses::total 261709 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches6.WriteReq.mshrMissLatency::processor.cores6.core.data 10213459000 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.WriteReq.mshrMissLatency::total 10213459000 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches6.WriteReq.mshrMissRate::processor.cores6.core.data 0.025538 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches6.WriteReq.mshrMissRate::total 0.025538 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches6.WriteReq.avgMshrMissLatency::processor.cores6.core.data 39026.013626 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.WriteReq.avgMshrMissLatency::total 39026.013626 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches6.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches6.prefetcher.demandMshrMisses 805058 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches6.prefetcher.pfIssued 5640220 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches6.prefetcher.pfUnused 82929 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1dcaches6.prefetcher.pfUseful 1825716 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches6.prefetcher.pfUsefulButMiss 316 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches6.prefetcher.accuracy 0.323696 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches6.prefetcher.coverage 0.693984 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches6.prefetcher.pfHitInCache 3575848 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches6.prefetcher.pfHitInMSHR 129194 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches6.prefetcher.pfHitInWB 9 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches6.prefetcher.pfLate 3705051 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches6.prefetcher.pfIdentified 5811575 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches6.prefetcher.pfBufferHit 121632 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches6.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches6.prefetcher.pfRemovedDemand 35353 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches6.prefetcher.pfRemovedFull 12954 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches6.prefetcher.pfSpanPage 930789 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches6.prefetcher.pfUsefulSpanPage 580471 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches6.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches6.tags.tagsInUse 507.205021 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches6.tags.totalRefs 60674424 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches6.tags.sampledRefs 2677552 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches6.tags.avgRefs 22.660409 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches6.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches6.tags.occupancies::cache_hierarchy.l1dcaches6.prefetcher 312.468627 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches6.tags.occupancies::processor.cores6.core.data 194.736394 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches6.tags.avgOccs::cache_hierarchy.l1dcaches6.prefetcher 0.610290 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches6.tags.avgOccs::processor.cores6.core.data 0.380345 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches6.tags.avgOccs::total 0.990635 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches6.tags.occupanciesTaskId::1022 38 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches6.tags.occupanciesTaskId::1024 474 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches6.tags.ageTaskId_1022::2 38 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches6.tags.ageTaskId_1024::0 24 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches6.tags.ageTaskId_1024::1 253 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches6.tags.ageTaskId_1024::2 197 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches6.tags.ratioOccsTaskId::1022 0.074219 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches6.tags.ratioOccsTaskId::1024 0.925781 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches6.tags.tagAccesses 473348063 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches6.tags.dataAccesses 473348063 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches6.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches7.demandHits::processor.cores7.core.data 58659784 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches7.demandHits::total 58659784 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches7.overallHits::processor.cores7.core.data 58659784 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches7.overallHits::total 58659784 # number of overall hits (Count)
board.cache_hierarchy.l1dcaches7.demandMisses::processor.cores7.core.data 760946 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches7.demandMisses::total 760946 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches7.overallMisses::processor.cores7.core.data 760946 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches7.overallMisses::total 760946 # number of overall misses (Count)
board.cache_hierarchy.l1dcaches7.demandMissLatency::processor.cores7.core.data 29316309494 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.demandMissLatency::total 29316309494 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.overallMissLatency::processor.cores7.core.data 29316309494 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.overallMissLatency::total 29316309494 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.demandAccesses::processor.cores7.core.data 59420730 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches7.demandAccesses::total 59420730 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches7.overallAccesses::processor.cores7.core.data 59420730 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches7.overallAccesses::total 59420730 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches7.demandMissRate::processor.cores7.core.data 0.012806 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches7.demandMissRate::total 0.012806 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches7.overallMissRate::processor.cores7.core.data 0.012806 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches7.overallMissRate::total 0.012806 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches7.demandAvgMissLatency::processor.cores7.core.data 38526.136538 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches7.demandAvgMissLatency::total 38526.136538 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches7.overallAvgMissLatency::processor.cores7.core.data 38526.136538 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.overallAvgMissLatency::total 38526.136538 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches7.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches7.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches7.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches7.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches7.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches7.writebacks::writebacks 925099 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches7.writebacks::total 925099 # number of writebacks (Count)
board.cache_hierarchy.l1dcaches7.demandMshrHits::processor.cores7.core.data 25356 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches7.demandMshrHits::total 25356 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches7.overallMshrHits::processor.cores7.core.data 25356 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches7.overallMshrHits::total 25356 # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches7.demandMshrMisses::processor.cores7.core.data 735590 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches7.demandMshrMisses::total 735590 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches7.overallMshrMisses::cache_hierarchy.l1dcaches7.prefetcher 1730849 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches7.overallMshrMisses::processor.cores7.core.data 735590 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches7.overallMshrMisses::total 2466439 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches7.demandMshrMissLatency::processor.cores7.core.data 27749731494 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.demandMshrMissLatency::total 27749731494 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.overallMshrMissLatency::cache_hierarchy.l1dcaches7.prefetcher 89787627956 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.overallMshrMissLatency::processor.cores7.core.data 27749731494 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.overallMshrMissLatency::total 117537359450 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.demandMshrMissRate::processor.cores7.core.data 0.012379 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches7.demandMshrMissRate::total 0.012379 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches7.overallMshrMissRate::cache_hierarchy.l1dcaches7.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches7.overallMshrMissRate::processor.cores7.core.data 0.012379 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches7.overallMshrMissRate::total 0.041508 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches7.demandAvgMshrMissLatency::processor.cores7.core.data 37724.454511 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.demandAvgMshrMissLatency::total 37724.454511 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches7.prefetcher 51874.905296 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.overallAvgMshrMissLatency::processor.cores7.core.data 37724.454511 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.overallAvgMshrMissLatency::total 47654.679256 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.replacements 2272008 # number of replacements (Count)
board.cache_hierarchy.l1dcaches7.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches7.prefetcher 1730849 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches7.HardPFReq.mshrMisses::total 1730849 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches7.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches7.prefetcher 89787627956 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.HardPFReq.mshrMissLatency::total 89787627956 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches7.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches7.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches7.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches7.prefetcher 51874.905296 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.HardPFReq.avgMshrMissLatency::total 51874.905296 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.LockedRMWReadReq.hits::processor.cores7.core.data 203 # number of LockedRMWReadReq hits (Count)
board.cache_hierarchy.l1dcaches7.LockedRMWReadReq.hits::total 203 # number of LockedRMWReadReq hits (Count)
board.cache_hierarchy.l1dcaches7.LockedRMWReadReq.misses::processor.cores7.core.data 177 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1dcaches7.LockedRMWReadReq.misses::total 177 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.l1dcaches7.LockedRMWReadReq.missLatency::processor.cores7.core.data 4368000 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.LockedRMWReadReq.missLatency::total 4368000 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.LockedRMWReadReq.accesses::processor.cores7.core.data 380 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches7.LockedRMWReadReq.accesses::total 380 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches7.LockedRMWReadReq.missRate::processor.cores7.core.data 0.465789 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches7.LockedRMWReadReq.missRate::total 0.465789 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches7.LockedRMWReadReq.avgMissLatency::processor.cores7.core.data 24677.966102 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.LockedRMWReadReq.avgMissLatency::total 24677.966102 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.LockedRMWReadReq.mshrMisses::processor.cores7.core.data 177 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches7.LockedRMWReadReq.mshrMisses::total 177 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches7.LockedRMWReadReq.mshrMissLatency::processor.cores7.core.data 8749000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.LockedRMWReadReq.mshrMissLatency::total 8749000 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.LockedRMWReadReq.mshrMissRate::processor.cores7.core.data 0.465789 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches7.LockedRMWReadReq.mshrMissRate::total 0.465789 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches7.LockedRMWReadReq.avgMshrMissLatency::processor.cores7.core.data 49429.378531 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.LockedRMWReadReq.avgMshrMissLatency::total 49429.378531 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.LockedRMWWriteReq.hits::processor.cores7.core.data 380 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1dcaches7.LockedRMWWriteReq.hits::total 380 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.l1dcaches7.LockedRMWWriteReq.accesses::processor.cores7.core.data 380 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches7.LockedRMWWriteReq.accesses::total 380 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches7.ReadReq.hits::processor.cores7.core.data 49096935 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches7.ReadReq.hits::total 49096935 # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches7.ReadReq.misses::processor.cores7.core.data 502411 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches7.ReadReq.misses::total 502411 # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches7.ReadReq.missLatency::processor.cores7.core.data 19762516494 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.ReadReq.missLatency::total 19762516494 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.ReadReq.accesses::processor.cores7.core.data 49599346 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches7.ReadReq.accesses::total 49599346 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches7.ReadReq.missRate::processor.cores7.core.data 0.010129 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches7.ReadReq.missRate::total 0.010129 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches7.ReadReq.avgMissLatency::processor.cores7.core.data 39335.357892 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.ReadReq.avgMissLatency::total 39335.357892 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.ReadReq.mshrHits::processor.cores7.core.data 20653 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches7.ReadReq.mshrHits::total 20653 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches7.ReadReq.mshrMisses::processor.cores7.core.data 481758 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches7.ReadReq.mshrMisses::total 481758 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches7.ReadReq.mshrMissLatency::processor.cores7.core.data 18550267494 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.ReadReq.mshrMissLatency::total 18550267494 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.ReadReq.mshrMissRate::processor.cores7.core.data 0.009713 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches7.ReadReq.mshrMissRate::total 0.009713 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches7.ReadReq.avgMshrMissLatency::processor.cores7.core.data 38505.364714 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.ReadReq.avgMshrMissLatency::total 38505.364714 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.WriteReq.hits::processor.cores7.core.data 9562849 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches7.WriteReq.hits::total 9562849 # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches7.WriteReq.misses::processor.cores7.core.data 258535 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches7.WriteReq.misses::total 258535 # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches7.WriteReq.missLatency::processor.cores7.core.data 9553793000 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.WriteReq.missLatency::total 9553793000 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.WriteReq.accesses::processor.cores7.core.data 9821384 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches7.WriteReq.accesses::total 9821384 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches7.WriteReq.missRate::processor.cores7.core.data 0.026324 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches7.WriteReq.missRate::total 0.026324 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches7.WriteReq.avgMissLatency::processor.cores7.core.data 36953.576885 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.WriteReq.avgMissLatency::total 36953.576885 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.WriteReq.mshrHits::processor.cores7.core.data 4703 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches7.WriteReq.mshrHits::total 4703 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches7.WriteReq.mshrMisses::processor.cores7.core.data 253832 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches7.WriteReq.mshrMisses::total 253832 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches7.WriteReq.mshrMissLatency::processor.cores7.core.data 9199464000 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.WriteReq.mshrMissLatency::total 9199464000 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches7.WriteReq.mshrMissRate::processor.cores7.core.data 0.025845 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches7.WriteReq.mshrMissRate::total 0.025845 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches7.WriteReq.avgMshrMissLatency::processor.cores7.core.data 36242.333512 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.WriteReq.avgMshrMissLatency::total 36242.333512 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches7.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches7.prefetcher.demandMshrMisses 735590 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches7.prefetcher.pfIssued 5057251 # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches7.prefetcher.pfUnused 80335 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1dcaches7.prefetcher.pfUseful 1625933 # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches7.prefetcher.pfUsefulButMiss 726 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches7.prefetcher.accuracy 0.321505 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches7.prefetcher.coverage 0.688510 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches7.prefetcher.pfHitInCache 3201860 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches7.prefetcher.pfHitInMSHR 124537 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches7.prefetcher.pfHitInWB 5 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches7.prefetcher.pfLate 3326402 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches7.prefetcher.pfIdentified 5236288 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches7.prefetcher.pfBufferHit 124354 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches7.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches7.prefetcher.pfRemovedDemand 36616 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches7.prefetcher.pfRemovedFull 16940 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches7.prefetcher.pfSpanPage 863448 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches7.prefetcher.pfUsefulSpanPage 514612 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches7.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches7.tags.tagsInUse 506.378106 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches7.tags.totalRefs 60171383 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches7.tags.sampledRefs 2406258 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches7.tags.avgRefs 25.006206 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches7.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches7.tags.occupancies::cache_hierarchy.l1dcaches7.prefetcher 311.450649 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches7.tags.occupancies::processor.cores7.core.data 194.927458 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches7.tags.avgOccs::cache_hierarchy.l1dcaches7.prefetcher 0.608302 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches7.tags.avgOccs::processor.cores7.core.data 0.380718 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches7.tags.avgOccs::total 0.989020 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches7.tags.occupanciesTaskId::1022 424 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches7.tags.occupanciesTaskId::1024 88 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches7.tags.ageTaskId_1022::3 424 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches7.tags.ageTaskId_1024::3 88 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches7.tags.ratioOccsTaskId::1022 0.828125 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches7.tags.ratioOccsTaskId::1024 0.171875 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches7.tags.tagAccesses 477778664 # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches7.tags.dataAccesses 477778664 # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches7.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches0.demandHits::processor.cores0.core.inst 156501287 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches0.demandHits::total 156501287 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches0.overallHits::processor.cores0.core.inst 156501287 # number of overall hits (Count)
board.cache_hierarchy.l1icaches0.overallHits::total 156501287 # number of overall hits (Count)
board.cache_hierarchy.l1icaches0.demandMisses::processor.cores0.core.inst 41354 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches0.demandMisses::total 41354 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches0.overallMisses::processor.cores0.core.inst 41354 # number of overall misses (Count)
board.cache_hierarchy.l1icaches0.overallMisses::total 41354 # number of overall misses (Count)
board.cache_hierarchy.l1icaches0.demandMissLatency::processor.cores0.core.inst 1527943000 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches0.demandMissLatency::total 1527943000 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches0.overallMissLatency::processor.cores0.core.inst 1527943000 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches0.overallMissLatency::total 1527943000 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches0.demandAccesses::processor.cores0.core.inst 156542641 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches0.demandAccesses::total 156542641 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches0.overallAccesses::processor.cores0.core.inst 156542641 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches0.overallAccesses::total 156542641 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches0.demandMissRate::processor.cores0.core.inst 0.000264 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches0.demandMissRate::total 0.000264 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches0.overallMissRate::processor.cores0.core.inst 0.000264 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches0.overallMissRate::total 0.000264 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches0.demandAvgMissLatency::processor.cores0.core.inst 36947.888959 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches0.demandAvgMissLatency::total 36947.888959 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches0.overallAvgMissLatency::processor.cores0.core.inst 36947.888959 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches0.overallAvgMissLatency::total 36947.888959 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches0.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches0.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches0.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches0.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches0.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches0.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches0.demandMshrMisses::processor.cores0.core.inst 41354 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches0.demandMshrMisses::total 41354 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches0.overallMshrMisses::processor.cores0.core.inst 41354 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches0.overallMshrMisses::total 41354 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches0.demandMshrMissLatency::processor.cores0.core.inst 1507265500 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches0.demandMshrMissLatency::total 1507265500 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches0.overallMshrMissLatency::processor.cores0.core.inst 1507265500 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches0.overallMshrMissLatency::total 1507265500 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches0.demandMshrMissRate::processor.cores0.core.inst 0.000264 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches0.demandMshrMissRate::total 0.000264 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches0.overallMshrMissRate::processor.cores0.core.inst 0.000264 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches0.overallMshrMissRate::total 0.000264 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches0.demandAvgMshrMissLatency::processor.cores0.core.inst 36447.876868 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches0.demandAvgMshrMissLatency::total 36447.876868 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches0.overallAvgMshrMissLatency::processor.cores0.core.inst 36447.876868 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches0.overallAvgMshrMissLatency::total 36447.876868 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches0.replacements 40897 # number of replacements (Count)
board.cache_hierarchy.l1icaches0.ReadReq.hits::processor.cores0.core.inst 156501287 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches0.ReadReq.hits::total 156501287 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches0.ReadReq.misses::processor.cores0.core.inst 41354 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches0.ReadReq.misses::total 41354 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches0.ReadReq.missLatency::processor.cores0.core.inst 1527943000 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches0.ReadReq.missLatency::total 1527943000 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches0.ReadReq.accesses::processor.cores0.core.inst 156542641 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches0.ReadReq.accesses::total 156542641 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches0.ReadReq.missRate::processor.cores0.core.inst 0.000264 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches0.ReadReq.missRate::total 0.000264 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches0.ReadReq.avgMissLatency::processor.cores0.core.inst 36947.888959 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches0.ReadReq.avgMissLatency::total 36947.888959 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches0.ReadReq.mshrMisses::processor.cores0.core.inst 41354 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches0.ReadReq.mshrMisses::total 41354 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches0.ReadReq.mshrMissLatency::processor.cores0.core.inst 1507265500 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches0.ReadReq.mshrMissLatency::total 1507265500 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches0.ReadReq.mshrMissRate::processor.cores0.core.inst 0.000264 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches0.ReadReq.mshrMissRate::total 0.000264 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches0.ReadReq.avgMshrMissLatency::processor.cores0.core.inst 36447.876868 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches0.ReadReq.avgMshrMissLatency::total 36447.876868 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches0.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches0.prefetcher.demandMshrMisses 41354 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches0.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches0.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches0.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches0.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches0.tags.tagsInUse 509.515008 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches0.tags.totalRefs 140638818 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches0.tags.sampledRefs 40897 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches0.tags.avgRefs 3438.854146 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches0.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches0.tags.occupancies::processor.cores0.core.inst 509.515008 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches0.tags.avgOccs::processor.cores0.core.inst 0.995146 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches0.tags.avgOccs::total 0.995146 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches0.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches0.tags.ageTaskId_1024::3 453 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches0.tags.ageTaskId_1024::4 59 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches0.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches0.tags.tagAccesses 1252382483 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches0.tags.dataAccesses 1252382483 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches0.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches1.demandHits::processor.cores1.core.inst 154928583 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches1.demandHits::total 154928583 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches1.overallHits::processor.cores1.core.inst 154928583 # number of overall hits (Count)
board.cache_hierarchy.l1icaches1.overallHits::total 154928583 # number of overall hits (Count)
board.cache_hierarchy.l1icaches1.demandMisses::processor.cores1.core.inst 57825 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches1.demandMisses::total 57825 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches1.overallMisses::processor.cores1.core.inst 57825 # number of overall misses (Count)
board.cache_hierarchy.l1icaches1.overallMisses::total 57825 # number of overall misses (Count)
board.cache_hierarchy.l1icaches1.demandMissLatency::processor.cores1.core.inst 2008526500 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches1.demandMissLatency::total 2008526500 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches1.overallMissLatency::processor.cores1.core.inst 2008526500 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches1.overallMissLatency::total 2008526500 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches1.demandAccesses::processor.cores1.core.inst 154986408 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches1.demandAccesses::total 154986408 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches1.overallAccesses::processor.cores1.core.inst 154986408 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches1.overallAccesses::total 154986408 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches1.demandMissRate::processor.cores1.core.inst 0.000373 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches1.demandMissRate::total 0.000373 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches1.overallMissRate::processor.cores1.core.inst 0.000373 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches1.overallMissRate::total 0.000373 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches1.demandAvgMissLatency::processor.cores1.core.inst 34734.569823 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches1.demandAvgMissLatency::total 34734.569823 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches1.overallAvgMissLatency::processor.cores1.core.inst 34734.569823 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches1.overallAvgMissLatency::total 34734.569823 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches1.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches1.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches1.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches1.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches1.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches1.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches1.demandMshrMisses::processor.cores1.core.inst 57825 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches1.demandMshrMisses::total 57825 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches1.overallMshrMisses::processor.cores1.core.inst 57825 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches1.overallMshrMisses::total 57825 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches1.demandMshrMissLatency::processor.cores1.core.inst 1979613500 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches1.demandMshrMissLatency::total 1979613500 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches1.overallMshrMissLatency::processor.cores1.core.inst 1979613500 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches1.overallMshrMissLatency::total 1979613500 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches1.demandMshrMissRate::processor.cores1.core.inst 0.000373 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches1.demandMshrMissRate::total 0.000373 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches1.overallMshrMissRate::processor.cores1.core.inst 0.000373 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches1.overallMshrMissRate::total 0.000373 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches1.demandAvgMshrMissLatency::processor.cores1.core.inst 34234.561176 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches1.demandAvgMshrMissLatency::total 34234.561176 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches1.overallAvgMshrMissLatency::processor.cores1.core.inst 34234.561176 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches1.overallAvgMshrMissLatency::total 34234.561176 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches1.replacements 57335 # number of replacements (Count)
board.cache_hierarchy.l1icaches1.ReadReq.hits::processor.cores1.core.inst 154928583 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches1.ReadReq.hits::total 154928583 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches1.ReadReq.misses::processor.cores1.core.inst 57825 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches1.ReadReq.misses::total 57825 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches1.ReadReq.missLatency::processor.cores1.core.inst 2008526500 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches1.ReadReq.missLatency::total 2008526500 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches1.ReadReq.accesses::processor.cores1.core.inst 154986408 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches1.ReadReq.accesses::total 154986408 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches1.ReadReq.missRate::processor.cores1.core.inst 0.000373 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches1.ReadReq.missRate::total 0.000373 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches1.ReadReq.avgMissLatency::processor.cores1.core.inst 34734.569823 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches1.ReadReq.avgMissLatency::total 34734.569823 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches1.ReadReq.mshrMisses::processor.cores1.core.inst 57825 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches1.ReadReq.mshrMisses::total 57825 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches1.ReadReq.mshrMissLatency::processor.cores1.core.inst 1979613500 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches1.ReadReq.mshrMissLatency::total 1979613500 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches1.ReadReq.mshrMissRate::processor.cores1.core.inst 0.000373 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches1.ReadReq.mshrMissRate::total 0.000373 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches1.ReadReq.avgMshrMissLatency::processor.cores1.core.inst 34234.561176 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches1.ReadReq.avgMshrMissLatency::total 34234.561176 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches1.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches1.prefetcher.demandMshrMisses 57825 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches1.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches1.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches1.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches1.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches1.tags.tagsInUse 510.674152 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches1.tags.totalRefs 140172768 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches1.tags.sampledRefs 57335 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches1.tags.avgRefs 2444.802791 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches1.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches1.tags.occupancies::processor.cores1.core.inst 510.674152 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches1.tags.avgOccs::processor.cores1.core.inst 0.997410 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches1.tags.avgOccs::total 0.997410 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches1.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches1.tags.ageTaskId_1024::3 454 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches1.tags.ageTaskId_1024::4 58 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches1.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches1.tags.tagAccesses 1239949090 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches1.tags.dataAccesses 1239949090 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches1.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches2.demandHits::processor.cores2.core.inst 153499164 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches2.demandHits::total 153499164 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches2.overallHits::processor.cores2.core.inst 153499164 # number of overall hits (Count)
board.cache_hierarchy.l1icaches2.overallHits::total 153499164 # number of overall hits (Count)
board.cache_hierarchy.l1icaches2.demandMisses::processor.cores2.core.inst 39928 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches2.demandMisses::total 39928 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches2.overallMisses::processor.cores2.core.inst 39928 # number of overall misses (Count)
board.cache_hierarchy.l1icaches2.overallMisses::total 39928 # number of overall misses (Count)
board.cache_hierarchy.l1icaches2.demandMissLatency::processor.cores2.core.inst 1064472000 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches2.demandMissLatency::total 1064472000 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches2.overallMissLatency::processor.cores2.core.inst 1064472000 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches2.overallMissLatency::total 1064472000 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches2.demandAccesses::processor.cores2.core.inst 153539092 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches2.demandAccesses::total 153539092 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches2.overallAccesses::processor.cores2.core.inst 153539092 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches2.overallAccesses::total 153539092 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches2.demandMissRate::processor.cores2.core.inst 0.000260 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches2.demandMissRate::total 0.000260 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches2.overallMissRate::processor.cores2.core.inst 0.000260 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches2.overallMissRate::total 0.000260 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches2.demandAvgMissLatency::processor.cores2.core.inst 26659.787618 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches2.demandAvgMissLatency::total 26659.787618 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches2.overallAvgMissLatency::processor.cores2.core.inst 26659.787618 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches2.overallAvgMissLatency::total 26659.787618 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches2.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches2.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches2.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches2.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches2.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches2.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches2.demandMshrMisses::processor.cores2.core.inst 39928 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches2.demandMshrMisses::total 39928 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches2.overallMshrMisses::processor.cores2.core.inst 39928 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches2.overallMshrMisses::total 39928 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches2.demandMshrMissLatency::processor.cores2.core.inst 1044508000 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches2.demandMshrMissLatency::total 1044508000 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches2.overallMshrMissLatency::processor.cores2.core.inst 1044508000 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches2.overallMshrMissLatency::total 1044508000 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches2.demandMshrMissRate::processor.cores2.core.inst 0.000260 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches2.demandMshrMissRate::total 0.000260 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches2.overallMshrMissRate::processor.cores2.core.inst 0.000260 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches2.overallMshrMissRate::total 0.000260 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches2.demandAvgMshrMissLatency::processor.cores2.core.inst 26159.787618 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches2.demandAvgMshrMissLatency::total 26159.787618 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches2.overallAvgMshrMissLatency::processor.cores2.core.inst 26159.787618 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches2.overallAvgMshrMissLatency::total 26159.787618 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches2.replacements 39437 # number of replacements (Count)
board.cache_hierarchy.l1icaches2.ReadReq.hits::processor.cores2.core.inst 153499164 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches2.ReadReq.hits::total 153499164 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches2.ReadReq.misses::processor.cores2.core.inst 39928 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches2.ReadReq.misses::total 39928 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches2.ReadReq.missLatency::processor.cores2.core.inst 1064472000 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches2.ReadReq.missLatency::total 1064472000 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches2.ReadReq.accesses::processor.cores2.core.inst 153539092 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches2.ReadReq.accesses::total 153539092 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches2.ReadReq.missRate::processor.cores2.core.inst 0.000260 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches2.ReadReq.missRate::total 0.000260 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches2.ReadReq.avgMissLatency::processor.cores2.core.inst 26659.787618 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches2.ReadReq.avgMissLatency::total 26659.787618 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches2.ReadReq.mshrMisses::processor.cores2.core.inst 39928 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches2.ReadReq.mshrMisses::total 39928 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches2.ReadReq.mshrMissLatency::processor.cores2.core.inst 1044508000 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches2.ReadReq.mshrMissLatency::total 1044508000 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches2.ReadReq.mshrMissRate::processor.cores2.core.inst 0.000260 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches2.ReadReq.mshrMissRate::total 0.000260 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches2.ReadReq.avgMshrMissLatency::processor.cores2.core.inst 26159.787618 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches2.ReadReq.avgMshrMissLatency::total 26159.787618 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches2.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches2.prefetcher.demandMshrMisses 39928 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches2.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches2.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches2.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches2.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches2.tags.tagsInUse 510.461018 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches2.tags.totalRefs 142392208 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches2.tags.sampledRefs 39437 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches2.tags.avgRefs 3610.624743 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches2.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches2.tags.occupancies::processor.cores2.core.inst 510.461018 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches2.tags.avgOccs::processor.cores2.core.inst 0.996994 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches2.tags.avgOccs::total 0.996994 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches2.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches2.tags.ageTaskId_1024::0 6 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches2.tags.ageTaskId_1024::1 1 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches2.tags.ageTaskId_1024::2 198 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches2.tags.ageTaskId_1024::3 254 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches2.tags.ageTaskId_1024::4 53 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches2.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches2.tags.tagAccesses 1228352664 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches2.tags.dataAccesses 1228352664 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches2.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches3.demandHits::processor.cores3.core.inst 153349994 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches3.demandHits::total 153349994 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches3.overallHits::processor.cores3.core.inst 153349994 # number of overall hits (Count)
board.cache_hierarchy.l1icaches3.overallHits::total 153349994 # number of overall hits (Count)
board.cache_hierarchy.l1icaches3.demandMisses::processor.cores3.core.inst 39891 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches3.demandMisses::total 39891 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches3.overallMisses::processor.cores3.core.inst 39891 # number of overall misses (Count)
board.cache_hierarchy.l1icaches3.overallMisses::total 39891 # number of overall misses (Count)
board.cache_hierarchy.l1icaches3.demandMissLatency::processor.cores3.core.inst 889679000 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches3.demandMissLatency::total 889679000 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches3.overallMissLatency::processor.cores3.core.inst 889679000 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches3.overallMissLatency::total 889679000 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches3.demandAccesses::processor.cores3.core.inst 153389885 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches3.demandAccesses::total 153389885 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches3.overallAccesses::processor.cores3.core.inst 153389885 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches3.overallAccesses::total 153389885 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches3.demandMissRate::processor.cores3.core.inst 0.000260 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches3.demandMissRate::total 0.000260 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches3.overallMissRate::processor.cores3.core.inst 0.000260 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches3.overallMissRate::total 0.000260 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches3.demandAvgMissLatency::processor.cores3.core.inst 22302.749994 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches3.demandAvgMissLatency::total 22302.749994 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches3.overallAvgMissLatency::processor.cores3.core.inst 22302.749994 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches3.overallAvgMissLatency::total 22302.749994 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches3.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches3.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches3.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches3.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches3.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches3.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches3.demandMshrMisses::processor.cores3.core.inst 39891 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches3.demandMshrMisses::total 39891 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches3.overallMshrMisses::processor.cores3.core.inst 39891 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches3.overallMshrMisses::total 39891 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches3.demandMshrMissLatency::processor.cores3.core.inst 869733500 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches3.demandMshrMissLatency::total 869733500 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches3.overallMshrMissLatency::processor.cores3.core.inst 869733500 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches3.overallMshrMissLatency::total 869733500 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches3.demandMshrMissRate::processor.cores3.core.inst 0.000260 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches3.demandMshrMissRate::total 0.000260 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches3.overallMshrMissRate::processor.cores3.core.inst 0.000260 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches3.overallMshrMissRate::total 0.000260 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches3.demandAvgMshrMissLatency::processor.cores3.core.inst 21802.749994 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches3.demandAvgMshrMissLatency::total 21802.749994 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches3.overallAvgMshrMissLatency::processor.cores3.core.inst 21802.749994 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches3.overallAvgMshrMissLatency::total 21802.749994 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches3.replacements 39401 # number of replacements (Count)
board.cache_hierarchy.l1icaches3.ReadReq.hits::processor.cores3.core.inst 153349994 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches3.ReadReq.hits::total 153349994 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches3.ReadReq.misses::processor.cores3.core.inst 39891 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches3.ReadReq.misses::total 39891 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches3.ReadReq.missLatency::processor.cores3.core.inst 889679000 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches3.ReadReq.missLatency::total 889679000 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches3.ReadReq.accesses::processor.cores3.core.inst 153389885 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches3.ReadReq.accesses::total 153389885 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches3.ReadReq.missRate::processor.cores3.core.inst 0.000260 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches3.ReadReq.missRate::total 0.000260 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches3.ReadReq.avgMissLatency::processor.cores3.core.inst 22302.749994 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches3.ReadReq.avgMissLatency::total 22302.749994 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches3.ReadReq.mshrMisses::processor.cores3.core.inst 39891 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches3.ReadReq.mshrMisses::total 39891 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches3.ReadReq.mshrMissLatency::processor.cores3.core.inst 869733500 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches3.ReadReq.mshrMissLatency::total 869733500 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches3.ReadReq.mshrMissRate::processor.cores3.core.inst 0.000260 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches3.ReadReq.mshrMissRate::total 0.000260 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches3.ReadReq.avgMshrMissLatency::processor.cores3.core.inst 21802.749994 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches3.ReadReq.avgMshrMissLatency::total 21802.749994 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches3.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches3.prefetcher.demandMshrMisses 39891 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches3.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches3.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches3.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches3.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches3.tags.tagsInUse 511.081431 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches3.tags.totalRefs 143099032 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches3.tags.sampledRefs 39401 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches3.tags.avgRefs 3631.862948 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches3.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches3.tags.occupancies::processor.cores3.core.inst 511.081431 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches3.tags.avgOccs::processor.cores3.core.inst 0.998206 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches3.tags.avgOccs::total 0.998206 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches3.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches3.tags.ageTaskId_1024::1 8 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches3.tags.ageTaskId_1024::2 433 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches3.tags.ageTaskId_1024::3 20 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches3.tags.ageTaskId_1024::4 51 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches3.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches3.tags.tagAccesses 1227158971 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches3.tags.dataAccesses 1227158971 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches3.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches4.demandHits::processor.cores4.core.inst 159314682 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches4.demandHits::total 159314682 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches4.overallHits::processor.cores4.core.inst 159314682 # number of overall hits (Count)
board.cache_hierarchy.l1icaches4.overallHits::total 159314682 # number of overall hits (Count)
board.cache_hierarchy.l1icaches4.demandMisses::processor.cores4.core.inst 39206 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches4.demandMisses::total 39206 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches4.overallMisses::processor.cores4.core.inst 39206 # number of overall misses (Count)
board.cache_hierarchy.l1icaches4.overallMisses::total 39206 # number of overall misses (Count)
board.cache_hierarchy.l1icaches4.demandMissLatency::processor.cores4.core.inst 1159996000 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches4.demandMissLatency::total 1159996000 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches4.overallMissLatency::processor.cores4.core.inst 1159996000 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches4.overallMissLatency::total 1159996000 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches4.demandAccesses::processor.cores4.core.inst 159353888 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches4.demandAccesses::total 159353888 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches4.overallAccesses::processor.cores4.core.inst 159353888 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches4.overallAccesses::total 159353888 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches4.demandMissRate::processor.cores4.core.inst 0.000246 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches4.demandMissRate::total 0.000246 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches4.overallMissRate::processor.cores4.core.inst 0.000246 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches4.overallMissRate::total 0.000246 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches4.demandAvgMissLatency::processor.cores4.core.inst 29587.206040 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches4.demandAvgMissLatency::total 29587.206040 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches4.overallAvgMissLatency::processor.cores4.core.inst 29587.206040 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches4.overallAvgMissLatency::total 29587.206040 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches4.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches4.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches4.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches4.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches4.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches4.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches4.demandMshrMisses::processor.cores4.core.inst 39206 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches4.demandMshrMisses::total 39206 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches4.overallMshrMisses::processor.cores4.core.inst 39206 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches4.overallMshrMisses::total 39206 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches4.demandMshrMissLatency::processor.cores4.core.inst 1140393000 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches4.demandMshrMissLatency::total 1140393000 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches4.overallMshrMissLatency::processor.cores4.core.inst 1140393000 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches4.overallMshrMissLatency::total 1140393000 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches4.demandMshrMissRate::processor.cores4.core.inst 0.000246 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches4.demandMshrMissRate::total 0.000246 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches4.overallMshrMissRate::processor.cores4.core.inst 0.000246 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches4.overallMshrMissRate::total 0.000246 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches4.demandAvgMshrMissLatency::processor.cores4.core.inst 29087.206040 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches4.demandAvgMshrMissLatency::total 29087.206040 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches4.overallAvgMshrMissLatency::processor.cores4.core.inst 29087.206040 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches4.overallAvgMshrMissLatency::total 29087.206040 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches4.replacements 38716 # number of replacements (Count)
board.cache_hierarchy.l1icaches4.ReadReq.hits::processor.cores4.core.inst 159314682 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches4.ReadReq.hits::total 159314682 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches4.ReadReq.misses::processor.cores4.core.inst 39206 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches4.ReadReq.misses::total 39206 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches4.ReadReq.missLatency::processor.cores4.core.inst 1159996000 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches4.ReadReq.missLatency::total 1159996000 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches4.ReadReq.accesses::processor.cores4.core.inst 159353888 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches4.ReadReq.accesses::total 159353888 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches4.ReadReq.missRate::processor.cores4.core.inst 0.000246 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches4.ReadReq.missRate::total 0.000246 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches4.ReadReq.avgMissLatency::processor.cores4.core.inst 29587.206040 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches4.ReadReq.avgMissLatency::total 29587.206040 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches4.ReadReq.mshrMisses::processor.cores4.core.inst 39206 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches4.ReadReq.mshrMisses::total 39206 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches4.ReadReq.mshrMissLatency::processor.cores4.core.inst 1140393000 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches4.ReadReq.mshrMissLatency::total 1140393000 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches4.ReadReq.mshrMissRate::processor.cores4.core.inst 0.000246 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches4.ReadReq.mshrMissRate::total 0.000246 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches4.ReadReq.avgMshrMissLatency::processor.cores4.core.inst 29087.206040 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches4.ReadReq.avgMshrMissLatency::total 29087.206040 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches4.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches4.prefetcher.demandMshrMisses 39206 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches4.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches4.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches4.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches4.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches4.tags.tagsInUse 509.260802 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches4.tags.totalRefs 144297783 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches4.tags.sampledRefs 38716 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches4.tags.avgRefs 3727.083970 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches4.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches4.tags.occupancies::processor.cores4.core.inst 509.260802 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches4.tags.avgOccs::processor.cores4.core.inst 0.994650 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches4.tags.avgOccs::total 0.994650 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches4.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches4.tags.ageTaskId_1024::3 453 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches4.tags.ageTaskId_1024::4 59 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches4.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches4.tags.tagAccesses 1274870310 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches4.tags.dataAccesses 1274870310 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches4.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches5.demandHits::processor.cores5.core.inst 159764804 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches5.demandHits::total 159764804 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches5.overallHits::processor.cores5.core.inst 159764804 # number of overall hits (Count)
board.cache_hierarchy.l1icaches5.overallHits::total 159764804 # number of overall hits (Count)
board.cache_hierarchy.l1icaches5.demandMisses::processor.cores5.core.inst 39275 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches5.demandMisses::total 39275 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches5.overallMisses::processor.cores5.core.inst 39275 # number of overall misses (Count)
board.cache_hierarchy.l1icaches5.overallMisses::total 39275 # number of overall misses (Count)
board.cache_hierarchy.l1icaches5.demandMissLatency::processor.cores5.core.inst 1126484500 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches5.demandMissLatency::total 1126484500 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches5.overallMissLatency::processor.cores5.core.inst 1126484500 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches5.overallMissLatency::total 1126484500 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches5.demandAccesses::processor.cores5.core.inst 159804079 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches5.demandAccesses::total 159804079 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches5.overallAccesses::processor.cores5.core.inst 159804079 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches5.overallAccesses::total 159804079 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches5.demandMissRate::processor.cores5.core.inst 0.000246 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches5.demandMissRate::total 0.000246 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches5.overallMissRate::processor.cores5.core.inst 0.000246 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches5.overallMissRate::total 0.000246 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches5.demandAvgMissLatency::processor.cores5.core.inst 28681.973265 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches5.demandAvgMissLatency::total 28681.973265 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches5.overallAvgMissLatency::processor.cores5.core.inst 28681.973265 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches5.overallAvgMissLatency::total 28681.973265 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches5.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches5.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches5.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches5.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches5.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches5.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches5.demandMshrMisses::processor.cores5.core.inst 39275 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches5.demandMshrMisses::total 39275 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches5.overallMshrMisses::processor.cores5.core.inst 39275 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches5.overallMshrMisses::total 39275 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches5.demandMshrMissLatency::processor.cores5.core.inst 1106846500 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches5.demandMshrMissLatency::total 1106846500 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches5.overallMshrMissLatency::processor.cores5.core.inst 1106846500 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches5.overallMshrMissLatency::total 1106846500 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches5.demandMshrMissRate::processor.cores5.core.inst 0.000246 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches5.demandMshrMissRate::total 0.000246 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches5.overallMshrMissRate::processor.cores5.core.inst 0.000246 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches5.overallMshrMissRate::total 0.000246 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches5.demandAvgMshrMissLatency::processor.cores5.core.inst 28181.960535 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches5.demandAvgMshrMissLatency::total 28181.960535 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches5.overallAvgMshrMissLatency::processor.cores5.core.inst 28181.960535 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches5.overallAvgMshrMissLatency::total 28181.960535 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches5.replacements 38785 # number of replacements (Count)
board.cache_hierarchy.l1icaches5.ReadReq.hits::processor.cores5.core.inst 159764804 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches5.ReadReq.hits::total 159764804 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches5.ReadReq.misses::processor.cores5.core.inst 39275 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches5.ReadReq.misses::total 39275 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches5.ReadReq.missLatency::processor.cores5.core.inst 1126484500 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches5.ReadReq.missLatency::total 1126484500 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches5.ReadReq.accesses::processor.cores5.core.inst 159804079 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches5.ReadReq.accesses::total 159804079 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches5.ReadReq.missRate::processor.cores5.core.inst 0.000246 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches5.ReadReq.missRate::total 0.000246 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches5.ReadReq.avgMissLatency::processor.cores5.core.inst 28681.973265 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches5.ReadReq.avgMissLatency::total 28681.973265 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches5.ReadReq.mshrMisses::processor.cores5.core.inst 39275 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches5.ReadReq.mshrMisses::total 39275 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches5.ReadReq.mshrMissLatency::processor.cores5.core.inst 1106846500 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches5.ReadReq.mshrMissLatency::total 1106846500 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches5.ReadReq.mshrMissRate::processor.cores5.core.inst 0.000246 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches5.ReadReq.mshrMissRate::total 0.000246 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches5.ReadReq.avgMshrMissLatency::processor.cores5.core.inst 28181.960535 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches5.ReadReq.avgMshrMissLatency::total 28181.960535 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches5.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches5.prefetcher.demandMshrMisses 39275 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches5.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches5.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches5.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches5.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches5.tags.tagsInUse 509.258084 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches5.tags.totalRefs 145582019 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches5.tags.sampledRefs 38785 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches5.tags.avgRefs 3753.565012 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches5.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches5.tags.occupancies::processor.cores5.core.inst 509.258084 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches5.tags.avgOccs::processor.cores5.core.inst 0.994645 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches5.tags.avgOccs::total 0.994645 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches5.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches5.tags.ageTaskId_1024::3 455 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches5.tags.ageTaskId_1024::4 57 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches5.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches5.tags.tagAccesses 1278471908 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches5.tags.dataAccesses 1278471908 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches5.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches6.demandHits::processor.cores6.core.inst 153087006 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches6.demandHits::total 153087006 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches6.overallHits::processor.cores6.core.inst 153087006 # number of overall hits (Count)
board.cache_hierarchy.l1icaches6.overallHits::total 153087006 # number of overall hits (Count)
board.cache_hierarchy.l1icaches6.demandMisses::processor.cores6.core.inst 39788 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches6.demandMisses::total 39788 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches6.overallMisses::processor.cores6.core.inst 39788 # number of overall misses (Count)
board.cache_hierarchy.l1icaches6.overallMisses::total 39788 # number of overall misses (Count)
board.cache_hierarchy.l1icaches6.demandMissLatency::processor.cores6.core.inst 953424000 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches6.demandMissLatency::total 953424000 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches6.overallMissLatency::processor.cores6.core.inst 953424000 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches6.overallMissLatency::total 953424000 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches6.demandAccesses::processor.cores6.core.inst 153126794 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches6.demandAccesses::total 153126794 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches6.overallAccesses::processor.cores6.core.inst 153126794 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches6.overallAccesses::total 153126794 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches6.demandMissRate::processor.cores6.core.inst 0.000260 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches6.demandMissRate::total 0.000260 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches6.overallMissRate::processor.cores6.core.inst 0.000260 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches6.overallMissRate::total 0.000260 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches6.demandAvgMissLatency::processor.cores6.core.inst 23962.601789 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches6.demandAvgMissLatency::total 23962.601789 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches6.overallAvgMissLatency::processor.cores6.core.inst 23962.601789 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches6.overallAvgMissLatency::total 23962.601789 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches6.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches6.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches6.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches6.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches6.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches6.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches6.demandMshrMisses::processor.cores6.core.inst 39788 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches6.demandMshrMisses::total 39788 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches6.overallMshrMisses::processor.cores6.core.inst 39788 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches6.overallMshrMisses::total 39788 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches6.demandMshrMissLatency::processor.cores6.core.inst 933529500 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches6.demandMshrMissLatency::total 933529500 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches6.overallMshrMissLatency::processor.cores6.core.inst 933529500 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches6.overallMshrMissLatency::total 933529500 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches6.demandMshrMissRate::processor.cores6.core.inst 0.000260 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches6.demandMshrMissRate::total 0.000260 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches6.overallMshrMissRate::processor.cores6.core.inst 0.000260 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches6.overallMshrMissRate::total 0.000260 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches6.demandAvgMshrMissLatency::processor.cores6.core.inst 23462.589223 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches6.demandAvgMshrMissLatency::total 23462.589223 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches6.overallAvgMshrMissLatency::processor.cores6.core.inst 23462.589223 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches6.overallAvgMshrMissLatency::total 23462.589223 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches6.replacements 39298 # number of replacements (Count)
board.cache_hierarchy.l1icaches6.ReadReq.hits::processor.cores6.core.inst 153087006 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches6.ReadReq.hits::total 153087006 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches6.ReadReq.misses::processor.cores6.core.inst 39788 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches6.ReadReq.misses::total 39788 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches6.ReadReq.missLatency::processor.cores6.core.inst 953424000 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches6.ReadReq.missLatency::total 953424000 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches6.ReadReq.accesses::processor.cores6.core.inst 153126794 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches6.ReadReq.accesses::total 153126794 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches6.ReadReq.missRate::processor.cores6.core.inst 0.000260 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches6.ReadReq.missRate::total 0.000260 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches6.ReadReq.avgMissLatency::processor.cores6.core.inst 23962.601789 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches6.ReadReq.avgMissLatency::total 23962.601789 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches6.ReadReq.mshrMisses::processor.cores6.core.inst 39788 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches6.ReadReq.mshrMisses::total 39788 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches6.ReadReq.mshrMissLatency::processor.cores6.core.inst 933529500 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches6.ReadReq.mshrMissLatency::total 933529500 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches6.ReadReq.mshrMissRate::processor.cores6.core.inst 0.000260 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches6.ReadReq.mshrMissRate::total 0.000260 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches6.ReadReq.avgMshrMissLatency::processor.cores6.core.inst 23462.589223 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches6.ReadReq.avgMshrMissLatency::total 23462.589223 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches6.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches6.prefetcher.demandMshrMisses 39788 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches6.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches6.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches6.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches6.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches6.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches6.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches6.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches6.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches6.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches6.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches6.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches6.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches6.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches6.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches6.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches6.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches6.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches6.tags.tagsInUse 509.117501 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches6.tags.totalRefs 141909248 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches6.tags.sampledRefs 39298 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches6.tags.avgRefs 3611.106112 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches6.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches6.tags.occupancies::processor.cores6.core.inst 509.117501 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches6.tags.avgOccs::processor.cores6.core.inst 0.994370 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches6.tags.avgOccs::total 0.994370 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches6.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches6.tags.ageTaskId_1024::2 178 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches6.tags.ageTaskId_1024::3 283 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches6.tags.ageTaskId_1024::4 51 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches6.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches6.tags.tagAccesses 1225054141 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches6.tags.dataAccesses 1225054141 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches6.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches7.demandHits::processor.cores7.core.inst 158748925 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches7.demandHits::total 158748925 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches7.overallHits::processor.cores7.core.inst 158748925 # number of overall hits (Count)
board.cache_hierarchy.l1icaches7.overallHits::total 158748925 # number of overall hits (Count)
board.cache_hierarchy.l1icaches7.demandMisses::processor.cores7.core.inst 40911 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches7.demandMisses::total 40911 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches7.overallMisses::processor.cores7.core.inst 40911 # number of overall misses (Count)
board.cache_hierarchy.l1icaches7.overallMisses::total 40911 # number of overall misses (Count)
board.cache_hierarchy.l1icaches7.demandMissLatency::processor.cores7.core.inst 1419153500 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches7.demandMissLatency::total 1419153500 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches7.overallMissLatency::processor.cores7.core.inst 1419153500 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches7.overallMissLatency::total 1419153500 # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches7.demandAccesses::processor.cores7.core.inst 158789836 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches7.demandAccesses::total 158789836 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches7.overallAccesses::processor.cores7.core.inst 158789836 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches7.overallAccesses::total 158789836 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches7.demandMissRate::processor.cores7.core.inst 0.000258 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches7.demandMissRate::total 0.000258 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches7.overallMissRate::processor.cores7.core.inst 0.000258 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches7.overallMissRate::total 0.000258 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches7.demandAvgMissLatency::processor.cores7.core.inst 34688.800078 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches7.demandAvgMissLatency::total 34688.800078 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches7.overallAvgMissLatency::processor.cores7.core.inst 34688.800078 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches7.overallAvgMissLatency::total 34688.800078 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches7.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches7.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches7.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches7.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches7.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches7.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches7.demandMshrMisses::processor.cores7.core.inst 40911 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches7.demandMshrMisses::total 40911 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches7.overallMshrMisses::processor.cores7.core.inst 40911 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches7.overallMshrMisses::total 40911 # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches7.demandMshrMissLatency::processor.cores7.core.inst 1398697500 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches7.demandMshrMissLatency::total 1398697500 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches7.overallMshrMissLatency::processor.cores7.core.inst 1398697500 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches7.overallMshrMissLatency::total 1398697500 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches7.demandMshrMissRate::processor.cores7.core.inst 0.000258 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches7.demandMshrMissRate::total 0.000258 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches7.overallMshrMissRate::processor.cores7.core.inst 0.000258 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches7.overallMshrMissRate::total 0.000258 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches7.demandAvgMshrMissLatency::processor.cores7.core.inst 34188.787857 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches7.demandAvgMshrMissLatency::total 34188.787857 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches7.overallAvgMshrMissLatency::processor.cores7.core.inst 34188.787857 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches7.overallAvgMshrMissLatency::total 34188.787857 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches7.replacements 40422 # number of replacements (Count)
board.cache_hierarchy.l1icaches7.ReadReq.hits::processor.cores7.core.inst 158748925 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches7.ReadReq.hits::total 158748925 # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches7.ReadReq.misses::processor.cores7.core.inst 40911 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches7.ReadReq.misses::total 40911 # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches7.ReadReq.missLatency::processor.cores7.core.inst 1419153500 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches7.ReadReq.missLatency::total 1419153500 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches7.ReadReq.accesses::processor.cores7.core.inst 158789836 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches7.ReadReq.accesses::total 158789836 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches7.ReadReq.missRate::processor.cores7.core.inst 0.000258 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches7.ReadReq.missRate::total 0.000258 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches7.ReadReq.avgMissLatency::processor.cores7.core.inst 34688.800078 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches7.ReadReq.avgMissLatency::total 34688.800078 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches7.ReadReq.mshrMisses::processor.cores7.core.inst 40911 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches7.ReadReq.mshrMisses::total 40911 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches7.ReadReq.mshrMissLatency::processor.cores7.core.inst 1398697500 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches7.ReadReq.mshrMissLatency::total 1398697500 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches7.ReadReq.mshrMissRate::processor.cores7.core.inst 0.000258 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches7.ReadReq.mshrMissRate::total 0.000258 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches7.ReadReq.avgMshrMissLatency::processor.cores7.core.inst 34188.787857 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches7.ReadReq.avgMshrMissLatency::total 34188.787857 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches7.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches7.prefetcher.demandMshrMisses 40911 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches7.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches7.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches7.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches7.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches7.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches7.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches7.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches7.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches7.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches7.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches7.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches7.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches7.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches7.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches7.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches7.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches7.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches7.tags.tagsInUse 509.566907 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches7.tags.totalRefs 144159817 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches7.tags.sampledRefs 40422 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches7.tags.avgRefs 3566.370219 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches7.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches7.tags.occupancies::processor.cores7.core.inst 509.566907 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches7.tags.avgOccs::processor.cores7.core.inst 0.995248 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches7.tags.avgOccs::total 0.995248 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches7.tags.occupanciesTaskId::1024 512 # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches7.tags.ageTaskId_1024::3 460 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches7.tags.ageTaskId_1024::4 52 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches7.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches7.tags.tagAccesses 1270359600 # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches7.tags.dataAccesses 1270359600 # Number of data accesses (Count)
board.cache_hierarchy.l1icaches7.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2bus.transDist::ReadResp 18789196 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::ReadRespWithInvalidate 481 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::WritebackDirty 12663099 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::CleanEvict 18398288 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::HardPFReq 1729695 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::UpgradeReq 390940 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::UpgradeResp 390940 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::ReadExReq 1561348 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::ReadExResp 1561348 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.transDist::ReadSharedReq 18789671 # Transaction distribution (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1icaches0.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 123606 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1dcaches0.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 6654535 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1icaches1.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 172986 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1dcaches1.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 7472299 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1icaches2.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 119293 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1dcaches2.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 7909171 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1icaches3.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 119183 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1dcaches3.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 7963693 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1icaches4.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 117128 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1dcaches4.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 7023112 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1icaches5.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 117336 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1dcaches5.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 7029332 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1icaches6.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 118875 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1dcaches6.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 7882321 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1icaches7.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 122245 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount_board.cache_hierarchy.l1dcaches7.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 7033640 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktCount::total 59978755 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1icaches0.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 2646720 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1dcaches0.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 201894784 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1icaches1.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 3700864 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1dcaches1.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 227949248 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1icaches2.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 2555392 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1dcaches2.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 234967168 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1icaches3.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 2553024 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1dcaches3.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 236295744 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1icaches4.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 2509184 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1dcaches4.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 205468096 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1icaches5.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 2513664 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1dcaches5.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 205860160 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1icaches6.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 2546496 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1dcaches6.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 232615488 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1icaches7.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 2618368 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize_board.cache_hierarchy.l1dcaches7.mem_side_port::board.cache_hierarchy.l2cache.cpu_side_port 205324928 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.pktSize::total 1772019328 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l2bus.snoops 14296251 # Total snoops (Count)
board.cache_hierarchy.l2bus.snoopTraffic 340884608 # Total snoop traffic (Byte)
board.cache_hierarchy.l2bus.snoopFanout::samples 34899669 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::mean 0.113567 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::stdev 0.636779 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::0 33054056 94.71% 94.71% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::1 1053474 3.02% 97.73% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::2 321291 0.92% 98.65% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::3 156720 0.45% 99.10% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::4 78306 0.22% 99.32% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::5 68391 0.20% 99.52% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::6 64438 0.18% 99.70% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::7 69572 0.20% 99.90% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::8 33133 0.09% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::9 53 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::10 48 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::11 42 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::12 38 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::13 42 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::14 35 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::15 28 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::16 2 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::17 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::18 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::19 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::20 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::21 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::22 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::23 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::24 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::25 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::26 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::27 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::28 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::29 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::30 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::31 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::32 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::max_value 16 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.snoopFanout::total 34899669 # Request fanout histogram (Count)
board.cache_hierarchy.l2bus.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2bus.reqLayer0.occupancy 32105292732 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.reqLayer0.utilization 0.2 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer0.occupancy 66165012 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer1.occupancy 3430581444 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer12.occupancy 64087987 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer12.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer13.occupancy 4131921676 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer13.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer16.occupancy 64111638 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer16.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer17.occupancy 3685267125 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer17.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer20.occupancy 64284364 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer20.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer21.occupancy 3691498250 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer21.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer24.occupancy 63903104 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer24.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer25.occupancy 4104799104 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer25.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer28.occupancy 66913505 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer28.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer29.occupancy 3695445466 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer29.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer4.occupancy 89998415 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer4.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer5.occupancy 3820684811 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer5.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer8.occupancy 64455709 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer8.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.respLayer9.occupancy 4090922637 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l2bus.respLayer9.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l2bus.snoop_filter.totRequests 42263874 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l2bus.snoop_filter.hitSingleRequests 20666617 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2bus.snoop_filter.hitMultiRequests 1639567 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2bus.snoop_filter.totSnoops 117598 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l2bus.snoop_filter.hitSingleSnoops 68810 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l2bus.snoop_filter.hitMultiSnoops 48788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l2cache.demandHits::cache_hierarchy.l1dcaches0.prefetcher 731223 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::cache_hierarchy.l1dcaches1.prefetcher 863664 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::cache_hierarchy.l1dcaches2.prefetcher 936443 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::cache_hierarchy.l1dcaches3.prefetcher 936440 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::cache_hierarchy.l1dcaches4.prefetcher 777414 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::cache_hierarchy.l1dcaches5.prefetcher 792505 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::cache_hierarchy.l1dcaches6.prefetcher 902259 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::cache_hierarchy.l1dcaches7.prefetcher 775016 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores0.core.inst 20901 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores0.core.data 266242 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores1.core.inst 29511 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores1.core.data 282036 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores2.core.inst 26338 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores2.core.data 296670 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores3.core.inst 29042 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores3.core.data 297538 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores4.core.inst 23815 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores4.core.data 254011 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores5.core.inst 24587 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores5.core.data 267168 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores6.core.inst 27902 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores6.core.data 300065 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores7.core.inst 21995 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::processor.cores7.core.data 257382 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.demandHits::total 9140167 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l2cache.overallHits::cache_hierarchy.l1dcaches0.prefetcher 731223 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::cache_hierarchy.l1dcaches1.prefetcher 863664 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::cache_hierarchy.l1dcaches2.prefetcher 936443 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::cache_hierarchy.l1dcaches3.prefetcher 936440 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::cache_hierarchy.l1dcaches4.prefetcher 777414 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::cache_hierarchy.l1dcaches5.prefetcher 792505 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::cache_hierarchy.l1dcaches6.prefetcher 902259 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::cache_hierarchy.l1dcaches7.prefetcher 775016 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores0.core.inst 20901 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores0.core.data 266242 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores1.core.inst 29511 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores1.core.data 282036 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores2.core.inst 26338 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores2.core.data 296670 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores3.core.inst 29042 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores3.core.data 297538 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores4.core.inst 23815 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores4.core.data 254011 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores5.core.inst 24587 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores5.core.data 267168 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores6.core.inst 27902 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores6.core.data 300065 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores7.core.inst 21995 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::processor.cores7.core.data 257382 # number of overall hits (Count)
board.cache_hierarchy.l2cache.overallHits::total 9140167 # number of overall hits (Count)
board.cache_hierarchy.l2cache.demandMisses::cache_hierarchy.l1dcaches0.prefetcher 844633 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::cache_hierarchy.l1dcaches1.prefetcher 977603 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::cache_hierarchy.l1dcaches2.prefetcher 991911 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::cache_hierarchy.l1dcaches3.prefetcher 1004759 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::cache_hierarchy.l1dcaches4.prefetcher 932219 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::cache_hierarchy.l1dcaches5.prefetcher 917089 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::cache_hierarchy.l1dcaches6.prefetcher 1008700 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::cache_hierarchy.l1dcaches7.prefetcher 932278 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores0.core.inst 20453 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores0.core.data 347622 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores1.core.inst 28314 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores1.core.data 343801 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores2.core.inst 13590 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores2.core.data 358816 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores3.core.inst 10849 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores3.core.data 363068 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores4.core.inst 15391 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores4.core.data 316844 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores5.core.inst 14688 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores5.core.data 312311 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores6.core.inst 11886 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores6.core.data 361284 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores7.core.inst 18916 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::processor.cores7.core.data 318427 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.demandMisses::total 10465452 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l2cache.overallMisses::cache_hierarchy.l1dcaches0.prefetcher 844633 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::cache_hierarchy.l1dcaches1.prefetcher 977603 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::cache_hierarchy.l1dcaches2.prefetcher 991911 # number of overall misses (Count)
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board.cache_hierarchy.l2cache.overallMisses::cache_hierarchy.l1dcaches4.prefetcher 932219 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::cache_hierarchy.l1dcaches5.prefetcher 917089 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::cache_hierarchy.l1dcaches6.prefetcher 1008700 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::cache_hierarchy.l1dcaches7.prefetcher 932278 # number of overall misses (Count)
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board.cache_hierarchy.l2cache.overallMisses::processor.cores0.core.data 347622 # number of overall misses (Count)
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board.cache_hierarchy.l2cache.overallMisses::processor.cores1.core.data 343801 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::processor.cores2.core.inst 13590 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::processor.cores2.core.data 358816 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::processor.cores3.core.inst 10849 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::processor.cores3.core.data 363068 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::processor.cores4.core.inst 15391 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::processor.cores4.core.data 316844 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::processor.cores5.core.inst 14688 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::processor.cores5.core.data 312311 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::processor.cores6.core.inst 11886 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::processor.cores6.core.data 361284 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::processor.cores7.core.inst 18916 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::processor.cores7.core.data 318427 # number of overall misses (Count)
board.cache_hierarchy.l2cache.overallMisses::total 10465452 # number of overall misses (Count)
board.cache_hierarchy.l2cache.demandMissLatency::cache_hierarchy.l1dcaches0.prefetcher 70800214564 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::cache_hierarchy.l1dcaches1.prefetcher 81384830135 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::cache_hierarchy.l1dcaches2.prefetcher 82449604215 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::cache_hierarchy.l1dcaches3.prefetcher 83148351753 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::cache_hierarchy.l1dcaches4.prefetcher 78801140991 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::cache_hierarchy.l1dcaches5.prefetcher 76932856829 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::cache_hierarchy.l1dcaches6.prefetcher 83583494840 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::cache_hierarchy.l1dcaches7.prefetcher 78572539591 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores0.core.inst 1282775794 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores0.core.data 25870480046 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores1.core.inst 1687007841 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores1.core.data 25652834102 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores2.core.inst 793521429 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores2.core.data 27030310647 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores3.core.inst 602870468 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores3.core.data 27162394458 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores4.core.inst 903767308 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores4.core.data 23898410659 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores5.core.inst 863445769 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores5.core.data 23544175858 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores6.core.inst 669886952 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores6.core.data 27165696762 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores7.core.inst 1165763667 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::processor.cores7.core.data 23889265771 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMissLatency::total 847855640449 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::cache_hierarchy.l1dcaches0.prefetcher 70800214564 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::cache_hierarchy.l1dcaches1.prefetcher 81384830135 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::cache_hierarchy.l1dcaches2.prefetcher 82449604215 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::cache_hierarchy.l1dcaches3.prefetcher 83148351753 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::cache_hierarchy.l1dcaches4.prefetcher 78801140991 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::cache_hierarchy.l1dcaches5.prefetcher 76932856829 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::cache_hierarchy.l1dcaches6.prefetcher 83583494840 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::cache_hierarchy.l1dcaches7.prefetcher 78572539591 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores0.core.inst 1282775794 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores0.core.data 25870480046 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores1.core.inst 1687007841 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores1.core.data 25652834102 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores2.core.inst 793521429 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores2.core.data 27030310647 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores3.core.inst 602870468 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores3.core.data 27162394458 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores4.core.inst 903767308 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores4.core.data 23898410659 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores5.core.inst 863445769 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores5.core.data 23544175858 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores6.core.inst 669886952 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores6.core.data 27165696762 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores7.core.inst 1165763667 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::processor.cores7.core.data 23889265771 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMissLatency::total 847855640449 # number of overall miss ticks (Tick)
board.cache_hierarchy.l2cache.demandAccesses::cache_hierarchy.l1dcaches0.prefetcher 1575856 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::cache_hierarchy.l1dcaches1.prefetcher 1841267 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::cache_hierarchy.l1dcaches2.prefetcher 1928354 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::cache_hierarchy.l1dcaches3.prefetcher 1941199 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::cache_hierarchy.l1dcaches4.prefetcher 1709633 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::cache_hierarchy.l1dcaches5.prefetcher 1709594 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::cache_hierarchy.l1dcaches6.prefetcher 1910959 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::cache_hierarchy.l1dcaches7.prefetcher 1707294 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores0.core.inst 41354 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores0.core.data 613864 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores1.core.inst 57825 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores1.core.data 625837 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores2.core.inst 39928 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores2.core.data 655486 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores3.core.inst 39891 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores3.core.data 660606 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores4.core.inst 39206 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores4.core.data 570855 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores5.core.inst 39275 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores5.core.data 579479 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores6.core.inst 39788 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores6.core.data 661349 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores7.core.inst 40911 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::processor.cores7.core.data 575809 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandAccesses::total 19605619 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::cache_hierarchy.l1dcaches0.prefetcher 1575856 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::cache_hierarchy.l1dcaches1.prefetcher 1841267 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::cache_hierarchy.l1dcaches2.prefetcher 1928354 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::cache_hierarchy.l1dcaches3.prefetcher 1941199 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::cache_hierarchy.l1dcaches4.prefetcher 1709633 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::cache_hierarchy.l1dcaches5.prefetcher 1709594 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::cache_hierarchy.l1dcaches6.prefetcher 1910959 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::cache_hierarchy.l1dcaches7.prefetcher 1707294 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores0.core.inst 41354 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores0.core.data 613864 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores1.core.inst 57825 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores1.core.data 625837 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores2.core.inst 39928 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores2.core.data 655486 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores3.core.inst 39891 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores3.core.data 660606 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores4.core.inst 39206 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores4.core.data 570855 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores5.core.inst 39275 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores5.core.data 579479 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores6.core.inst 39788 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores6.core.data 661349 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores7.core.inst 40911 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::processor.cores7.core.data 575809 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.overallAccesses::total 19605619 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l2cache.demandMissRate::cache_hierarchy.l1dcaches0.prefetcher 0.535984 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::cache_hierarchy.l1dcaches1.prefetcher 0.530940 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::cache_hierarchy.l1dcaches2.prefetcher 0.514382 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::cache_hierarchy.l1dcaches3.prefetcher 0.517597 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::cache_hierarchy.l1dcaches4.prefetcher 0.545274 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::cache_hierarchy.l1dcaches5.prefetcher 0.536437 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::cache_hierarchy.l1dcaches6.prefetcher 0.527850 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::cache_hierarchy.l1dcaches7.prefetcher 0.546056 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores0.core.inst 0.494583 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores0.core.data 0.566285 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores1.core.inst 0.489650 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores1.core.data 0.549346 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores2.core.inst 0.340363 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores2.core.data 0.547405 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores3.core.inst 0.271966 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores3.core.data 0.549598 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores4.core.inst 0.392567 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores4.core.data 0.555034 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores5.core.inst 0.373978 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores5.core.data 0.538951 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores6.core.inst 0.298733 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores6.core.data 0.546283 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores7.core.inst 0.462370 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::processor.cores7.core.data 0.553008 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMissRate::total 0.533799 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::cache_hierarchy.l1dcaches0.prefetcher 0.535984 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::cache_hierarchy.l1dcaches1.prefetcher 0.530940 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::cache_hierarchy.l1dcaches2.prefetcher 0.514382 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::cache_hierarchy.l1dcaches3.prefetcher 0.517597 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::cache_hierarchy.l1dcaches4.prefetcher 0.545274 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::cache_hierarchy.l1dcaches5.prefetcher 0.536437 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::cache_hierarchy.l1dcaches6.prefetcher 0.527850 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::cache_hierarchy.l1dcaches7.prefetcher 0.546056 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores0.core.inst 0.494583 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores0.core.data 0.566285 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores1.core.inst 0.489650 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores1.core.data 0.549346 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores2.core.inst 0.340363 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores2.core.data 0.547405 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores3.core.inst 0.271966 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores3.core.data 0.549598 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores4.core.inst 0.392567 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores4.core.data 0.555034 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores5.core.inst 0.373978 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores5.core.data 0.538951 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores6.core.inst 0.298733 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores6.core.data 0.546283 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores7.core.inst 0.462370 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::processor.cores7.core.data 0.553008 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMissRate::total 0.533799 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l2cache.demandAvgMissLatency::cache_hierarchy.l1dcaches0.prefetcher 83823.642415 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::cache_hierarchy.l1dcaches1.prefetcher 83249.366190 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::cache_hierarchy.l1dcaches2.prefetcher 83121.977894 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::cache_hierarchy.l1dcaches3.prefetcher 82754.522978 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::cache_hierarchy.l1dcaches4.prefetcher 84530.717558 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::cache_hierarchy.l1dcaches5.prefetcher 83888.103367 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::cache_hierarchy.l1dcaches6.prefetcher 82862.590304 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::cache_hierarchy.l1dcaches7.prefetcher 84280.160629 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores0.core.inst 62718.221972 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores0.core.data 74421.296828 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores1.core.inst 59582.109239 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores1.core.data 74615.356273 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores2.core.inst 58390.097792 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores2.core.data 75331.954670 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores3.core.inst 55569.220020 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores3.core.data 74813.518289 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores4.core.inst 58720.506010 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores4.core.data 75426.426440 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores5.core.inst 58785.795820 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores5.core.data 75386.956777 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores6.core.inst 56359.326266 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores6.core.data 75192.083685 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores7.core.inst 61628.445073 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::processor.cores7.core.data 75022.739187 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMissLatency::total 81014.717802 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::cache_hierarchy.l1dcaches0.prefetcher 83823.642415 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::cache_hierarchy.l1dcaches1.prefetcher 83249.366190 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::cache_hierarchy.l1dcaches2.prefetcher 83121.977894 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::cache_hierarchy.l1dcaches3.prefetcher 82754.522978 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::cache_hierarchy.l1dcaches4.prefetcher 84530.717558 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::cache_hierarchy.l1dcaches5.prefetcher 83888.103367 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::cache_hierarchy.l1dcaches6.prefetcher 82862.590304 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::cache_hierarchy.l1dcaches7.prefetcher 84280.160629 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores0.core.inst 62718.221972 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores0.core.data 74421.296828 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores1.core.inst 59582.109239 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores1.core.data 74615.356273 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores2.core.inst 58390.097792 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores2.core.data 75331.954670 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores3.core.inst 55569.220020 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores3.core.data 74813.518289 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores4.core.inst 58720.506010 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores4.core.data 75426.426440 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores5.core.inst 58785.795820 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores5.core.data 75386.956777 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores6.core.inst 56359.326266 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores6.core.data 75192.083685 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores7.core.inst 61628.445073 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::processor.cores7.core.data 75022.739187 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMissLatency::total 81014.717802 # average overall miss latency ((Tick/Count))
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board.cache_hierarchy.l2cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l2cache.blockedCauses::no_mshrs 2084272 # number of times access was blocked (Count)
board.cache_hierarchy.l2cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l2cache.avgBlocked::no_mshrs 10.171417 # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l2cache.writebacks::writebacks 4580922 # number of writebacks (Count)
board.cache_hierarchy.l2cache.writebacks::total 4580922 # number of writebacks (Count)
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board.cache_hierarchy.l2cache.demandMshrHits::cache_hierarchy.l1dcaches2.prefetcher 20665 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::cache_hierarchy.l1dcaches3.prefetcher 22104 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::cache_hierarchy.l1dcaches4.prefetcher 17522 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::cache_hierarchy.l1dcaches5.prefetcher 21081 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::cache_hierarchy.l1dcaches6.prefetcher 20454 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::cache_hierarchy.l1dcaches7.prefetcher 18798 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::processor.cores0.core.inst 6927 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::processor.cores0.core.data 2362 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::processor.cores1.core.inst 5203 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::processor.cores1.core.data 1817 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::processor.cores2.core.inst 8194 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::processor.cores2.core.data 2906 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::processor.cores3.core.inst 7747 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::processor.cores3.core.data 3766 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::processor.cores4.core.inst 9753 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::processor.cores4.core.data 4334 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::processor.cores5.core.inst 9896 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::processor.cores5.core.data 5433 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::processor.cores6.core.inst 7606 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::processor.cores6.core.data 3047 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::processor.cores7.core.inst 10083 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::processor.cores7.core.data 4771 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrHits::total 258722 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::cache_hierarchy.l1dcaches0.prefetcher 21520 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::cache_hierarchy.l1dcaches1.prefetcher 22733 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::cache_hierarchy.l1dcaches2.prefetcher 20665 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::cache_hierarchy.l1dcaches3.prefetcher 22104 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::cache_hierarchy.l1dcaches4.prefetcher 17522 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::cache_hierarchy.l1dcaches5.prefetcher 21081 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::cache_hierarchy.l1dcaches6.prefetcher 20454 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::cache_hierarchy.l1dcaches7.prefetcher 18798 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::processor.cores0.core.inst 6927 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::processor.cores0.core.data 2362 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::processor.cores1.core.inst 5203 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::processor.cores1.core.data 1817 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::processor.cores2.core.inst 8194 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::processor.cores2.core.data 2906 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::processor.cores3.core.inst 7747 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::processor.cores3.core.data 3766 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::processor.cores4.core.inst 9753 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::processor.cores4.core.data 4334 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::processor.cores5.core.inst 9896 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::processor.cores5.core.data 5433 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::processor.cores6.core.inst 7606 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::processor.cores6.core.data 3047 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::processor.cores7.core.inst 10083 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::processor.cores7.core.data 4771 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.overallMshrHits::total 258722 # number of overall MSHR hits (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::cache_hierarchy.l1dcaches0.prefetcher 823113 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::cache_hierarchy.l1dcaches1.prefetcher 954870 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::cache_hierarchy.l1dcaches2.prefetcher 971246 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::cache_hierarchy.l1dcaches3.prefetcher 982655 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::cache_hierarchy.l1dcaches4.prefetcher 914697 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::cache_hierarchy.l1dcaches5.prefetcher 896008 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::cache_hierarchy.l1dcaches6.prefetcher 988246 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::cache_hierarchy.l1dcaches7.prefetcher 913480 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores0.core.inst 13526 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores0.core.data 345260 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores1.core.inst 23111 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores1.core.data 341984 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores2.core.inst 5396 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores2.core.data 355910 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores3.core.inst 3102 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores3.core.data 359302 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores4.core.inst 5638 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores4.core.data 312510 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores5.core.inst 4792 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores5.core.data 306878 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores6.core.inst 4280 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores6.core.data 358237 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores7.core.inst 8833 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::processor.cores7.core.data 313656 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMisses::total 10206730 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::cache_hierarchy.l1dcaches0.prefetcher 823113 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::cache_hierarchy.l1dcaches1.prefetcher 954870 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::cache_hierarchy.l1dcaches2.prefetcher 971246 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::cache_hierarchy.l1dcaches3.prefetcher 982655 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::cache_hierarchy.l1dcaches4.prefetcher 914697 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::cache_hierarchy.l1dcaches5.prefetcher 896008 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::cache_hierarchy.l1dcaches6.prefetcher 988246 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::cache_hierarchy.l1dcaches7.prefetcher 913480 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::cache_hierarchy.l2cache.prefetcher 1276690 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores0.core.inst 13526 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores0.core.data 345260 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores1.core.inst 23111 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores1.core.data 341984 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores2.core.inst 5396 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores2.core.data 355910 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores3.core.inst 3102 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores3.core.data 359302 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores4.core.inst 5638 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores4.core.data 312510 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores5.core.inst 4792 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores5.core.data 306878 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores6.core.inst 4280 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores6.core.data 358237 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores7.core.inst 8833 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::processor.cores7.core.data 313656 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.overallMshrMisses::total 11483420 # number of overall MSHR misses (Count)
board.cache_hierarchy.l2cache.demandMshrMissLatency::cache_hierarchy.l1dcaches0.prefetcher 69062139051 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::cache_hierarchy.l1dcaches1.prefetcher 79540742653 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::cache_hierarchy.l1dcaches2.prefetcher 80741349892 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::cache_hierarchy.l1dcaches3.prefetcher 81311951015 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::cache_hierarchy.l1dcaches4.prefetcher 77267081213 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::cache_hierarchy.l1dcaches5.prefetcher 75163020916 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::cache_hierarchy.l1dcaches6.prefetcher 81875617074 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::cache_hierarchy.l1dcaches7.prefetcher 76951677856 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores0.core.inst 926758806 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores0.core.data 25562622570 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores1.core.inst 1411704857 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores1.core.data 25381212124 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores2.core.inst 366613449 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores2.core.data 26681926161 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores3.core.inst 200954980 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores3.core.data 26752258473 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores4.core.inst 377321384 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores4.core.data 23470933704 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores5.core.inst 334002341 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores5.core.data 23046988421 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores6.core.inst 276353464 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores6.core.data 26800775277 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores7.core.inst 616046264 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::processor.cores7.core.data 23428077847 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissLatency::total 827548129792 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::cache_hierarchy.l1dcaches0.prefetcher 69062139051 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::cache_hierarchy.l1dcaches1.prefetcher 79540742653 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::cache_hierarchy.l1dcaches2.prefetcher 80741349892 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::cache_hierarchy.l1dcaches3.prefetcher 81311951015 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::cache_hierarchy.l1dcaches4.prefetcher 77267081213 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::cache_hierarchy.l1dcaches5.prefetcher 75163020916 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::cache_hierarchy.l1dcaches6.prefetcher 81875617074 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::cache_hierarchy.l1dcaches7.prefetcher 76951677856 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::cache_hierarchy.l2cache.prefetcher 92863301872 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores0.core.inst 926758806 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores0.core.data 25562622570 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores1.core.inst 1411704857 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores1.core.data 25381212124 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores2.core.inst 366613449 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores2.core.data 26681926161 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores3.core.inst 200954980 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores3.core.data 26752258473 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores4.core.inst 377321384 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores4.core.data 23470933704 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores5.core.inst 334002341 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores5.core.data 23046988421 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores6.core.inst 276353464 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores6.core.data 26800775277 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores7.core.inst 616046264 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::processor.cores7.core.data 23428077847 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.overallMshrMissLatency::total 920411431664 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.demandMshrMissRate::cache_hierarchy.l1dcaches0.prefetcher 0.522328 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::cache_hierarchy.l1dcaches1.prefetcher 0.518594 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::cache_hierarchy.l1dcaches2.prefetcher 0.503666 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::cache_hierarchy.l1dcaches3.prefetcher 0.506210 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::cache_hierarchy.l1dcaches4.prefetcher 0.535025 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::cache_hierarchy.l1dcaches5.prefetcher 0.524106 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::cache_hierarchy.l1dcaches6.prefetcher 0.517147 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::cache_hierarchy.l1dcaches7.prefetcher 0.535046 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores0.core.inst 0.327078 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores0.core.data 0.562437 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores1.core.inst 0.399671 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores1.core.data 0.546443 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores2.core.inst 0.135143 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores2.core.data 0.542971 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores3.core.inst 0.077762 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores3.core.data 0.543898 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores4.core.inst 0.143805 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores4.core.data 0.547442 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores5.core.inst 0.122011 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores5.core.data 0.529576 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores6.core.inst 0.107570 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores6.core.data 0.541676 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores7.core.inst 0.215908 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::processor.cores7.core.data 0.544722 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.demandMshrMissRate::total 0.520602 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::cache_hierarchy.l1dcaches0.prefetcher 0.522328 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::cache_hierarchy.l1dcaches1.prefetcher 0.518594 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::cache_hierarchy.l1dcaches2.prefetcher 0.503666 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::cache_hierarchy.l1dcaches3.prefetcher 0.506210 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::cache_hierarchy.l1dcaches4.prefetcher 0.535025 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::cache_hierarchy.l1dcaches5.prefetcher 0.524106 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::cache_hierarchy.l1dcaches6.prefetcher 0.517147 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::cache_hierarchy.l1dcaches7.prefetcher 0.535046 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::cache_hierarchy.l2cache.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores0.core.inst 0.327078 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores0.core.data 0.562437 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores1.core.inst 0.399671 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores1.core.data 0.546443 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores2.core.inst 0.135143 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores2.core.data 0.542971 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores3.core.inst 0.077762 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores3.core.data 0.543898 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores4.core.inst 0.143805 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores4.core.data 0.547442 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores5.core.inst 0.122011 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores5.core.data 0.529576 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores6.core.inst 0.107570 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores6.core.data 0.541676 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores7.core.inst 0.215908 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::processor.cores7.core.data 0.544722 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.overallMshrMissRate::total 0.585721 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::cache_hierarchy.l1dcaches0.prefetcher 83903.594101 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::cache_hierarchy.l1dcaches1.prefetcher 83300.075040 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::cache_hierarchy.l1dcaches2.prefetcher 83131.719350 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::cache_hierarchy.l1dcaches3.prefetcher 82747.201220 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::cache_hierarchy.l1dcaches4.prefetcher 84472.870484 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::cache_hierarchy.l1dcaches5.prefetcher 83886.551142 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::cache_hierarchy.l1dcaches6.prefetcher 82849.429266 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::cache_hierarchy.l1dcaches7.prefetcher 84240.134273 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores0.core.inst 68516.842082 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores0.core.data 74038.760847 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores1.core.inst 61083.676907 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores1.core.data 74217.542704 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores2.core.inst 67941.706635 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores2.core.data 74968.183420 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores3.core.inst 64782.392005 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores3.core.data 74456.191374 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores4.core.inst 66924.686768 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores4.core.data 75104.584506 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores5.core.inst 69699.987688 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores5.core.data 75101.468404 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores6.core.inst 64568.566355 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores6.core.data 74812.973749 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores7.core.inst 69743.718329 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::processor.cores7.core.data 74693.542757 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.demandAvgMshrMissLatency::total 81078.673561 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches0.prefetcher 83903.594101 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches1.prefetcher 83300.075040 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches2.prefetcher 83131.719350 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches3.prefetcher 82747.201220 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches4.prefetcher 84472.870484 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches5.prefetcher 83886.551142 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches6.prefetcher 82849.429266 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches7.prefetcher 84240.134273 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::cache_hierarchy.l2cache.prefetcher 72737.549344 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores0.core.inst 68516.842082 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores0.core.data 74038.760847 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores1.core.inst 61083.676907 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores1.core.data 74217.542704 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores2.core.inst 67941.706635 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores2.core.data 74968.183420 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores3.core.inst 64782.392005 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores3.core.data 74456.191374 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores4.core.inst 66924.686768 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores4.core.data 75104.584506 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores5.core.inst 69699.987688 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores5.core.data 75101.468404 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores6.core.inst 64568.566355 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores6.core.data 74812.973749 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores7.core.inst 69743.718329 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::processor.cores7.core.data 74693.542757 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.overallAvgMshrMissLatency::total 80151.333981 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.replacements 11483080 # number of replacements (Count)
board.cache_hierarchy.l2cache.CleanEvict.mshrMisses::writebacks 60518 # number of CleanEvict MSHR misses (Count)
board.cache_hierarchy.l2cache.CleanEvict.mshrMisses::total 60518 # number of CleanEvict MSHR misses (Count)
board.cache_hierarchy.l2cache.CleanEvict.mshrMissRate::writebacks inf # mshr miss rate for CleanEvict accesses (Ratio)
board.cache_hierarchy.l2cache.CleanEvict.mshrMissRate::total inf # mshr miss rate for CleanEvict accesses (Ratio)
board.cache_hierarchy.l2cache.HardPFReq.mshrMisses::cache_hierarchy.l2cache.prefetcher 1276690 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l2cache.HardPFReq.mshrMisses::total 1276690 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l2cache.HardPFReq.mshrMissLatency::cache_hierarchy.l2cache.prefetcher 92863301872 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.HardPFReq.mshrMissLatency::total 92863301872 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.HardPFReq.mshrMissRate::cache_hierarchy.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l2cache.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l2cache.HardPFReq.avgMshrMissLatency::cache_hierarchy.l2cache.prefetcher 72737.549344 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.HardPFReq.avgMshrMissLatency::total 72737.549344 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.hits::cache_hierarchy.l1dcaches0.prefetcher 21 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.hits::cache_hierarchy.l1dcaches1.prefetcher 22 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.hits::cache_hierarchy.l1dcaches2.prefetcher 19 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.hits::cache_hierarchy.l1dcaches3.prefetcher 21 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.hits::cache_hierarchy.l1dcaches4.prefetcher 16 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.hits::cache_hierarchy.l1dcaches5.prefetcher 21 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.hits::cache_hierarchy.l1dcaches6.prefetcher 13 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.hits::cache_hierarchy.l1dcaches7.prefetcher 21 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.hits::processor.cores0.core.data 41729 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.hits::processor.cores1.core.data 39820 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.hits::processor.cores2.core.data 40630 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.hits::processor.cores3.core.data 43460 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.hits::processor.cores4.core.data 30046 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.hits::processor.cores5.core.data 31187 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.hits::processor.cores6.core.data 39214 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.hits::processor.cores7.core.data 30898 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.hits::total 297138 # number of ReadExReq hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::cache_hierarchy.l1dcaches0.prefetcher 176 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::cache_hierarchy.l1dcaches1.prefetcher 154 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::cache_hierarchy.l1dcaches2.prefetcher 143 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::cache_hierarchy.l1dcaches3.prefetcher 175 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::cache_hierarchy.l1dcaches4.prefetcher 166 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::cache_hierarchy.l1dcaches5.prefetcher 171 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::cache_hierarchy.l1dcaches6.prefetcher 175 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::cache_hierarchy.l1dcaches7.prefetcher 196 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::processor.cores0.core.data 148262 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::processor.cores1.core.data 136493 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::processor.cores2.core.data 131198 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::processor.cores3.core.data 133495 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::processor.cores4.core.data 121290 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::processor.cores5.core.data 119499 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::processor.cores6.core.data 131785 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::processor.cores7.core.data 118656 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.misses::total 1042034 # number of ReadExReq misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::cache_hierarchy.l1dcaches0.prefetcher 15665435 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::cache_hierarchy.l1dcaches1.prefetcher 14036439 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::cache_hierarchy.l1dcaches2.prefetcher 13912951 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::cache_hierarchy.l1dcaches3.prefetcher 16718931 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::cache_hierarchy.l1dcaches4.prefetcher 15985937 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::cache_hierarchy.l1dcaches5.prefetcher 16062441 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::cache_hierarchy.l1dcaches6.prefetcher 15811927 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::cache_hierarchy.l1dcaches7.prefetcher 19592931 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::processor.cores0.core.data 10186665524 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::processor.cores1.core.data 9461232050 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::processor.cores2.core.data 9195885690 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::processor.cores3.core.data 9309345917 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::processor.cores4.core.data 8437473685 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::processor.cores5.core.data 8294663647 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::processor.cores6.core.data 9259277435 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::processor.cores7.core.data 8244927942 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.missLatency::total 72517258882 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.accesses::cache_hierarchy.l1dcaches0.prefetcher 197 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.accesses::cache_hierarchy.l1dcaches1.prefetcher 176 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.accesses::cache_hierarchy.l1dcaches2.prefetcher 162 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.accesses::cache_hierarchy.l1dcaches3.prefetcher 196 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.accesses::cache_hierarchy.l1dcaches4.prefetcher 182 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.accesses::cache_hierarchy.l1dcaches5.prefetcher 192 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.accesses::cache_hierarchy.l1dcaches6.prefetcher 188 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.accesses::cache_hierarchy.l1dcaches7.prefetcher 217 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.accesses::processor.cores0.core.data 189991 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.accesses::processor.cores1.core.data 176313 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.accesses::processor.cores2.core.data 171828 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.accesses::processor.cores3.core.data 176955 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.accesses::processor.cores4.core.data 151336 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.accesses::processor.cores5.core.data 150686 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.accesses::processor.cores6.core.data 170999 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.accesses::processor.cores7.core.data 149554 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.accesses::total 1339172 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.ReadExReq.missRate::cache_hierarchy.l1dcaches0.prefetcher 0.893401 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.missRate::cache_hierarchy.l1dcaches1.prefetcher 0.875000 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.missRate::cache_hierarchy.l1dcaches2.prefetcher 0.882716 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.missRate::cache_hierarchy.l1dcaches3.prefetcher 0.892857 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.missRate::cache_hierarchy.l1dcaches4.prefetcher 0.912088 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.missRate::cache_hierarchy.l1dcaches5.prefetcher 0.890625 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.missRate::cache_hierarchy.l1dcaches6.prefetcher 0.930851 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.missRate::cache_hierarchy.l1dcaches7.prefetcher 0.903226 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.missRate::processor.cores0.core.data 0.780363 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.missRate::processor.cores1.core.data 0.774152 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.missRate::processor.cores2.core.data 0.763543 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.missRate::processor.cores3.core.data 0.754401 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.missRate::processor.cores4.core.data 0.801462 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.missRate::processor.cores5.core.data 0.793033 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.missRate::processor.cores6.core.data 0.770677 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.missRate::processor.cores7.core.data 0.793399 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.missRate::total 0.778118 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::cache_hierarchy.l1dcaches0.prefetcher 89008.153409 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::cache_hierarchy.l1dcaches1.prefetcher 91145.707792 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::cache_hierarchy.l1dcaches2.prefetcher 97293.363636 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::cache_hierarchy.l1dcaches3.prefetcher 95536.748571 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::cache_hierarchy.l1dcaches4.prefetcher 96300.825301 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::cache_hierarchy.l1dcaches5.prefetcher 93932.403509 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::cache_hierarchy.l1dcaches6.prefetcher 90353.868571 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::cache_hierarchy.l1dcaches7.prefetcher 99963.933673 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::processor.cores0.core.data 68707.190811 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::processor.cores1.core.data 69316.610009 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::processor.cores2.core.data 70091.660620 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::processor.cores3.core.data 69735.540035 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::processor.cores4.core.data 69564.462734 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::processor.cores5.core.data 69411.992125 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::processor.cores6.core.data 70260.480593 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::processor.cores7.core.data 69485.975779 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMissLatency::total 69592.027594 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.mshrHits::cache_hierarchy.l1dcaches2.prefetcher 1 # number of ReadExReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrHits::cache_hierarchy.l1dcaches7.prefetcher 1 # number of ReadExReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrHits::processor.cores0.core.data 31 # number of ReadExReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrHits::processor.cores1.core.data 16 # number of ReadExReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrHits::processor.cores2.core.data 51 # number of ReadExReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrHits::processor.cores3.core.data 63 # number of ReadExReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrHits::processor.cores4.core.data 64 # number of ReadExReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrHits::processor.cores5.core.data 89 # number of ReadExReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrHits::processor.cores6.core.data 33 # number of ReadExReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrHits::processor.cores7.core.data 61 # number of ReadExReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrHits::total 410 # number of ReadExReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::cache_hierarchy.l1dcaches0.prefetcher 176 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::cache_hierarchy.l1dcaches1.prefetcher 154 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::cache_hierarchy.l1dcaches2.prefetcher 142 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::cache_hierarchy.l1dcaches3.prefetcher 175 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::cache_hierarchy.l1dcaches4.prefetcher 166 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::cache_hierarchy.l1dcaches5.prefetcher 171 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::cache_hierarchy.l1dcaches6.prefetcher 175 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::cache_hierarchy.l1dcaches7.prefetcher 195 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::processor.cores0.core.data 148231 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::processor.cores1.core.data 136477 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::processor.cores2.core.data 131147 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::processor.cores3.core.data 133432 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::processor.cores4.core.data 121226 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::processor.cores5.core.data 119410 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::processor.cores6.core.data 131752 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::processor.cores7.core.data 118595 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMisses::total 1041624 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::cache_hierarchy.l1dcaches0.prefetcher 15577435 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::cache_hierarchy.l1dcaches1.prefetcher 13959439 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::cache_hierarchy.l1dcaches2.prefetcher 13827451 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::cache_hierarchy.l1dcaches3.prefetcher 16631431 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::cache_hierarchy.l1dcaches4.prefetcher 15902937 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::cache_hierarchy.l1dcaches5.prefetcher 15976941 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::cache_hierarchy.l1dcaches6.prefetcher 15724427 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::cache_hierarchy.l1dcaches7.prefetcher 19408932 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::processor.cores0.core.data 10110793029 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::processor.cores1.core.data 9392404552 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::processor.cores2.core.data 9128776191 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::processor.cores3.core.data 9240935917 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::processor.cores4.core.data 8375042689 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::processor.cores5.core.data 8232092652 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::processor.cores6.core.data 9192284936 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::processor.cores7.core.data 8183953445 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissLatency::total 71983292404 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::cache_hierarchy.l1dcaches0.prefetcher 0.893401 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::cache_hierarchy.l1dcaches1.prefetcher 0.875000 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::cache_hierarchy.l1dcaches2.prefetcher 0.876543 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::cache_hierarchy.l1dcaches3.prefetcher 0.892857 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::cache_hierarchy.l1dcaches4.prefetcher 0.912088 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::cache_hierarchy.l1dcaches5.prefetcher 0.890625 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::cache_hierarchy.l1dcaches6.prefetcher 0.930851 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::cache_hierarchy.l1dcaches7.prefetcher 0.898618 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::processor.cores0.core.data 0.780200 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::processor.cores1.core.data 0.774061 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::processor.cores2.core.data 0.763246 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::processor.cores3.core.data 0.754045 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::processor.cores4.core.data 0.801039 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::processor.cores5.core.data 0.792443 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::processor.cores6.core.data 0.770484 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::processor.cores7.core.data 0.792991 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.mshrMissRate::total 0.777812 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::cache_hierarchy.l1dcaches0.prefetcher 88508.153409 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::cache_hierarchy.l1dcaches1.prefetcher 90645.707792 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::cache_hierarchy.l1dcaches2.prefetcher 97376.415493 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::cache_hierarchy.l1dcaches3.prefetcher 95036.748571 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::cache_hierarchy.l1dcaches4.prefetcher 95800.825301 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::cache_hierarchy.l1dcaches5.prefetcher 93432.403509 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::cache_hierarchy.l1dcaches6.prefetcher 89853.868571 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::cache_hierarchy.l1dcaches7.prefetcher 99532.984615 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::processor.cores0.core.data 68209.706667 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::processor.cores1.core.data 68820.420672 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::processor.cores2.core.data 69607.205586 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::processor.cores3.core.data 69255.770108 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::processor.cores4.core.data 69086.191815 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::processor.cores5.core.data 68939.725752 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::processor.cores6.core.data 69769.604530 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::processor.cores7.core.data 69007.575741 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadExReq.avgMshrMissLatency::total 69106.791322 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.hits::cache_hierarchy.l1dcaches0.prefetcher 731202 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.hits::cache_hierarchy.l1dcaches1.prefetcher 863642 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.hits::cache_hierarchy.l1dcaches2.prefetcher 936424 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.hits::cache_hierarchy.l1dcaches3.prefetcher 936419 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.hits::cache_hierarchy.l1dcaches4.prefetcher 777398 # number of ReadSharedReq hits (Count)
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board.cache_hierarchy.l2cache.ReadSharedReq.misses::processor.cores7.core.data 199771 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.misses::total 9423418 # number of ReadSharedReq misses (Count)
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board.cache_hierarchy.l2cache.ReadSharedReq.missRate::processor.cores0.core.data 0.470330 # miss rate for ReadSharedReq accesses (Ratio)
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board.cache_hierarchy.l2cache.ReadSharedReq.missRate::processor.cores1.core.data 0.461172 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.missRate::processor.cores2.core.inst 0.340363 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.missRate::processor.cores2.core.data 0.470618 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.missRate::processor.cores3.core.inst 0.271966 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.missRate::processor.cores3.core.data 0.474667 # miss rate for ReadSharedReq accesses (Ratio)
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board.cache_hierarchy.l2cache.ReadSharedReq.missRate::processor.cores4.core.data 0.466139 # miss rate for ReadSharedReq accesses (Ratio)
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board.cache_hierarchy.l2cache.ReadSharedReq.missRate::processor.cores6.core.data 0.468031 # miss rate for ReadSharedReq accesses (Ratio)
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board.cache_hierarchy.l2cache.ReadSharedReq.missRate::processor.cores7.core.data 0.468665 # miss rate for ReadSharedReq accesses (Ratio)
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board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::cache_hierarchy.l1dcaches3.prefetcher 82752.296296 # average ReadSharedReq miss latency ((Tick/Count))
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board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::cache_hierarchy.l1dcaches5.prefetcher 83886.230162 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::cache_hierarchy.l1dcaches6.prefetcher 82861.290412 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::cache_hierarchy.l1dcaches7.prefetcher 84276.862615 # average ReadSharedReq miss latency ((Tick/Count))
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board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores0.core.data 78670.819232 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores1.core.inst 59582.109239 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores1.core.data 78104.086924 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores2.core.inst 58390.097792 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores2.core.data 78352.436789 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores3.core.inst 55569.220020 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores3.core.data 77766.325051 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores4.core.inst 58720.506010 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores4.core.data 79062.238430 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores5.core.inst 58785.795820 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores5.core.data 79090.057730 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores6.core.inst 56359.326266 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores6.core.data 78023.953599 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores7.core.inst 61628.445073 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::processor.cores7.core.data 78311.355647 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMissLatency::total 82277.829718 # average ReadSharedReq miss latency ((Tick/Count))
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board.cache_hierarchy.l2cache.ReadSharedReq.mshrHits::processor.cores6.core.data 3014 # number of ReadSharedReq MSHR hits (Count)
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board.cache_hierarchy.l2cache.ReadSharedReq.mshrHits::processor.cores7.core.data 4710 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrHits::total 258312 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::cache_hierarchy.l1dcaches0.prefetcher 822937 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::cache_hierarchy.l1dcaches1.prefetcher 954716 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::cache_hierarchy.l1dcaches2.prefetcher 971104 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::cache_hierarchy.l1dcaches3.prefetcher 982480 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::cache_hierarchy.l1dcaches4.prefetcher 914531 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::cache_hierarchy.l1dcaches5.prefetcher 895837 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::cache_hierarchy.l1dcaches6.prefetcher 988071 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::cache_hierarchy.l1dcaches7.prefetcher 913285 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores0.core.inst 13526 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores0.core.data 197029 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores1.core.inst 23111 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores1.core.data 205507 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores2.core.inst 5396 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores2.core.data 224763 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores3.core.inst 3102 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores3.core.data 225870 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores4.core.inst 5638 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores4.core.data 191284 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores5.core.inst 4792 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores5.core.data 187468 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores6.core.inst 4280 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores6.core.data 226485 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores7.core.inst 8833 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::processor.cores7.core.data 195061 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMisses::total 9165106 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.l1dcaches0.prefetcher 69046561616 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.l1dcaches1.prefetcher 79526783214 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.l1dcaches2.prefetcher 80727522441 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.l1dcaches3.prefetcher 81295319584 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.l1dcaches4.prefetcher 77251178276 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.l1dcaches5.prefetcher 75147043975 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.l1dcaches6.prefetcher 81859892647 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.l1dcaches7.prefetcher 76932268924 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores0.core.inst 926758806 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores0.core.data 15451829541 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores1.core.inst 1411704857 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores1.core.data 15988807572 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores2.core.inst 366613449 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores2.core.data 17553149970 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores3.core.inst 200954980 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores3.core.data 17511322556 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores4.core.inst 377321384 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores4.core.data 15095891015 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores5.core.inst 334002341 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores5.core.data 14814895769 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores6.core.inst 276353464 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores6.core.data 17608490341 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores7.core.inst 616046264 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::processor.cores7.core.data 15244124402 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissLatency::total 755564837388 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::cache_hierarchy.l1dcaches0.prefetcher 0.522281 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::cache_hierarchy.l1dcaches1.prefetcher 0.518560 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::cache_hierarchy.l1dcaches2.prefetcher 0.503634 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::cache_hierarchy.l1dcaches3.prefetcher 0.506171 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::cache_hierarchy.l1dcaches4.prefetcher 0.534985 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::cache_hierarchy.l1dcaches5.prefetcher 0.524065 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::cache_hierarchy.l1dcaches6.prefetcher 0.517106 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::cache_hierarchy.l1dcaches7.prefetcher 0.534999 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores0.core.inst 0.327078 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores0.core.data 0.464830 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores1.core.inst 0.399671 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores1.core.data 0.457166 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores2.core.inst 0.135143 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores2.core.data 0.464715 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores3.core.inst 0.077762 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores3.core.data 0.467010 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores4.core.inst 0.143805 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores4.core.data 0.455960 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores5.core.inst 0.122011 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores5.core.data 0.437199 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores6.core.inst 0.107570 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores6.core.data 0.461884 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores7.core.inst 0.215908 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::processor.cores7.core.data 0.457616 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.mshrMissRate::total 0.501745 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.l1dcaches0.prefetcher 83902.609332 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.l1dcaches1.prefetcher 83298.890156 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.l1dcaches2.prefetcher 83129.636415 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.l1dcaches3.prefetcher 82745.012198 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.l1dcaches4.prefetcher 84470.814304 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.l1dcaches5.prefetcher 83884.729002 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.l1dcaches6.prefetcher 82848.188690 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.l1dcaches7.prefetcher 84236.869021 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores0.core.inst 68516.842082 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores0.core.data 78424.138279 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores1.core.inst 61083.676907 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores1.core.data 77801.766227 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores2.core.inst 67941.706635 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores2.core.data 78096.261262 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores3.core.inst 64782.392005 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores3.core.data 77528.324063 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores4.core.inst 66924.686768 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores4.core.data 78918.733480 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores5.core.inst 69699.987688 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores5.core.data 79026.264584 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores6.core.inst 64568.566355 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores6.core.data 77746.828006 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores7.core.inst 69743.718329 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores7.core.data 78150.549838 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.ReadSharedReq.avgMshrMissLatency::total 82439.290652 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.UpgradeReq.hits::processor.cores0.core.data 1541 # number of UpgradeReq hits (Count)
board.cache_hierarchy.l2cache.UpgradeReq.hits::processor.cores1.core.data 427 # number of UpgradeReq hits (Count)
board.cache_hierarchy.l2cache.UpgradeReq.hits::processor.cores2.core.data 2629 # number of UpgradeReq hits (Count)
board.cache_hierarchy.l2cache.UpgradeReq.hits::processor.cores3.core.data 7054 # number of UpgradeReq hits (Count)
board.cache_hierarchy.l2cache.UpgradeReq.hits::processor.cores4.core.data 11012 # number of UpgradeReq hits (Count)
board.cache_hierarchy.l2cache.UpgradeReq.hits::processor.cores5.core.data 10037 # number of UpgradeReq hits (Count)
board.cache_hierarchy.l2cache.UpgradeReq.hits::processor.cores6.core.data 6714 # number of UpgradeReq hits (Count)
board.cache_hierarchy.l2cache.UpgradeReq.hits::processor.cores7.core.data 11781 # number of UpgradeReq hits (Count)
board.cache_hierarchy.l2cache.UpgradeReq.hits::total 51195 # number of UpgradeReq hits (Count)
board.cache_hierarchy.l2cache.UpgradeReq.misses::processor.cores1.core.data 308 # number of UpgradeReq misses (Count)
board.cache_hierarchy.l2cache.UpgradeReq.misses::processor.cores2.core.data 450 # number of UpgradeReq misses (Count)
board.cache_hierarchy.l2cache.UpgradeReq.misses::processor.cores3.core.data 465 # number of UpgradeReq misses (Count)
board.cache_hierarchy.l2cache.UpgradeReq.misses::processor.cores6.core.data 446 # number of UpgradeReq misses (Count)
board.cache_hierarchy.l2cache.UpgradeReq.misses::total 1669 # number of UpgradeReq misses (Count)
board.cache_hierarchy.l2cache.UpgradeReq.missLatency::processor.cores1.core.data 21000 # number of UpgradeReq miss ticks (Tick)
board.cache_hierarchy.l2cache.UpgradeReq.missLatency::processor.cores2.core.data 31500 # number of UpgradeReq miss ticks (Tick)
board.cache_hierarchy.l2cache.UpgradeReq.missLatency::processor.cores3.core.data 42000 # number of UpgradeReq miss ticks (Tick)
board.cache_hierarchy.l2cache.UpgradeReq.missLatency::total 94500 # number of UpgradeReq miss ticks (Tick)
board.cache_hierarchy.l2cache.UpgradeReq.accesses::processor.cores0.core.data 1541 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.UpgradeReq.accesses::processor.cores1.core.data 735 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.UpgradeReq.accesses::processor.cores2.core.data 3079 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.UpgradeReq.accesses::processor.cores3.core.data 7519 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.UpgradeReq.accesses::processor.cores4.core.data 11012 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.UpgradeReq.accesses::processor.cores5.core.data 10037 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.UpgradeReq.accesses::processor.cores6.core.data 7160 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.UpgradeReq.accesses::processor.cores7.core.data 11781 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.UpgradeReq.accesses::total 52864 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.UpgradeReq.missRate::processor.cores1.core.data 0.419048 # miss rate for UpgradeReq accesses (Ratio)
board.cache_hierarchy.l2cache.UpgradeReq.missRate::processor.cores2.core.data 0.146151 # miss rate for UpgradeReq accesses (Ratio)
board.cache_hierarchy.l2cache.UpgradeReq.missRate::processor.cores3.core.data 0.061843 # miss rate for UpgradeReq accesses (Ratio)
board.cache_hierarchy.l2cache.UpgradeReq.missRate::processor.cores6.core.data 0.062291 # miss rate for UpgradeReq accesses (Ratio)
board.cache_hierarchy.l2cache.UpgradeReq.missRate::total 0.031572 # miss rate for UpgradeReq accesses (Ratio)
board.cache_hierarchy.l2cache.UpgradeReq.avgMissLatency::processor.cores1.core.data 68.181818 # average UpgradeReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.UpgradeReq.avgMissLatency::processor.cores2.core.data 70 # average UpgradeReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.UpgradeReq.avgMissLatency::processor.cores3.core.data 90.322581 # average UpgradeReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.UpgradeReq.avgMissLatency::total 56.620731 # average UpgradeReq miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.UpgradeReq.mshrMisses::processor.cores1.core.data 308 # number of UpgradeReq MSHR misses (Count)
board.cache_hierarchy.l2cache.UpgradeReq.mshrMisses::processor.cores2.core.data 450 # number of UpgradeReq MSHR misses (Count)
board.cache_hierarchy.l2cache.UpgradeReq.mshrMisses::processor.cores3.core.data 465 # number of UpgradeReq MSHR misses (Count)
board.cache_hierarchy.l2cache.UpgradeReq.mshrMisses::processor.cores6.core.data 446 # number of UpgradeReq MSHR misses (Count)
board.cache_hierarchy.l2cache.UpgradeReq.mshrMisses::total 1669 # number of UpgradeReq MSHR misses (Count)
board.cache_hierarchy.l2cache.UpgradeReq.mshrMissLatency::processor.cores1.core.data 3082500 # number of UpgradeReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.UpgradeReq.mshrMissLatency::processor.cores2.core.data 4505000 # number of UpgradeReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.UpgradeReq.mshrMissLatency::processor.cores3.core.data 4652999 # number of UpgradeReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.UpgradeReq.mshrMissLatency::processor.cores6.core.data 4463500 # number of UpgradeReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.UpgradeReq.mshrMissLatency::total 16703999 # number of UpgradeReq MSHR miss ticks (Tick)
board.cache_hierarchy.l2cache.UpgradeReq.mshrMissRate::processor.cores1.core.data 0.419048 # mshr miss rate for UpgradeReq accesses (Ratio)
board.cache_hierarchy.l2cache.UpgradeReq.mshrMissRate::processor.cores2.core.data 0.146151 # mshr miss rate for UpgradeReq accesses (Ratio)
board.cache_hierarchy.l2cache.UpgradeReq.mshrMissRate::processor.cores3.core.data 0.061843 # mshr miss rate for UpgradeReq accesses (Ratio)
board.cache_hierarchy.l2cache.UpgradeReq.mshrMissRate::processor.cores6.core.data 0.062291 # mshr miss rate for UpgradeReq accesses (Ratio)
board.cache_hierarchy.l2cache.UpgradeReq.mshrMissRate::total 0.031572 # mshr miss rate for UpgradeReq accesses (Ratio)
board.cache_hierarchy.l2cache.UpgradeReq.avgMshrMissLatency::processor.cores1.core.data 10008.116883 # average UpgradeReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.UpgradeReq.avgMshrMissLatency::processor.cores2.core.data 10011.111111 # average UpgradeReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.UpgradeReq.avgMshrMissLatency::processor.cores3.core.data 10006.449462 # average UpgradeReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.UpgradeReq.avgMshrMissLatency::processor.cores6.core.data 10007.847534 # average UpgradeReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.UpgradeReq.avgMshrMissLatency::total 10008.387657 # average UpgradeReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l2cache.WritebackDirty.hits::writebacks 8082177 # number of WritebackDirty hits (Count)
board.cache_hierarchy.l2cache.WritebackDirty.hits::total 8082177 # number of WritebackDirty hits (Count)
board.cache_hierarchy.l2cache.WritebackDirty.accesses::writebacks 8082177 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.WritebackDirty.accesses::total 8082177 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.l2cache.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2cache.prefetcher.demandMshrMisses 10206730 # demands not covered by prefetchs (Count)
board.cache_hierarchy.l2cache.prefetcher.pfIssued 2645592 # number of hwpf issued (Count)
board.cache_hierarchy.l2cache.prefetcher.pfUnused 32936 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l2cache.prefetcher.pfUseful 1097605 # number of useful prefetch (Count)
board.cache_hierarchy.l2cache.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l2cache.prefetcher.accuracy 0.414881 # accuracy of the prefetcher (Count)
board.cache_hierarchy.l2cache.prefetcher.coverage 0.097096 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l2cache.prefetcher.pfHitInCache 1105448 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l2cache.prefetcher.pfHitInMSHR 263442 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l2cache.prefetcher.pfHitInWB 12 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l2cache.prefetcher.pfLate 1368902 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l2cache.prefetcher.pfIdentified 3411050 # number of prefetch candidates identified (Count)
board.cache_hierarchy.l2cache.prefetcher.pfBufferHit 409889 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l2cache.prefetcher.pfRemovedDemand 194255 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l2cache.prefetcher.pfRemovedFull 6969 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l2cache.prefetcher.pfSpanPage 784074 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l2cache.prefetcher.pfUsefulSpanPage 310207 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l2cache.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l2cache.tags.tagsInUse 32698.763570 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l2cache.tags.totalRefs 39370048 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l2cache.tags.sampledRefs 11483080 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l2cache.tags.avgRefs 3.428527 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l2cache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l2cache.tags.occupancies::writebacks 105.950359 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::cache_hierarchy.l1dcaches0.prefetcher 2017.694098 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::cache_hierarchy.l1dcaches1.prefetcher 2475.673686 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::cache_hierarchy.l1dcaches2.prefetcher 2636.540034 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::cache_hierarchy.l1dcaches3.prefetcher 2557.842347 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::cache_hierarchy.l1dcaches4.prefetcher 2378.277911 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::cache_hierarchy.l1dcaches5.prefetcher 2319.020688 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::cache_hierarchy.l1dcaches6.prefetcher 2669.321731 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::cache_hierarchy.l1dcaches7.prefetcher 2398.513580 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::cache_hierarchy.l2cache.prefetcher 4795.325298 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores0.core.inst 50.468153 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores0.core.data 987.883942 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores1.core.inst 62.297986 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores1.core.data 1007.683198 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores2.core.inst 27.652285 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores2.core.data 1098.460554 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores3.core.inst 10.755404 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores3.core.data 1065.532735 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores4.core.inst 17.271966 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores4.core.data 950.829026 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores5.core.inst 14.411106 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores5.core.data 930.031517 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores6.core.inst 29.457824 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores6.core.data 1090.544845 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores7.core.inst 38.296953 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.occupancies::processor.cores7.core.data 963.026343 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::writebacks 0.003233 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::cache_hierarchy.l1dcaches0.prefetcher 0.061575 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::cache_hierarchy.l1dcaches1.prefetcher 0.075552 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::cache_hierarchy.l1dcaches2.prefetcher 0.080461 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::cache_hierarchy.l1dcaches3.prefetcher 0.078059 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::cache_hierarchy.l1dcaches4.prefetcher 0.072579 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::cache_hierarchy.l1dcaches5.prefetcher 0.070771 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::cache_hierarchy.l1dcaches6.prefetcher 0.081461 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::cache_hierarchy.l1dcaches7.prefetcher 0.073197 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::cache_hierarchy.l2cache.prefetcher 0.146342 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores0.core.inst 0.001540 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores0.core.data 0.030148 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores1.core.inst 0.001901 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores1.core.data 0.030752 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores2.core.inst 0.000844 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores2.core.data 0.033522 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores3.core.inst 0.000328 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores3.core.data 0.032517 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores4.core.inst 0.000527 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores4.core.data 0.029017 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores5.core.inst 0.000440 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores5.core.data 0.028382 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores6.core.inst 0.000899 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores6.core.data 0.033281 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores7.core.inst 0.001169 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::processor.cores7.core.data 0.029389 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.avgOccs::total 0.997887 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l2cache.tags.occupanciesTaskId::1022 25633 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2cache.tags.occupanciesTaskId::1024 7135 # Occupied blocks per task id (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1022::1 22 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1022::2 5013 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1022::3 20153 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1022::4 445 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1024::0 6 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1024::1 83 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1024::2 1167 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1024::3 5749 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ageTaskId_1024::4 130 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l2cache.tags.ratioOccsTaskId::1022 0.782257 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2cache.tags.ratioOccsTaskId::1024 0.217743 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l2cache.tags.tagAccesses 630413675 # Number of tag accesses (Count)
board.cache_hierarchy.l2cache.tags.dataAccesses 630413675 # Number of data accesses (Count)
board.cache_hierarchy.l2cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.transDist::ReadResp 10441415 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WritebackDirty 4580922 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::CleanEvict 6857303 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::UpgradeReq 339746 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq 1045564 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp 1041624 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq 10441410 # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2cache.mem_side_port::board.memory.mem_ctrl0.port 17291966 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2cache.mem_side_port::board.memory.mem_ctrl1.port 17456018 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l2cache.mem_side_port::total 34747984 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total 34747984 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2cache.mem_side_port::board.memory.mem_ctrl0.port 513933760 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2cache.mem_side_port::board.memory.mem_ctrl1.port 514159744 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l2cache.mem_side_port::total 1028093504 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total 1028093504 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops 342016 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 11826720 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 11826720 100.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 11826720 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy 7163960241 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization 0.1 # Layer utilization (Ratio)
board.cache_hierarchy.membus.reqLayer1.occupancy 7171906783 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer1.utilization 0.1 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer9.occupancy 13205645507 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer9.utilization 0.1 # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests 23264945 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 11796796 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 500 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.memory.mem_ctrl0.avgPriority_writebacks::samples 2289879.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_cache_hierarchy.l1dcaches0.prefetcher::samples 409511.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_cache_hierarchy.l1dcaches1.prefetcher::samples 474873.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_cache_hierarchy.l1dcaches2.prefetcher::samples 483273.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_cache_hierarchy.l1dcaches3.prefetcher::samples 488710.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_cache_hierarchy.l1dcaches4.prefetcher::samples 454985.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_cache_hierarchy.l1dcaches5.prefetcher::samples 445664.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_cache_hierarchy.l1dcaches6.prefetcher::samples 491464.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_cache_hierarchy.l1dcaches7.prefetcher::samples 454208.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_cache_hierarchy.l2cache.prefetcher::samples 631103.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores0.core.inst::samples 6810.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores0.core.data::samples 174983.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores1.core.inst::samples 11475.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores1.core.data::samples 173756.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores2.core.inst::samples 2729.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores2.core.data::samples 180178.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores3.core.inst::samples 1577.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores3.core.data::samples 182084.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores4.core.inst::samples 2815.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores4.core.data::samples 158346.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores5.core.inst::samples 2413.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores5.core.data::samples 155615.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores6.core.inst::samples 2148.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores6.core.data::samples 181461.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores7.core.inst::samples 4505.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.avgPriority_processor.cores7.core.data::samples 158924.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl0.priorityMinLatency 0.000000017492 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl0.priorityMaxLatency 0.001253058652 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl0.numReadWriteTurnArounds 135542 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl0.numWriteReadTurnArounds 135542 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl0.numStayReadState 11132811 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl0.numStayWriteState 2161464 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl0.readReqs 5740334 # Number of read requests accepted (Count)
board.memory.mem_ctrl0.writeReqs 2289879 # Number of write requests accepted (Count)
board.memory.mem_ctrl0.readBursts 5740334 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl0.writeBursts 2289879 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl0.servicedByWrQ 6724 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl0.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl0.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl0.avgRdQLen 3.42 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.avgWrQLen 57.26 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl0.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl0.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl0.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.readPktSize::6 5740334 # Read request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.writePktSize::6 2289879 # Write request sizes (log2) (Count)
board.memory.mem_ctrl0.rdQLenPdf::0 1029691 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::1 936411 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::2 812566 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::3 690021 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::4 572898 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::5 468532 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::6 375543 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::7 289122 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::8 209122 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::9 143348 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::10 91901 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::11 54550 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::12 30610 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::13 16151 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::14 7710 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::15 3414 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::16 1377 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::17 491 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::18 131 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::19 21 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
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board.memory.mem_ctrl0.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::0 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::1 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::2 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::3 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::4 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::5 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::6 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::7 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::8 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::9 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::10 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::11 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::12 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::13 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::14 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::15 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::16 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::17 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::18 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::19 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::20 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::21 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::22 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::23 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::24 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::25 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::26 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::27 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::28 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::29 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::30 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::31 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::32 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::33 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::34 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::35 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::36 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::37 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::38 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::39 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::40 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::41 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::42 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::43 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::44 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::45 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::46 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::47 30613 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::48 35759 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::49 65262 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::50 88869 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::51 106977 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::52 120539 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::53 131303 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::54 140917 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::55 147959 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::56 151900 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::57 155776 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::58 163203 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::59 156143 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::60 147963 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::61 146339 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::62 144779 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::63 144299 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::64 143203 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::65 16770 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::66 11200 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::67 7955 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::68 6037 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::69 4487 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::70 3536 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::71 2784 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::72 2178 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::73 1767 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::74 1539 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::75 1342 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::76 1048 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::77 916 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::78 772 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::79 696 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::80 612 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::81 496 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::82 439 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::83 367 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::84 310 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::85 291 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::86 246 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::87 236 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::88 204 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::89 185 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::90 176 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::91 162 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::92 137 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::93 125 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::94 142 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::95 119 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::96 104 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::97 97 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::98 89 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::99 81 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::100 59 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::101 51 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::102 51 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::103 56 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::104 49 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::105 23 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::106 18 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::107 17 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::108 16 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::109 12 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::110 9 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::111 9 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::112 7 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::113 5 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::114 2 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl0.rdPerTurnAround::samples 135542 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl0.rdPerTurnAround::mean 42.317142 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl0.rdPerTurnAround::gmean 33.536962 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl0.rdPerTurnAround::stdev 65.231832 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl0.rdPerTurnAround::0-511 135470 99.95% 99.95% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl0.rdPerTurnAround::512-1023 47 0.03% 99.98% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl0.rdPerTurnAround::1024-1535 11 0.01% 99.99% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl0.rdPerTurnAround::1536-2047 7 0.01% 99.99% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl0.rdPerTurnAround::2048-2559 2 0.00% 100.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl0.rdPerTurnAround::2560-3071 2 0.00% 100.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl0.rdPerTurnAround::3072-3583 2 0.00% 100.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl0.rdPerTurnAround::17408-17919 1 0.00% 100.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl0.rdPerTurnAround::total 135542 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl0.wrPerTurnAround::samples 135542 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::mean 16.893819 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::gmean 16.815214 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::stdev 1.745558 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::16 97780 72.14% 72.14% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::17 2952 2.18% 74.32% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::18 15501 11.44% 85.75% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::19 7663 5.65% 91.41% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::20 4414 3.26% 94.66% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::21 2586 1.91% 96.57% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::22 1684 1.24% 97.81% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::23 1257 0.93% 98.74% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::24 1147 0.85% 99.59% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::25 317 0.23% 99.82% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::26 118 0.09% 99.91% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::27 58 0.04% 99.95% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::28 27 0.02% 99.97% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::29 20 0.01% 99.99% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::30 7 0.01% 99.99% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::31 4 0.00% 99.99% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::32 2 0.00% 100.00% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::33 2 0.00% 100.00% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::36 2 0.00% 100.00% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::39 1 0.00% 100.00% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.wrPerTurnAround::total 135542 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl0.bytesReadWrQ 430336 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl0.bytesReadSys 367381376 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl0.bytesWrittenSys 146552256 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl0.avgRdBWSys 2632116652.86962366 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.avgWrBWSys 1049978737.98919022 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl0.totGap 139576301000 # Total gap between requests (Tick)
board.memory.mem_ctrl0.avgGap 17381.39 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl0.requestorReadBytes::cache_hierarchy.l1dcaches0.prefetcher 26208704 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::cache_hierarchy.l1dcaches1.prefetcher 30391872 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::cache_hierarchy.l1dcaches2.prefetcher 30929472 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::cache_hierarchy.l1dcaches3.prefetcher 31277440 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::cache_hierarchy.l1dcaches4.prefetcher 29119040 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::cache_hierarchy.l1dcaches5.prefetcher 28522496 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::cache_hierarchy.l1dcaches6.prefetcher 31453696 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::cache_hierarchy.l1dcaches7.prefetcher 29069312 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::cache_hierarchy.l2cache.prefetcher 40390592 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores0.core.inst 435840 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores0.core.data 11198912 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores1.core.inst 734400 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores1.core.data 11120384 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores2.core.inst 174656 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores2.core.data 11531392 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores3.core.inst 100928 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores3.core.data 11653376 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores4.core.inst 180160 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores4.core.data 10134144 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores5.core.inst 154432 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores5.core.data 9959360 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores6.core.inst 137472 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores6.core.data 11613504 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores7.core.inst 288320 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorReadBytes::processor.cores7.core.data 10171136 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl0.requestorWriteBytes::writebacks 146548608 # Per-requestor bytes write to memory (Byte)
board.memory.mem_ctrl0.requestorReadRate::cache_hierarchy.l1dcaches0.prefetcher 187773171.845626473427 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::cache_hierarchy.l1dcaches1.prefetcher 217743624.551839083433 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::cache_hierarchy.l1dcaches2.prefetcher 221595278.459800690413 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::cache_hierarchy.l1dcaches3.prefetcher 224088307.304751545191 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::cache_hierarchy.l1dcaches4.prefetcher 208624375.394512861967 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::cache_hierarchy.l1dcaches5.prefetcher 204350415.147356897593 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::cache_hierarchy.l1dcaches6.prefetcher 225351099.550290375948 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::cache_hierarchy.l1dcaches7.prefetcher 208268097.408026427031 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::cache_hierarchy.l2cache.prefetcher 289379801.937653422356 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores0.core.inst 3122590.846811724827 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores0.core.data 80234994.735338628292 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores1.core.inst 5261634.356411826797 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores1.core.data 79672378.146639943123 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores2.core.inst 1251328.989860381465 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores2.core.data 82617059.265322014689 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores3.core.inst 723102.168197076418 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores3.core.data 83491017.878247588873 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores4.core.inst 1290762.589394273935 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores4.core.data 72606427.346438974142 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores5.core.inst 1106433.438084683148 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores5.core.data 71354181.296124309301 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores6.core.inst 984922.927893037442 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores6.core.data 83205353.546740442514 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores7.core.inst 2065678.673257976538 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadRate::processor.cores7.core.data 72871457.817724898458 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorWriteRate::writebacks 1049952601.766243338585 # Per-requestor bytes write to memory rate ((Byte/Second))
board.memory.mem_ctrl0.requestorReadAccesses::cache_hierarchy.l1dcaches0.prefetcher 410039 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::cache_hierarchy.l1dcaches1.prefetcher 475445 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::cache_hierarchy.l1dcaches2.prefetcher 483968 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::cache_hierarchy.l1dcaches3.prefetcher 489316 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::cache_hierarchy.l1dcaches4.prefetcher 455527 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::cache_hierarchy.l1dcaches5.prefetcher 446224 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::cache_hierarchy.l1dcaches6.prefetcher 492080 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::cache_hierarchy.l1dcaches7.prefetcher 454810 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::cache_hierarchy.l2cache.prefetcher 631899 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores0.core.inst 6810 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores0.core.data 175149 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores1.core.inst 11475 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores1.core.data 173910 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores2.core.inst 2729 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores2.core.data 180322 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores3.core.inst 1577 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores3.core.data 182256 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores4.core.inst 2815 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores4.core.data 158476 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores5.core.inst 2413 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores5.core.data 155760 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores6.core.inst 2148 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores6.core.data 181607 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores7.core.inst 4505 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadAccesses::processor.cores7.core.data 159074 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorWriteAccesses::writebacks 2289879 # Per-requestor write serviced memory accesses (Count)
board.memory.mem_ctrl0.requestorReadTotalLat::cache_hierarchy.l1dcaches0.prefetcher 21597914054 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::cache_hierarchy.l1dcaches1.prefetcher 24765413983 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::cache_hierarchy.l1dcaches2.prefetcher 25105686278 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::cache_hierarchy.l1dcaches3.prefetcher 25210194742 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::cache_hierarchy.l1dcaches4.prefetcher 24245233443 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::cache_hierarchy.l1dcaches5.prefetcher 23442166335 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::cache_hierarchy.l1dcaches6.prefetcher 25363851086 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::cache_hierarchy.l1dcaches7.prefetcher 24102480880 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::cache_hierarchy.l2cache.prefetcher 29742187095 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores0.core.inst 257694348 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores0.core.data 7597225183 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores1.core.inst 350276723 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores1.core.data 7579673631 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores2.core.inst 101254993 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores2.core.data 7971116317 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores3.core.inst 53134206 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores3.core.data 7978718942 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores4.core.inst 101261214 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores4.core.data 7040611423 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores5.core.inst 96025399 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores5.core.data 6929766106 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores6.core.inst 72983607 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores6.core.data 8012458882 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores7.core.inst 176061403 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadTotalLat::processor.cores7.core.data 7021152289 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl0.requestorWriteTotalLat::writebacks 7909200002438 # Per-requestor write total memory access latency (Tick)
board.memory.mem_ctrl0.requestorReadAvgLat::cache_hierarchy.l1dcaches0.prefetcher 52672.83 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::cache_hierarchy.l1dcaches1.prefetcher 52088.91 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::cache_hierarchy.l1dcaches2.prefetcher 51874.68 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::cache_hierarchy.l1dcaches3.prefetcher 51521.30 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::cache_hierarchy.l1dcaches4.prefetcher 53224.58 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::cache_hierarchy.l1dcaches5.prefetcher 52534.53 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::cache_hierarchy.l1dcaches6.prefetcher 51544.16 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::cache_hierarchy.l1dcaches7.prefetcher 52994.62 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::cache_hierarchy.l2cache.prefetcher 47067.94 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores0.core.inst 37840.58 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores0.core.data 43375.78 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores1.core.inst 30525.20 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores1.core.data 43583.89 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores2.core.inst 37103.33 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores2.core.data 44204.90 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores3.core.inst 33693.22 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores3.core.data 43777.54 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores4.core.inst 35972.01 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores4.core.data 44426.99 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores5.core.inst 39795.03 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores5.core.data 44490.02 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores6.core.inst 33977.47 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores6.core.data 44119.77 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores7.core.inst 39081.33 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorReadAvgLat::processor.cores7.core.data 44137.65 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.requestorWriteAvgLat::writebacks 3453981.63 # Per-requestor write average memory access latency ((Tick/Count))
board.memory.mem_ctrl0.dram.bytesRead::cache_hierarchy.l1dcaches0.prefetcher 26242496 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::cache_hierarchy.l1dcaches1.prefetcher 30428480 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::cache_hierarchy.l1dcaches2.prefetcher 30973952 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::cache_hierarchy.l1dcaches3.prefetcher 31316224 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::cache_hierarchy.l1dcaches4.prefetcher 29153728 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::cache_hierarchy.l1dcaches5.prefetcher 28558336 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::cache_hierarchy.l1dcaches6.prefetcher 31493120 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::cache_hierarchy.l1dcaches7.prefetcher 29107840 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::cache_hierarchy.l2cache.prefetcher 40441536 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores0.core.inst 435840 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores0.core.data 11209536 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores1.core.inst 734400 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores1.core.data 11130240 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores2.core.inst 174656 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores2.core.data 11540608 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores3.core.inst 100928 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores3.core.data 11664384 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores4.core.inst 180160 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores4.core.data 10142464 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores5.core.inst 154432 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores5.core.data 9968640 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores6.core.inst 137472 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores6.core.data 11622848 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores7.core.inst 288320 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::processor.cores7.core.data 10180736 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesRead::total 367381376 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesInstRead::processor.cores0.core.inst 435840 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesInstRead::processor.cores1.core.inst 734400 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesInstRead::processor.cores2.core.inst 174656 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesInstRead::processor.cores3.core.inst 100928 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesInstRead::processor.cores4.core.inst 180160 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesInstRead::processor.cores5.core.inst 154432 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesInstRead::processor.cores6.core.inst 137472 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesInstRead::processor.cores7.core.inst 288320 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesInstRead::total 2206208 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl0.dram.bytesWritten::writebacks 146552256 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl0.dram.bytesWritten::total 146552256 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl0.dram.numReads::cache_hierarchy.l1dcaches0.prefetcher 410039 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::cache_hierarchy.l1dcaches1.prefetcher 475445 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::cache_hierarchy.l1dcaches2.prefetcher 483968 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::cache_hierarchy.l1dcaches3.prefetcher 489316 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::cache_hierarchy.l1dcaches4.prefetcher 455527 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::cache_hierarchy.l1dcaches5.prefetcher 446224 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::cache_hierarchy.l1dcaches6.prefetcher 492080 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::cache_hierarchy.l1dcaches7.prefetcher 454810 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::cache_hierarchy.l2cache.prefetcher 631899 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores0.core.inst 6810 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores0.core.data 175149 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores1.core.inst 11475 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores1.core.data 173910 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores2.core.inst 2729 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores2.core.data 180322 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores3.core.inst 1577 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores3.core.data 182256 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores4.core.inst 2815 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores4.core.data 158476 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores5.core.inst 2413 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores5.core.data 155760 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores6.core.inst 2148 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores6.core.data 181607 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores7.core.inst 4505 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::processor.cores7.core.data 159074 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numReads::total 5740334 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numWrites::writebacks 2289879 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.numWrites::total 2289879 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl0.dram.bwRead::cache_hierarchy.l1dcaches0.prefetcher 188015276 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::cache_hierarchy.l1dcaches1.prefetcher 218005904 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::cache_hierarchy.l1dcaches2.prefetcher 221913957 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::cache_hierarchy.l1dcaches3.prefetcher 224366177 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::cache_hierarchy.l1dcaches4.prefetcher 208872899 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::cache_hierarchy.l1dcaches5.prefetcher 204607192 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::cache_hierarchy.l1dcaches6.prefetcher 225633554 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::cache_hierarchy.l1dcaches7.prefetcher 208544133 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::cache_hierarchy.l2cache.prefetcher 289744792 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores0.core.inst 3122591 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores0.core.data 80311111 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores1.core.inst 5261634 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores1.core.data 79742992 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores2.core.inst 1251329 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores2.core.data 82683088 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores3.core.inst 723102 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores3.core.data 83569885 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores4.core.inst 1290763 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores4.core.data 72666036 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores5.core.inst 1106433 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores5.core.data 71420668 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores6.core.inst 984923 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores6.core.data 83272299 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores7.core.inst 2065679 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::processor.cores7.core.data 72940237 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwRead::total 2632116653 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwInstRead::processor.cores0.core.inst 3122591 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwInstRead::processor.cores1.core.inst 5261634 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwInstRead::processor.cores2.core.inst 1251329 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwInstRead::processor.cores3.core.inst 723102 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwInstRead::processor.cores4.core.inst 1290763 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwInstRead::processor.cores5.core.inst 1106433 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwInstRead::processor.cores6.core.inst 984923 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwInstRead::processor.cores7.core.inst 2065679 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwInstRead::total 15806454 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwWrite::writebacks 1049978738 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwWrite::total 1049978738 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::writebacks 1049978738 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::cache_hierarchy.l1dcaches0.prefetcher 188015276 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::cache_hierarchy.l1dcaches1.prefetcher 218005904 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::cache_hierarchy.l1dcaches2.prefetcher 221913957 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::cache_hierarchy.l1dcaches3.prefetcher 224366177 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::cache_hierarchy.l1dcaches4.prefetcher 208872899 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::cache_hierarchy.l1dcaches5.prefetcher 204607192 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::cache_hierarchy.l1dcaches6.prefetcher 225633554 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::cache_hierarchy.l1dcaches7.prefetcher 208544133 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::cache_hierarchy.l2cache.prefetcher 289744792 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores0.core.inst 3122591 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores0.core.data 80311111 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores1.core.inst 5261634 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores1.core.data 79742992 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores2.core.inst 1251329 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores2.core.data 82683088 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores3.core.inst 723102 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores3.core.data 83569885 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores4.core.inst 1290763 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores4.core.data 72666036 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores5.core.inst 1106433 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores5.core.data 71420668 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores6.core.inst 984923 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores6.core.data 83272299 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores7.core.inst 2065679 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::processor.cores7.core.data 72940237 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.bwTotal::total 3682095391 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl0.dram.readBursts 5733610 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl0.dram.writeBursts 2289822 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::0 183321 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::1 181889 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::2 190402 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::3 174284 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::4 170951 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::5 180727 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::6 179710 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::7 186537 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::8 193532 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::9 201181 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::10 175481 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::11 184628 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::12 181906 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::13 182421 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::14 178189 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::15 183225 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::16 172378 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::17 186891 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::18 175814 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::19 172567 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::20 173390 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::21 179335 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::22 179582 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::23 176041 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::24 172934 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::25 177527 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::26 173370 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::27 174911 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::28 172102 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::29 170699 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::30 172452 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankRdBursts::31 175233 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::0 73110 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::1 72849 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::2 76345 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::3 71550 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::4 71011 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::5 74757 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::6 73517 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::7 76815 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::8 78603 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::9 84915 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::10 69978 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::11 71032 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::12 69662 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::13 76783 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::14 72092 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::15 71856 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::16 68473 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::17 74637 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::18 66523 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::19 68740 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::20 66102 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::21 70258 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::22 71282 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::23 68405 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::24 67012 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::25 70642 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::26 69162 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::27 67670 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::28 66484 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::29 69402 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::30 68839 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.perBankWrBursts::31 71316 # Per bank write bursts (Count)
board.memory.mem_ctrl0.dram.totQLat 184622236442 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl0.dram.totBusLat 19104388520 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl0.dram.totMemAccLat 284914542562 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl0.dram.avgQLat 32200.00 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgBusLat 3332.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.avgMemAccLat 49692.00 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl0.dram.readRowHits 4009932 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl0.dram.writeRowHits 1561002 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl0.dram.readRowHitRate 69.94 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl0.dram.writeRowHitRate 68.17 # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl0.dram.bytesPerActivate::samples 2452505 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::mean 209.378502 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::gmean 142.440331 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::stdev 221.015939 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::0-127 1002662 40.88% 40.88% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::128-255 768990 31.36% 72.24% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::256-383 295629 12.05% 84.29% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::384-511 142539 5.81% 90.10% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::512-639 74871 3.05% 93.16% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::640-767 42590 1.74% 94.89% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::768-895 29661 1.21% 96.10% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::896-1023 20374 0.83% 96.93% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::1024-1151 75189 3.07% 100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.bytesPerActivate::total 2452505 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl0.dram.dramBytesRead 366951040 # Total bytes read (Byte)
board.memory.mem_ctrl0.dram.dramBytesWritten 146548608 # Total bytes written (Byte)
board.memory.mem_ctrl0.dram.avgRdBW 2629.033496 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.avgWrBW 1049.952602 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl0.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl0.dram.busUtil 19.15 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl0.dram.busUtilRead 13.69 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl0.dram.busUtilWrite 5.47 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl0.dram.pageHitRate 69.43 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl0.dram.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl0.dram.rank0.actEnergy 1989358338.240012 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preEnergy 3511979851.917566 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.readEnergy 8032441561.670578 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.writeEnergy 2795186478.000010 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.refreshEnergy 12116062437.680319 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actBackEnergy 63757945704.369377 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.preBackEnergy 1542691364.524927 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.totalEnergy 93745665736.396881 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank0.averagePower 671.644084 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::IDLE 4223160986 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::REF 6274450000 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT 129080603194 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.actEnergy 1835023776.767994 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preEnergy 3239522744.371163 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.readEnergy 7694474842.454635 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.writeEnergy 2606631850.031994 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.refreshEnergy 12116062437.680319 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actBackEnergy 63608617601.513008 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.preBackEnergy 1645786525.958526 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.totalEnergy 92746119778.771164 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl0.dram.rank1.averagePower 664.482803 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl0.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::IDLE 4537765630 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::REF 6274450000 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT 128766015470 # Time in different power states (Tick)
board.memory.mem_ctrl0.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl0.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.avgPriority_writebacks::samples 2291043.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_cache_hierarchy.l1dcaches0.prefetcher::samples 413559.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_cache_hierarchy.l1dcaches1.prefetcher::samples 479916.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_cache_hierarchy.l1dcaches2.prefetcher::samples 487554.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_cache_hierarchy.l1dcaches3.prefetcher::samples 493493.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_cache_hierarchy.l1dcaches4.prefetcher::samples 459122.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_cache_hierarchy.l1dcaches5.prefetcher::samples 449773.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_cache_hierarchy.l1dcaches6.prefetcher::samples 496402.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_cache_hierarchy.l1dcaches7.prefetcher::samples 458552.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_cache_hierarchy.l2cache.prefetcher::samples 637430.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores0.core.inst::samples 6716.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores0.core.data::samples 169935.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores1.core.inst::samples 11637.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores1.core.data::samples 167898.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores2.core.inst::samples 2667.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores2.core.data::samples 175456.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores3.core.inst::samples 1525.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores3.core.data::samples 176847.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores4.core.inst::samples 2823.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores4.core.data::samples 153902.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores5.core.inst::samples 2379.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores5.core.data::samples 150989.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores6.core.inst::samples 2132.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores6.core.data::samples 176478.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores7.core.inst::samples 4328.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.avgPriority_processor.cores7.core.data::samples 154447.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl1.priorityMinLatency 0.000000017492 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl1.priorityMaxLatency 0.001196091652 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl1.numReadWriteTurnArounds 135356 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl1.numWriteReadTurnArounds 135356 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl1.numStayReadState 11093072 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl1.numStayWriteState 2162852 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl1.readReqs 5742700 # Number of read requests accepted (Count)
board.memory.mem_ctrl1.writeReqs 2291043 # Number of write requests accepted (Count)
board.memory.mem_ctrl1.readBursts 5742700 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl1.writeBursts 2291043 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl1.servicedByWrQ 6740 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl1.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl1.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl1.avgRdQLen 3.46 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.avgWrQLen 57.29 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl1.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl1.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl1.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.readPktSize::6 5742700 # Read request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.writePktSize::6 2291043 # Write request sizes (log2) (Count)
board.memory.mem_ctrl1.rdQLenPdf::0 1021450 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::1 921859 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::2 804743 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::3 688769 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::4 579648 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::5 476598 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::6 383576 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::7 295018 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::8 212519 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::9 144782 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::10 92238 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::11 55054 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::12 30754 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::13 15952 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::14 7693 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::15 3353 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::16 1333 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::17 471 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::18 129 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::19 21 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::0 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::1 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::2 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::3 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::4 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::5 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::6 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::7 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::8 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::9 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::10 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::11 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::12 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::13 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::14 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::15 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::16 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::17 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::18 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::19 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::20 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::21 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::22 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::23 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::24 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::25 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::26 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::27 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::28 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::29 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::30 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::31 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::32 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::33 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::34 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::35 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::36 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::37 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::38 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::39 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::40 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::41 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::42 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::43 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::44 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::45 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::46 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::47 31323 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::48 36531 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::49 65025 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::50 88457 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::51 106813 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::52 120400 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::53 131396 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::54 141097 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::55 148560 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::56 152809 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::57 156909 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::58 163497 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::59 156792 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::60 148366 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::61 146505 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::62 145362 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::63 144170 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::64 142980 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::65 16176 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::66 10571 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::67 7575 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::68 5686 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::69 4290 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::70 3247 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::71 2631 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::72 2191 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::73 1800 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::74 1391 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::75 1214 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::76 980 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::77 802 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::78 706 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::79 617 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::80 500 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::81 448 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::82 390 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::83 335 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::84 287 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::85 223 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::86 206 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::87 186 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::88 165 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::89 163 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::90 128 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::91 131 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::92 123 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::93 106 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::94 100 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::95 74 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::96 68 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::97 67 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::98 47 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::99 50 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::100 56 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::101 55 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::102 42 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::103 33 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::104 32 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::105 23 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::106 28 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::107 17 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::108 21 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::109 12 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::110 4 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::111 5 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::112 2 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl1.rdPerTurnAround::samples 135356 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.rdPerTurnAround::mean 42.392690 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.rdPerTurnAround::gmean 33.628379 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.rdPerTurnAround::stdev 65.184733 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.rdPerTurnAround::0-511 135285 99.95% 99.95% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.rdPerTurnAround::512-1023 49 0.04% 99.98% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.rdPerTurnAround::1024-1535 11 0.01% 99.99% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.rdPerTurnAround::1536-2047 4 0.00% 99.99% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.rdPerTurnAround::2048-2559 2 0.00% 100.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.rdPerTurnAround::2560-3071 1 0.00% 100.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.rdPerTurnAround::3072-3583 2 0.00% 100.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.rdPerTurnAround::3584-4095 1 0.00% 100.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.rdPerTurnAround::17408-17919 1 0.00% 100.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.rdPerTurnAround::total 135356 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl1.wrPerTurnAround::samples 135356 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::mean 16.925648 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::gmean 16.843375 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::stdev 1.788713 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::16 96837 71.54% 71.54% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::17 3016 2.23% 73.77% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::18 15482 11.44% 85.21% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::19 7842 5.79% 91.00% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::20 4448 3.29% 94.29% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::21 2675 1.98% 96.26% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::22 1884 1.39% 97.66% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::23 1347 1.00% 98.65% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::24 1199 0.89% 99.54% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::25 336 0.25% 99.79% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::26 121 0.09% 99.88% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::27 81 0.06% 99.93% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::28 42 0.03% 99.97% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::29 16 0.01% 99.98% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::30 14 0.01% 99.99% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::31 7 0.01% 99.99% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::32 4 0.00% 100.00% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::33 2 0.00% 100.00% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::34 1 0.00% 100.00% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::35 1 0.00% 100.00% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::37 1 0.00% 100.00% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.wrPerTurnAround::total 135356 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl1.bytesReadWrQ 431360 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl1.bytesReadSys 367532800 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl1.bytesWrittenSys 146626752 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl1.avgRdBWSys 2633201535.38703251 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.avgWrBWSys 1050512467.17357922 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl1.totGap 139571606500 # Total gap between requests (Tick)
board.memory.mem_ctrl1.avgGap 17373.17 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl1.requestorReadBytes::cache_hierarchy.l1dcaches0.prefetcher 26467776 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::cache_hierarchy.l1dcaches1.prefetcher 30714624 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::cache_hierarchy.l1dcaches2.prefetcher 31203456 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::cache_hierarchy.l1dcaches3.prefetcher 31583552 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::cache_hierarchy.l1dcaches4.prefetcher 29383808 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::cache_hierarchy.l1dcaches5.prefetcher 28785472 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::cache_hierarchy.l1dcaches6.prefetcher 31769728 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::cache_hierarchy.l1dcaches7.prefetcher 29347328 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::cache_hierarchy.l2cache.prefetcher 40795520 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores0.core.inst 429824 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores0.core.data 10875840 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores1.core.inst 744768 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores1.core.data 10745472 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores2.core.inst 170688 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores2.core.data 11229184 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores3.core.inst 97600 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores3.core.data 11318208 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores4.core.inst 180672 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores4.core.data 9849728 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores5.core.inst 152256 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores5.core.data 9663296 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores6.core.inst 136448 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores6.core.data 11294592 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores7.core.inst 276992 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorReadBytes::processor.cores7.core.data 9884608 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl1.requestorWriteBytes::writebacks 146623232 # Per-requestor bytes write to memory (Byte)
board.memory.mem_ctrl1.requestorReadRate::cache_hierarchy.l1dcaches0.prefetcher 189629302.205082237720 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::cache_hierarchy.l1dcaches1.prefetcher 220055992.487297475338 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::cache_hierarchy.l1dcaches2.prefetcher 223558246.362179696560 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::cache_hierarchy.l1dcaches3.prefetcher 226281457.381153970957 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::cache_hierarchy.l1dcaches4.prefetcher 210521314.944183945656 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::cache_hierarchy.l1dcaches5.prefetcher 206234515.850668132305 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::cache_hierarchy.l1dcaches6.prefetcher 227615321.811899244785 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::cache_hierarchy.l1dcaches7.prefetcher 210259952.714715123177 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::cache_hierarchy.l2cache.prefetcher 292280922.684757351875 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores0.core.inst 3079489.005460726097 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores0.core.data 77920334.148744568229 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores1.core.inst 5335916.253208229318 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores1.core.data 76986308.076063871384 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores2.core.inst 1222900.115777807776 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores2.core.data 80451879.532775029540 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores3.core.inst 699258.596385885496 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores3.core.data 81089695.078724384308 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores4.core.inst 1294430.831211380195 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores4.core.data 70568719.017036423087 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores5.core.inst 1090843.410361981485 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores5.core.data 69233020.465382605791 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores6.core.inst 977586.444258824922 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores6.core.data 80920497.424910366535 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores7.core.inst 1984518.823054499924 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadRate::processor.cores7.core.data 70818617.990826800466 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorWriteRate::writebacks 1050487248.011086583138 # Per-requestor bytes write to memory rate ((Byte/Second))
board.memory.mem_ctrl1.requestorReadAccesses::cache_hierarchy.l1dcaches0.prefetcher 414087 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::cache_hierarchy.l1dcaches1.prefetcher 480519 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::cache_hierarchy.l1dcaches2.prefetcher 488232 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::cache_hierarchy.l1dcaches3.prefetcher 494153 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::cache_hierarchy.l1dcaches4.prefetcher 459660 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::cache_hierarchy.l1dcaches5.prefetcher 450367 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::cache_hierarchy.l1dcaches6.prefetcher 496977 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::cache_hierarchy.l1dcaches7.prefetcher 459131 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::cache_hierarchy.l2cache.prefetcher 638185 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores0.core.inst 6716 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores0.core.data 170110 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores1.core.inst 11637 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores1.core.data 168074 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores2.core.inst 2667 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores2.core.data 175588 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores3.core.inst 1525 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores3.core.data 177046 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores4.core.inst 2823 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores4.core.data 154034 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores5.core.inst 2379 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores5.core.data 151118 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores6.core.inst 2132 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores6.core.data 176630 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores7.core.inst 4328 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadAccesses::processor.cores7.core.data 154582 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorWriteAccesses::writebacks 2291043 # Per-requestor write serviced memory accesses (Count)
board.memory.mem_ctrl1.requestorReadTotalLat::cache_hierarchy.l1dcaches0.prefetcher 21866866689 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::cache_hierarchy.l1dcaches1.prefetcher 25078163809 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::cache_hierarchy.l1dcaches2.prefetcher 25417822654 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::cache_hierarchy.l1dcaches3.prefetcher 25538600120 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::cache_hierarchy.l1dcaches4.prefetcher 24570504173 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::cache_hierarchy.l1dcaches5.prefetcher 23855720507 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::cache_hierarchy.l1dcaches6.prefetcher 25767561413 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::cache_hierarchy.l1dcaches7.prefetcher 24438117615 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::cache_hierarchy.l2cache.prefetcher 30464902735 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores0.core.inst 253032200 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores0.core.data 7356776245 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores1.core.inst 350743972 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores1.core.data 7292657397 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores2.core.inst 99073916 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores2.core.data 7770040518 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores3.core.inst 52013731 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores3.core.data 7731308057 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores4.core.inst 103052005 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores4.core.data 6824019941 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores5.core.inst 90530861 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores5.core.data 6683502333 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores6.core.inst 71800423 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores6.core.data 7778601778 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores7.core.inst 168449696 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadTotalLat::processor.cores7.core.data 6767403498 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl1.requestorWriteTotalLat::writebacks 7907679602471 # Per-requestor write total memory access latency (Tick)
board.memory.mem_ctrl1.requestorReadAvgLat::cache_hierarchy.l1dcaches0.prefetcher 52807.42 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::cache_hierarchy.l1dcaches1.prefetcher 52189.74 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::cache_hierarchy.l1dcaches2.prefetcher 52060.95 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::cache_hierarchy.l1dcaches3.prefetcher 51681.56 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::cache_hierarchy.l1dcaches4.prefetcher 53453.65 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::cache_hierarchy.l1dcaches5.prefetcher 52969.51 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::cache_hierarchy.l1dcaches6.prefetcher 51848.60 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::cache_hierarchy.l1dcaches7.prefetcher 53226.90 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::cache_hierarchy.l2cache.prefetcher 47736.79 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores0.core.inst 37676.03 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores0.core.data 43247.17 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores1.core.inst 30140.41 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores1.core.data 43389.56 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores2.core.inst 37148.07 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores2.core.data 44251.55 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores3.core.inst 34107.36 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores3.core.data 43668.36 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores4.core.inst 36504.43 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores4.core.data 44302.04 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores5.core.inst 38054.17 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores5.core.data 44227.04 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores6.core.inst 33677.50 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores6.core.data 44038.96 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores7.core.inst 38920.91 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorReadAvgLat::processor.cores7.core.data 43778.73 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.requestorWriteAvgLat::writebacks 3451563.15 # Per-requestor write average memory access latency ((Tick/Count))
board.memory.mem_ctrl1.dram.bytesRead::cache_hierarchy.l1dcaches0.prefetcher 26501568 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::cache_hierarchy.l1dcaches1.prefetcher 30753216 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::cache_hierarchy.l1dcaches2.prefetcher 31246848 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::cache_hierarchy.l1dcaches3.prefetcher 31625792 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::cache_hierarchy.l1dcaches4.prefetcher 29418240 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::cache_hierarchy.l1dcaches5.prefetcher 28823488 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::cache_hierarchy.l1dcaches6.prefetcher 31806528 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::cache_hierarchy.l1dcaches7.prefetcher 29384384 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::cache_hierarchy.l2cache.prefetcher 40843840 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores0.core.inst 429824 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores0.core.data 10887040 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores1.core.inst 744768 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores1.core.data 10756736 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores2.core.inst 170688 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores2.core.data 11237696 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores3.core.inst 97600 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores3.core.data 11330944 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores4.core.inst 180672 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores4.core.data 9858176 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores5.core.inst 152256 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores5.core.data 9671552 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores6.core.inst 136448 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores6.core.data 11304320 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores7.core.inst 276992 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::processor.cores7.core.data 9893248 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesRead::total 367532864 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::processor.cores0.core.inst 429824 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::processor.cores1.core.inst 744768 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::processor.cores2.core.inst 170688 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::processor.cores3.core.inst 97600 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::processor.cores4.core.inst 180672 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::processor.cores5.core.inst 152256 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::processor.cores6.core.inst 136448 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::processor.cores7.core.inst 276992 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesInstRead::total 2189248 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl1.dram.bytesWritten::writebacks 146626752 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl1.dram.bytesWritten::total 146626752 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl1.dram.numReads::cache_hierarchy.l1dcaches0.prefetcher 414087 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::cache_hierarchy.l1dcaches1.prefetcher 480519 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::cache_hierarchy.l1dcaches2.prefetcher 488232 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::cache_hierarchy.l1dcaches3.prefetcher 494153 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::cache_hierarchy.l1dcaches4.prefetcher 459660 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::cache_hierarchy.l1dcaches5.prefetcher 450367 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::cache_hierarchy.l1dcaches6.prefetcher 496977 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::cache_hierarchy.l1dcaches7.prefetcher 459131 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::cache_hierarchy.l2cache.prefetcher 638185 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores0.core.inst 6716 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores0.core.data 170110 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores1.core.inst 11637 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores1.core.data 168074 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores2.core.inst 2667 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores2.core.data 175589 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores3.core.inst 1525 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores3.core.data 177046 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores4.core.inst 2823 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores4.core.data 154034 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores5.core.inst 2379 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores5.core.data 151118 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores6.core.inst 2132 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores6.core.data 176630 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores7.core.inst 4328 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::processor.cores7.core.data 154582 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numReads::total 5742701 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numWrites::writebacks 2291043 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.numWrites::total 2291043 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl1.dram.bwRead::cache_hierarchy.l1dcaches0.prefetcher 189871406 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::cache_hierarchy.l1dcaches1.prefetcher 220332486 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::cache_hierarchy.l1dcaches2.prefetcher 223869130 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::cache_hierarchy.l1dcaches3.prefetcher 226584087 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::cache_hierarchy.l1dcaches4.prefetcher 210768004 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::cache_hierarchy.l1dcaches5.prefetcher 206506883 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::cache_hierarchy.l1dcaches6.prefetcher 227878977 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::cache_hierarchy.l1dcaches7.prefetcher 210525442 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::cache_hierarchy.l2cache.prefetcher 292627113 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores0.core.inst 3079489 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores0.core.data 78000577 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores1.core.inst 5335916 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores1.core.data 77067009 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores2.core.inst 1222900 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores2.core.data 80512864 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores3.core.inst 699259 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores3.core.data 81180943 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores4.core.inst 1294431 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores4.core.data 70629245 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores5.core.inst 1090843 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores5.core.data 69292171 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores6.core.inst 977586 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores6.core.data 80990194 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores7.core.inst 1984519 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::processor.cores7.core.data 70880520 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwRead::total 2633201994 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::processor.cores0.core.inst 3079489 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::processor.cores1.core.inst 5335916 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::processor.cores2.core.inst 1222900 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::processor.cores3.core.inst 699259 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::processor.cores4.core.inst 1294431 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::processor.cores5.core.inst 1090843 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::processor.cores6.core.inst 977586 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::processor.cores7.core.inst 1984519 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwInstRead::total 15684943 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwWrite::writebacks 1050512467 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwWrite::total 1050512467 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::writebacks 1050512467 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::cache_hierarchy.l1dcaches0.prefetcher 189871406 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::cache_hierarchy.l1dcaches1.prefetcher 220332486 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::cache_hierarchy.l1dcaches2.prefetcher 223869130 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::cache_hierarchy.l1dcaches3.prefetcher 226584087 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::cache_hierarchy.l1dcaches4.prefetcher 210768004 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::cache_hierarchy.l1dcaches5.prefetcher 206506883 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::cache_hierarchy.l1dcaches6.prefetcher 227878977 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::cache_hierarchy.l1dcaches7.prefetcher 210525442 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::cache_hierarchy.l2cache.prefetcher 292627113 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores0.core.inst 3079489 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores0.core.data 78000577 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores1.core.inst 5335916 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores1.core.data 77067009 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores2.core.inst 1222900 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores2.core.data 80512864 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores3.core.inst 699259 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores3.core.data 81180943 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores4.core.inst 1294431 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores4.core.data 70629245 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores5.core.inst 1090843 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores5.core.data 69292171 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores6.core.inst 977586 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores6.core.data 80990194 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores7.core.inst 1984519 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::processor.cores7.core.data 70880520 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.bwTotal::total 3683714461 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl1.dram.readBursts 5735960 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl1.dram.writeBursts 2290988 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::0 183320 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::1 182359 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::2 190796 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::3 174459 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::4 171199 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::5 180805 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::6 179892 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::7 186403 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::8 193705 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::9 200724 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::10 175320 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::11 184949 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::12 181923 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::13 182740 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::14 177952 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::15 183491 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::16 172673 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::17 187019 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::18 175359 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::19 173281 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::20 173658 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::21 179021 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::22 179859 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::23 175463 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::24 173002 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::25 177721 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::26 173306 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::27 175140 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::28 172165 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::29 170932 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::30 171833 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankRdBursts::31 175491 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::0 73059 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::1 72629 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::2 76518 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::3 71509 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::4 71114 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::5 74760 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::6 73362 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::7 76736 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::8 78557 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::9 84734 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::10 70014 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::11 71088 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::12 69659 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::13 77046 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::14 72069 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::15 71927 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::16 68513 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::17 74722 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::18 66630 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::19 69350 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::20 66226 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::21 69957 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::22 71870 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::23 68420 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::24 66902 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::25 70697 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::26 69019 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::27 67748 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::28 66499 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::29 69492 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::30 68726 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.perBankWrBursts::31 71436 # Per bank write bursts (Count)
board.memory.mem_ctrl1.dram.totQLat 186057853966 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl1.dram.totBusLat 19112218720 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl1.dram.totMemAccLat 286391266286 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl1.dram.avgQLat 32437.09 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgBusLat 3332.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.avgMemAccLat 49929.09 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl1.dram.readRowHits 4031906 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl1.dram.writeRowHits 1562949 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl1.dram.readRowHitRate 70.29 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl1.dram.writeRowHitRate 68.22 # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl1.dram.bytesPerActivate::samples 2432099 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::mean 211.227270 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::gmean 143.998396 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::stdev 221.543616 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::0-127 976591 40.15% 40.15% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::128-255 774402 31.84% 72.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::256-383 295541 12.15% 84.15% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::384-511 142721 5.87% 90.02% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::512-639 74885 3.08% 93.09% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::640-767 42496 1.75% 94.84% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::768-895 29851 1.23% 96.07% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::896-1023 20072 0.83% 96.89% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::1024-1151 75540 3.11% 100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.bytesPerActivate::total 2432099 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl1.dram.dramBytesRead 367101440 # Total bytes read (Byte)
board.memory.mem_ctrl1.dram.dramBytesWritten 146623232 # Total bytes written (Byte)
board.memory.mem_ctrl1.dram.avgRdBW 2630.111042 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.avgWrBW 1050.487248 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl1.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl1.dram.busUtil 19.16 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl1.dram.busUtilRead 13.69 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl1.dram.busUtilWrite 5.47 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl1.dram.pageHitRate 69.70 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl1.dram.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl1.dram.rank0.actEnergy 1972490568.048011 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preEnergy 3482204502.823161 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.readEnergy 8037011237.068947 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.writeEnergy 2794964726.736001 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.refreshEnergy 12116062437.680319 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actBackEnergy 63762396123.489784 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.preBackEnergy 1539376738.905725 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.totalEnergy 93704506334.744934 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank0.averagePower 671.349196 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::IDLE 4214317020 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::REF 6274450000 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT 129088704480 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.actEnergy 1820072479.679994 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preEnergy 3213127954.511950 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.readEnergy 7696383902.525015 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.writeEnergy 2609604260.592002 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.refreshEnergy 12116062437.680319 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actBackEnergy 63563129591.997459 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.preBackEnergy 1677145097.510520 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.totalEnergy 92695525724.490128 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl1.dram.rank1.averagePower 664.120320 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl1.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::IDLE 4633619866 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::REF 6274450000 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT 128670025634 # Time in different power states (Tick)
board.memory.mem_ctrl1.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl1.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores0.core.numCycles 279152890 # Number of cpu cycles simulated (Cycle)
board.processor.cores0.core.cpi 2.561954 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores0.core.ipc 0.390327 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores0.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores0.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores0.core.commitStats0.numInsts 108960916 # Number of instructions committed (thread level) (Count)
board.processor.cores0.core.commitStats0.numOps 210091395 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores0.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores0.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores0.core.commitStats0.cpi 2.561954 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores0.core.commitStats0.ipc 0.390327 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores0.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.cores0.core.commitStats0.numFpInsts 112234446 # Number of float instructions (Count)
board.processor.cores0.core.commitStats0.numIntInsts 135476240 # Number of integer instructions (Count)
board.processor.cores0.core.commitStats0.numLoadInsts 47228348 # Number of load instructions (Count)
board.processor.cores0.core.commitStats0.numStoreInsts 9918001 # Number of store instructions (Count)
board.processor.cores0.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores0.core.commitStats0.committedInstType::No_OpClass 1052180 0.50% 0.50% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::IntAlu 84504413 40.22% 40.72% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::IntMult 153653 0.07% 40.80% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::IntDiv 665 0.00% 40.80% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::FloatAdd 8634527 4.11% 44.91% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::FloatCmp 0 0.00% 44.91% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::FloatCvt 0 0.00% 44.91% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::FloatMult 0 0.00% 44.91% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 44.91% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::FloatDiv 0 0.00% 44.91% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::FloatMisc 0 0.00% 44.91% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 44.91% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdAdd 398468 0.19% 45.10% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 45.10% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdAlu 6852340 3.26% 48.36% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdCmp 0 0.00% 48.36% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdCvt 391524 0.19% 48.54% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdMisc 2166429 1.03% 49.58% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdMult 0 0.00% 49.58% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 49.58% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 49.58% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdShift 671770 0.32% 49.90% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 49.90% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdDiv 0 0.00% 49.90% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 49.90% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdFloatAdd 20725865 9.87% 59.76% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdFloatAlu 1408052 0.67% 60.43% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdFloatCmp 1197617 0.57% 61.00% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdFloatCvt 2515567 1.20% 62.20% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdFloatDiv 479054 0.23% 62.43% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 62.43% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdFloatMult 21755335 10.36% 72.78% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 72.78% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 72.78% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdFloatSqrt 37587 0.02% 72.80% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 72.80% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 72.80% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 72.80% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 72.80% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 72.80% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdAes 0 0.00% 72.80% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 72.80% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 72.80% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 72.80% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 72.80% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 72.80% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 72.80% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 72.80% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 72.80% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::Matrix 0 0.00% 72.80% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::MatrixMov 0 0.00% 72.80% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::MatrixOP 0 0.00% 72.80% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::MemRead 16605749 7.90% 80.70% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::MemWrite 2663559 1.27% 81.97% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::FloatMemRead 30622599 14.58% 96.55% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::FloatMemWrite 7254442 3.45% 100.00% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedInstType::total 210091395 # Class of committed instruction. (Count)
board.processor.cores0.core.commitStats0.committedControl::IsControl 13287952 # Class of control type instructions committed (Count)
board.processor.cores0.core.commitStats0.committedControl::IsDirectControl 12034139 # Class of control type instructions committed (Count)
board.processor.cores0.core.commitStats0.committedControl::IsIndirectControl 1253813 # Class of control type instructions committed (Count)
board.processor.cores0.core.commitStats0.committedControl::IsCondControl 11210882 # Class of control type instructions committed (Count)
board.processor.cores0.core.commitStats0.committedControl::IsUncondControl 2077070 # Class of control type instructions committed (Count)
board.processor.cores0.core.commitStats0.committedControl::IsCall 557764 # Class of control type instructions committed (Count)
board.processor.cores0.core.commitStats0.committedControl::IsReturn 557764 # Class of control type instructions committed (Count)
board.processor.cores0.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.cores0.core.exec_context.thread_0.numCallsReturns 1115528 # Number of times a function call or return occured (Count)
board.processor.cores0.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.cores0.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.cores0.core.exec_context.thread_0.numBusyCycles 279152890 # Number of busy cycles (Cycle)
board.processor.cores0.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.cores0.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.cores0.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.cores0.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores0.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.cores0.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.cores0.core.executeStats0.numStoreInsts 57146349 # Number of stores executed (Count)
board.processor.cores0.core.executeStats0.instRate 0 # Inst execution rate ((Count/Cycle))
board.processor.cores0.core.executeStats0.numFpAluAccesses 112234446 # Number of float alu accesses (Count)
board.processor.cores0.core.executeStats0.numFpRegReads 184536874 # Number of times the floating registers were read (Count)
board.processor.cores0.core.executeStats0.numFpRegWrites 103063570 # Number of times the floating registers were written (Count)
board.processor.cores0.core.executeStats0.numIntAluAccesses 135476240 # Number of integer alu accesses (Count)
board.processor.cores0.core.executeStats0.numIntRegReads 169432081 # Number of times the integer registers were read (Count)
board.processor.cores0.core.executeStats0.numIntRegWrites 70951610 # Number of times the integer registers were written (Count)
board.processor.cores0.core.executeStats0.numMemRefs 57146349 # Number of memory refs (Count)
board.processor.cores0.core.executeStats0.numMiscRegReads 87314989 # Number of times the Misc registers were read (Count)
board.processor.cores0.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores0.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores0.core.fetchStats0.numInsts 108960917 # Number of instructions fetched (thread level) (Count)
board.processor.cores0.core.fetchStats0.numOps 210091396 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores0.core.fetchStats0.fetchRate 0.390327 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores0.core.fetchStats0.numBranches 13287952 # Number of branches fetched (Count)
board.processor.cores0.core.fetchStats0.branchRate 0.047601 # Number of branch fetches per cycle (Ratio)
board.processor.cores0.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores0.core.interrupts.clk_domain.clock 8000 # Clock period in ticks (Tick)
board.processor.cores0.core.mmu.dtb.rdAccesses 48360128 # TLB accesses on read requests (Count)
board.processor.cores0.core.mmu.dtb.wrAccesses 9984441 # TLB accesses on write requests (Count)
board.processor.cores0.core.mmu.dtb.rdMisses 29654 # TLB misses on read requests (Count)
board.processor.cores0.core.mmu.dtb.wrMisses 6843 # TLB misses on write requests (Count)
board.processor.cores0.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores0.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.cores0.core.mmu.itb.wrAccesses 156542706 # TLB accesses on write requests (Count)
board.processor.cores0.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores0.core.mmu.itb.wrMisses 716 # TLB misses on write requests (Count)
board.processor.cores0.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores0.core.power_state.pwrStateResidencyTicks::ON 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores0.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.cores0.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.cores0.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.cores0.core.workload.numSyscalls 1281 # Number of system calls (Count)
board.processor.cores1.core.numCycles 279152814 # Number of cpu cycles simulated (Cycle)
board.processor.cores1.core.cpi 2.583826 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores1.core.ipc 0.387023 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores1.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores1.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores1.core.commitStats0.numInsts 108038539 # Number of instructions committed (thread level) (Count)
board.processor.cores1.core.commitStats0.numOps 207370290 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores1.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores1.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores1.core.commitStats0.cpi 2.583826 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores1.core.commitStats0.ipc 0.387023 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores1.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.cores1.core.commitStats0.numFpInsts 125312407 # Number of float instructions (Count)
board.processor.cores1.core.commitStats0.numIntInsts 124248120 # Number of integer instructions (Count)
board.processor.cores1.core.commitStats0.numLoadInsts 47275315 # Number of load instructions (Count)
board.processor.cores1.core.commitStats0.numStoreInsts 10340250 # Number of store instructions (Count)
board.processor.cores1.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores1.core.commitStats0.committedInstType::No_OpClass 997521 0.48% 0.48% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::IntAlu 73460329 35.42% 35.91% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::IntMult 170937 0.08% 35.99% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::IntDiv 665 0.00% 35.99% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::FloatAdd 9495909 4.58% 40.57% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::FloatCmp 0 0.00% 40.57% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::FloatCvt 0 0.00% 40.57% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::FloatMult 0 0.00% 40.57% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 40.57% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::FloatDiv 0 0.00% 40.57% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::FloatMisc 0 0.00% 40.57% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 40.57% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdAdd 397022 0.19% 40.76% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 40.76% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdAlu 7642136 3.69% 44.44% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdCmp 0 0.00% 44.44% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdCvt 397124 0.19% 44.64% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdMisc 2459426 1.19% 45.82% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdMult 0 0.00% 45.82% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 45.82% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 45.82% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdShift 782444 0.38% 46.20% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 46.20% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdDiv 0 0.00% 46.20% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 46.20% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdFloatAdd 23234664 11.20% 57.40% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdFloatAlu 1589278 0.77% 58.17% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdFloatCmp 1339681 0.65% 58.82% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdFloatCvt 2697219 1.30% 60.12% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdFloatDiv 523541 0.25% 60.37% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 60.37% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdFloatMult 24527166 11.83% 72.20% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 72.20% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 72.20% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdFloatSqrt 39663 0.02% 72.22% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 72.22% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 72.22% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 72.22% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 72.22% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 72.22% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdAes 0 0.00% 72.22% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 72.22% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 72.22% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 72.22% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 72.22% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 72.22% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 72.22% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 72.22% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 72.22% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::Matrix 0 0.00% 72.22% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::MatrixMov 0 0.00% 72.22% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::MatrixOP 0 0.00% 72.22% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::MemRead 13078191 6.31% 78.52% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::MemWrite 2344787 1.13% 79.65% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::FloatMemRead 34197124 16.49% 96.14% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::FloatMemWrite 7995463 3.86% 100.00% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedInstType::total 207370290 # Class of committed instruction. (Count)
board.processor.cores1.core.commitStats0.committedControl::IsControl 10982057 # Class of control type instructions committed (Count)
board.processor.cores1.core.commitStats0.committedControl::IsDirectControl 9974486 # Class of control type instructions committed (Count)
board.processor.cores1.core.commitStats0.committedControl::IsIndirectControl 1007571 # Class of control type instructions committed (Count)
board.processor.cores1.core.commitStats0.committedControl::IsCondControl 9243655 # Class of control type instructions committed (Count)
board.processor.cores1.core.commitStats0.committedControl::IsUncondControl 1738402 # Class of control type instructions committed (Count)
board.processor.cores1.core.commitStats0.committedControl::IsCall 421437 # Class of control type instructions committed (Count)
board.processor.cores1.core.commitStats0.committedControl::IsReturn 421436 # Class of control type instructions committed (Count)
board.processor.cores1.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.cores1.core.exec_context.thread_0.numCallsReturns 842873 # Number of times a function call or return occured (Count)
board.processor.cores1.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.cores1.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.cores1.core.exec_context.thread_0.numBusyCycles 279152814 # Number of busy cycles (Cycle)
board.processor.cores1.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.cores1.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.cores1.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.cores1.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores1.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.cores1.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.cores1.core.executeStats0.numStoreInsts 57615565 # Number of stores executed (Count)
board.processor.cores1.core.executeStats0.instRate 0 # Inst execution rate ((Count/Cycle))
board.processor.cores1.core.executeStats0.numFpAluAccesses 125312407 # Number of float alu accesses (Count)
board.processor.cores1.core.executeStats0.numFpRegReads 206877681 # Number of times the floating registers were read (Count)
board.processor.cores1.core.executeStats0.numFpRegWrites 115241435 # Number of times the floating registers were written (Count)
board.processor.cores1.core.executeStats0.numIntAluAccesses 124248120 # Number of integer alu accesses (Count)
board.processor.cores1.core.executeStats0.numIntRegReads 162489362 # Number of times the integer registers were read (Count)
board.processor.cores1.core.executeStats0.numIntRegWrites 60290879 # Number of times the integer registers were written (Count)
board.processor.cores1.core.executeStats0.numMemRefs 57615565 # Number of memory refs (Count)
board.processor.cores1.core.executeStats0.numMiscRegReads 82465443 # Number of times the Misc registers were read (Count)
board.processor.cores1.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores1.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores1.core.fetchStats0.numInsts 108038540 # Number of instructions fetched (thread level) (Count)
board.processor.cores1.core.fetchStats0.numOps 207370291 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores1.core.fetchStats0.fetchRate 0.387023 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores1.core.fetchStats0.numBranches 10982057 # Number of branches fetched (Count)
board.processor.cores1.core.fetchStats0.branchRate 0.039341 # Number of branch fetches per cycle (Ratio)
board.processor.cores1.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores1.core.interrupts.clk_domain.clock 8000 # Clock period in ticks (Tick)
board.processor.cores1.core.mmu.dtb.rdAccesses 48517278 # TLB accesses on read requests (Count)
board.processor.cores1.core.mmu.dtb.wrAccesses 10416753 # TLB accesses on write requests (Count)
board.processor.cores1.core.mmu.dtb.rdMisses 34723 # TLB misses on read requests (Count)
board.processor.cores1.core.mmu.dtb.wrMisses 7410 # TLB misses on write requests (Count)
board.processor.cores1.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores1.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.cores1.core.mmu.itb.wrAccesses 154986506 # TLB accesses on write requests (Count)
board.processor.cores1.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores1.core.mmu.itb.wrMisses 1442 # TLB misses on write requests (Count)
board.processor.cores1.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores1.core.power_state.pwrStateResidencyTicks::ON 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores1.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.cores1.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.cores1.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.cores2.core.numCycles 279152826 # Number of cpu cycles simulated (Cycle)
board.processor.cores2.core.cpi 2.618541 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores2.core.ipc 0.381892 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores2.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores2.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores2.core.commitStats0.numInsts 106606238 # Number of instructions committed (thread level) (Count)
board.processor.cores2.core.commitStats0.numOps 204529041 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores2.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores2.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores2.core.commitStats0.cpi 2.618541 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores2.core.commitStats0.ipc 0.381892 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores2.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.cores2.core.commitStats0.numFpInsts 135871462 # Number of float instructions (Count)
board.processor.cores2.core.commitStats0.numIntInsts 113973204 # Number of integer instructions (Count)
board.processor.cores2.core.commitStats0.numLoadInsts 47337826 # Number of load instructions (Count)
board.processor.cores2.core.commitStats0.numStoreInsts 10166119 # Number of store instructions (Count)
board.processor.cores2.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores2.core.commitStats0.committedInstType::No_OpClass 914158 0.45% 0.45% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::IntAlu 63866753 31.23% 31.67% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::IntMult 178032 0.09% 31.76% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::IntDiv 665 0.00% 31.76% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::FloatAdd 10307985 5.04% 36.80% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::FloatCmp 0 0.00% 36.80% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::FloatCvt 0 0.00% 36.80% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::FloatMult 0 0.00% 36.80% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 36.80% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::FloatDiv 0 0.00% 36.80% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::FloatMisc 0 0.00% 36.80% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 36.80% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdAdd 425956 0.21% 37.01% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 37.01% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdAlu 8449378 4.13% 41.14% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdCmp 0 0.00% 41.14% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdCvt 431578 0.21% 41.35% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdMisc 2590284 1.27% 42.62% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdMult 0 0.00% 42.62% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 42.62% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 42.62% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdShift 819616 0.40% 43.02% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 43.02% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdDiv 0 0.00% 43.02% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 43.02% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdFloatAdd 25493492 12.46% 55.48% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdFloatAlu 1710605 0.84% 56.32% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdFloatCmp 1525219 0.75% 57.06% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdFloatCvt 2886868 1.41% 58.48% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdFloatDiv 552633 0.27% 58.75% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 58.75% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdFloatMult 26832106 13.12% 71.87% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 71.87% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 71.87% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdFloatSqrt 39768 0.02% 71.88% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 71.88% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 71.88% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 71.88% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 71.88% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 71.88% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdAes 0 0.00% 71.88% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 71.88% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 71.88% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 71.88% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 71.88% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 71.88% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 71.88% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 71.88% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 71.88% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::Matrix 0 0.00% 71.88% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::MatrixMov 0 0.00% 71.88% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::MatrixOP 0 0.00% 71.88% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::MemRead 10476449 5.12% 77.01% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::MemWrite 1990772 0.97% 77.98% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::FloatMemRead 36861377 18.02% 96.00% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::FloatMemWrite 8175347 4.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedInstType::total 204529041 # Class of committed instruction. (Count)
board.processor.cores2.core.commitStats0.committedControl::IsControl 8983703 # Class of control type instructions committed (Count)
board.processor.cores2.core.commitStats0.committedControl::IsDirectControl 8180783 # Class of control type instructions committed (Count)
board.processor.cores2.core.commitStats0.committedControl::IsIndirectControl 802920 # Class of control type instructions committed (Count)
board.processor.cores2.core.commitStats0.committedControl::IsCondControl 7587239 # Class of control type instructions committed (Count)
board.processor.cores2.core.commitStats0.committedControl::IsUncondControl 1396464 # Class of control type instructions committed (Count)
board.processor.cores2.core.commitStats0.committedControl::IsCall 314991 # Class of control type instructions committed (Count)
board.processor.cores2.core.commitStats0.committedControl::IsReturn 314988 # Class of control type instructions committed (Count)
board.processor.cores2.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.cores2.core.exec_context.thread_0.numCallsReturns 629979 # Number of times a function call or return occured (Count)
board.processor.cores2.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.cores2.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.cores2.core.exec_context.thread_0.numBusyCycles 279152826 # Number of busy cycles (Cycle)
board.processor.cores2.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.cores2.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.cores2.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.cores2.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores2.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.cores2.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.cores2.core.executeStats0.numStoreInsts 57503945 # Number of stores executed (Count)
board.processor.cores2.core.executeStats0.instRate 0 # Inst execution rate ((Count/Cycle))
board.processor.cores2.core.executeStats0.numFpAluAccesses 135871462 # Number of float alu accesses (Count)
board.processor.cores2.core.executeStats0.numFpRegReads 225783377 # Number of times the floating registers were read (Count)
board.processor.cores2.core.executeStats0.numFpRegWrites 125484008 # Number of times the floating registers were written (Count)
board.processor.cores2.core.executeStats0.numIntAluAccesses 113973204 # Number of integer alu accesses (Count)
board.processor.cores2.core.executeStats0.numIntRegReads 153700575 # Number of times the integer registers were read (Count)
board.processor.cores2.core.executeStats0.numIntRegWrites 51422499 # Number of times the integer registers were written (Count)
board.processor.cores2.core.executeStats0.numMemRefs 57503945 # Number of memory refs (Count)
board.processor.cores2.core.executeStats0.numMiscRegReads 78206002 # Number of times the Misc registers were read (Count)
board.processor.cores2.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores2.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores2.core.fetchStats0.numInsts 106606238 # Number of instructions fetched (thread level) (Count)
board.processor.cores2.core.fetchStats0.numOps 204529040 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores2.core.fetchStats0.fetchRate 0.381892 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores2.core.fetchStats0.numBranches 8983703 # Number of branches fetched (Count)
board.processor.cores2.core.fetchStats0.branchRate 0.032182 # Number of branch fetches per cycle (Ratio)
board.processor.cores2.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores2.core.interrupts.clk_domain.clock 8000 # Clock period in ticks (Tick)
board.processor.cores2.core.mmu.dtb.rdAccesses 48671792 # TLB accesses on read requests (Count)
board.processor.cores2.core.mmu.dtb.wrAccesses 10254886 # TLB accesses on write requests (Count)
board.processor.cores2.core.mmu.dtb.rdMisses 34077 # TLB misses on read requests (Count)
board.processor.cores2.core.mmu.dtb.wrMisses 7490 # TLB misses on write requests (Count)
board.processor.cores2.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores2.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.cores2.core.mmu.itb.wrAccesses 153539122 # TLB accesses on write requests (Count)
board.processor.cores2.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores2.core.mmu.itb.wrMisses 664 # TLB misses on write requests (Count)
board.processor.cores2.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores2.core.power_state.pwrStateResidencyTicks::ON 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores2.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.cores2.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.cores2.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.cores3.core.numCycles 279152806 # Number of cpu cycles simulated (Cycle)
board.processor.cores3.core.cpi 2.623212 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores3.core.ipc 0.381212 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores3.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores3.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores3.core.commitStats0.numInsts 106416422 # Number of instructions committed (thread level) (Count)
board.processor.cores3.core.commitStats0.numOps 204072216 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores3.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores3.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores3.core.commitStats0.cpi 2.623212 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores3.core.commitStats0.ipc 0.381212 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores3.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.cores3.core.commitStats0.numFpInsts 136384176 # Number of float instructions (Count)
board.processor.cores3.core.commitStats0.numIntInsts 113280639 # Number of integer instructions (Count)
board.processor.cores3.core.commitStats0.numLoadInsts 47262693 # Number of load instructions (Count)
board.processor.cores3.core.commitStats0.numStoreInsts 10213147 # Number of store instructions (Count)
board.processor.cores3.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores3.core.commitStats0.committedInstType::No_OpClass 891259 0.44% 0.44% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::IntAlu 63149074 30.94% 31.38% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::IntMult 177370 0.09% 31.47% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::IntDiv 665 0.00% 31.47% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::FloatAdd 10403384 5.10% 36.57% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::FloatCmp 0 0.00% 36.57% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::FloatCvt 0 0.00% 36.57% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::FloatMult 0 0.00% 36.57% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 36.57% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::FloatDiv 0 0.00% 36.57% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::FloatMisc 0 0.00% 36.57% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 36.57% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdAdd 456954 0.22% 36.79% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 36.79% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdAlu 8490172 4.16% 40.95% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdCmp 0 0.00% 40.95% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdCvt 455856 0.22% 41.17% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdMisc 2552499 1.25% 42.42% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdMult 0 0.00% 42.42% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 42.42% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 42.42% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdShift 799450 0.39% 42.82% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 42.82% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdDiv 0 0.00% 42.82% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 42.82% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdFloatAdd 25583432 12.54% 55.35% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdFloatAlu 1700028 0.83% 56.19% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdFloatCmp 1539981 0.75% 56.94% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdFloatCvt 2962692 1.45% 58.39% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdFloatDiv 556664 0.27% 58.67% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 58.67% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdFloatMult 26834478 13.15% 71.81% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 71.81% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 71.81% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdFloatSqrt 42418 0.02% 71.84% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 71.84% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 71.84% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 71.84% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 71.84% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 71.84% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdAes 0 0.00% 71.84% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 71.84% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 71.84% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 71.84% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 71.84% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 71.84% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 71.84% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 71.84% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 71.84% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::Matrix 0 0.00% 71.84% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::MatrixMov 0 0.00% 71.84% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::MatrixOP 0 0.00% 71.84% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::MemRead 10246936 5.02% 76.86% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::MemWrite 1990062 0.98% 77.83% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::FloatMemRead 37015757 18.14% 95.97% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::FloatMemWrite 8223085 4.03% 100.00% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedInstType::total 204072216 # Class of committed instruction. (Count)
board.processor.cores3.core.commitStats0.committedControl::IsControl 8739026 # Class of control type instructions committed (Count)
board.processor.cores3.core.commitStats0.committedControl::IsDirectControl 7957216 # Class of control type instructions committed (Count)
board.processor.cores3.core.commitStats0.committedControl::IsIndirectControl 781810 # Class of control type instructions committed (Count)
board.processor.cores3.core.commitStats0.committedControl::IsCondControl 7374543 # Class of control type instructions committed (Count)
board.processor.cores3.core.commitStats0.committedControl::IsUncondControl 1364483 # Class of control type instructions committed (Count)
board.processor.cores3.core.commitStats0.committedControl::IsCall 309971 # Class of control type instructions committed (Count)
board.processor.cores3.core.commitStats0.committedControl::IsReturn 309968 # Class of control type instructions committed (Count)
board.processor.cores3.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.cores3.core.exec_context.thread_0.numCallsReturns 619939 # Number of times a function call or return occured (Count)
board.processor.cores3.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.cores3.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.cores3.core.exec_context.thread_0.numBusyCycles 279152806 # Number of busy cycles (Cycle)
board.processor.cores3.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.cores3.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.cores3.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.cores3.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores3.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.cores3.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.cores3.core.executeStats0.numStoreInsts 57475840 # Number of stores executed (Count)
board.processor.cores3.core.executeStats0.instRate 0 # Inst execution rate ((Count/Cycle))
board.processor.cores3.core.executeStats0.numFpAluAccesses 136384176 # Number of float alu accesses (Count)
board.processor.cores3.core.executeStats0.numFpRegReads 226290581 # Number of times the floating registers were read (Count)
board.processor.cores3.core.executeStats0.numFpRegWrites 125917368 # Number of times the floating registers were written (Count)
board.processor.cores3.core.executeStats0.numIntAluAccesses 113280639 # Number of integer alu accesses (Count)
board.processor.cores3.core.executeStats0.numIntRegReads 152907932 # Number of times the integer registers were read (Count)
board.processor.cores3.core.executeStats0.numIntRegWrites 50962898 # Number of times the integer registers were written (Count)
board.processor.cores3.core.executeStats0.numMemRefs 57475840 # Number of memory refs (Count)
board.processor.cores3.core.executeStats0.numMiscRegReads 77848366 # Number of times the Misc registers were read (Count)
board.processor.cores3.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores3.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores3.core.fetchStats0.numInsts 106416422 # Number of instructions fetched (thread level) (Count)
board.processor.cores3.core.fetchStats0.numOps 204072217 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores3.core.fetchStats0.fetchRate 0.381212 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores3.core.fetchStats0.numBranches 8739026 # Number of branches fetched (Count)
board.processor.cores3.core.fetchStats0.branchRate 0.031306 # Number of branch fetches per cycle (Ratio)
board.processor.cores3.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores3.core.interrupts.clk_domain.clock 8000 # Clock period in ticks (Tick)
board.processor.cores3.core.mmu.dtb.rdAccesses 48593581 # TLB accesses on read requests (Count)
board.processor.cores3.core.mmu.dtb.wrAccesses 10299042 # TLB accesses on write requests (Count)
board.processor.cores3.core.mmu.dtb.rdMisses 34178 # TLB misses on read requests (Count)
board.processor.cores3.core.mmu.dtb.wrMisses 7558 # TLB misses on write requests (Count)
board.processor.cores3.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores3.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.cores3.core.mmu.itb.wrAccesses 153389902 # TLB accesses on write requests (Count)
board.processor.cores3.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores3.core.mmu.itb.wrMisses 652 # TLB misses on write requests (Count)
board.processor.cores3.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores3.core.power_state.pwrStateResidencyTicks::ON 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores3.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.cores3.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.cores3.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.cores4.core.numCycles 279152807 # Number of cpu cycles simulated (Cycle)
board.processor.cores4.core.cpi 2.520173 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores4.core.ipc 0.396798 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores4.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores4.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores4.core.commitStats0.numInsts 110767307 # Number of instructions committed (thread level) (Count)
board.processor.cores4.core.commitStats0.numOps 213508114 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores4.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores4.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores4.core.commitStats0.cpi 2.520173 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores4.core.commitStats0.ipc 0.396798 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores4.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.cores4.core.commitStats0.numFpInsts 121499360 # Number of float instructions (Count)
board.processor.cores4.core.commitStats0.numIntInsts 131949719 # Number of integer instructions (Count)
board.processor.cores4.core.commitStats0.numLoadInsts 48415541 # Number of load instructions (Count)
board.processor.cores4.core.commitStats0.numStoreInsts 9752165 # Number of store instructions (Count)
board.processor.cores4.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores4.core.commitStats0.committedInstType::No_OpClass 1055946 0.49% 0.49% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::IntAlu 80560291 37.73% 38.23% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::IntMult 161179 0.08% 38.30% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::IntDiv 665 0.00% 38.30% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::FloatAdd 9401203 4.40% 42.71% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::FloatCmp 0 0.00% 42.71% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::FloatCvt 0 0.00% 42.71% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::FloatMult 0 0.00% 42.71% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 42.71% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::FloatDiv 0 0.00% 42.71% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::FloatMisc 0 0.00% 42.71% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 42.71% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdAdd 407678 0.19% 42.90% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 42.90% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdAlu 7667924 3.59% 46.49% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdCmp 0 0.00% 46.49% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdCvt 397570 0.19% 46.67% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdMisc 2345398 1.10% 47.77% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdMult 0 0.00% 47.77% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 47.77% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 47.77% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdShift 727900 0.34% 48.11% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 48.11% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdDiv 0 0.00% 48.11% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 48.11% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdFloatAdd 22652801 10.61% 58.72% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdFloatAlu 1516541 0.71% 59.43% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdFloatCmp 1407039 0.66% 60.09% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdFloatCvt 2660911 1.25% 61.34% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdFloatDiv 497514 0.23% 61.57% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 61.57% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdFloatMult 23840949 11.17% 72.74% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 72.74% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 72.74% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdFloatSqrt 38899 0.02% 72.76% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 72.76% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 72.76% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 72.76% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 72.76% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 72.76% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdAes 0 0.00% 72.76% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 72.76% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 72.76% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 72.76% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 72.76% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 72.76% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 72.76% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 72.76% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 72.76% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::Matrix 0 0.00% 72.76% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::MatrixMov 0 0.00% 72.76% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::MatrixOP 0 0.00% 72.76% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::MemRead 15610056 7.31% 80.07% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::MemWrite 2480533 1.16% 81.23% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::FloatMemRead 32805485 15.36% 96.59% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::FloatMemWrite 7271632 3.41% 100.00% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedInstType::total 213508114 # Class of committed instruction. (Count)
board.processor.cores4.core.commitStats0.committedControl::IsControl 12453196 # Class of control type instructions committed (Count)
board.processor.cores4.core.commitStats0.committedControl::IsDirectControl 11278287 # Class of control type instructions committed (Count)
board.processor.cores4.core.commitStats0.committedControl::IsIndirectControl 1174909 # Class of control type instructions committed (Count)
board.processor.cores4.core.commitStats0.committedControl::IsCondControl 10520105 # Class of control type instructions committed (Count)
board.processor.cores4.core.commitStats0.committedControl::IsUncondControl 1933091 # Class of control type instructions committed (Count)
board.processor.cores4.core.commitStats0.committedControl::IsCall 512443 # Class of control type instructions committed (Count)
board.processor.cores4.core.commitStats0.committedControl::IsReturn 512443 # Class of control type instructions committed (Count)
board.processor.cores4.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.cores4.core.exec_context.thread_0.numCallsReturns 1024886 # Number of times a function call or return occured (Count)
board.processor.cores4.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.cores4.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.cores4.core.exec_context.thread_0.numBusyCycles 279152807 # Number of busy cycles (Cycle)
board.processor.cores4.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.cores4.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.cores4.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.cores4.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores4.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.cores4.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.cores4.core.executeStats0.numStoreInsts 58167706 # Number of stores executed (Count)
board.processor.cores4.core.executeStats0.instRate 0 # Inst execution rate ((Count/Cycle))
board.processor.cores4.core.executeStats0.numFpAluAccesses 121499360 # Number of float alu accesses (Count)
board.processor.cores4.core.executeStats0.numFpRegReads 201541005 # Number of times the floating registers were read (Count)
board.processor.cores4.core.executeStats0.numFpRegWrites 112183311 # Number of times the floating registers were written (Count)
board.processor.cores4.core.executeStats0.numIntAluAccesses 131949719 # Number of integer alu accesses (Count)
board.processor.cores4.core.executeStats0.numIntRegReads 167162311 # Number of times the integer registers were read (Count)
board.processor.cores4.core.executeStats0.numIntRegWrites 67130077 # Number of times the integer registers were written (Count)
board.processor.cores4.core.executeStats0.numMemRefs 58167706 # Number of memory refs (Count)
board.processor.cores4.core.executeStats0.numMiscRegReads 86570303 # Number of times the Misc registers were read (Count)
board.processor.cores4.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores4.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores4.core.fetchStats0.numInsts 110767308 # Number of instructions fetched (thread level) (Count)
board.processor.cores4.core.fetchStats0.numOps 213508115 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores4.core.fetchStats0.fetchRate 0.396798 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores4.core.fetchStats0.numBranches 12453196 # Number of branches fetched (Count)
board.processor.cores4.core.fetchStats0.branchRate 0.044611 # Number of branch fetches per cycle (Ratio)
board.processor.cores4.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores4.core.interrupts.clk_domain.clock 8000 # Clock period in ticks (Tick)
board.processor.cores4.core.mmu.dtb.rdAccesses 49590975 # TLB accesses on read requests (Count)
board.processor.cores4.core.mmu.dtb.wrAccesses 9829192 # TLB accesses on write requests (Count)
board.processor.cores4.core.mmu.dtb.rdMisses 30510 # TLB misses on read requests (Count)
board.processor.cores4.core.mmu.dtb.wrMisses 6764 # TLB misses on write requests (Count)
board.processor.cores4.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores4.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.cores4.core.mmu.itb.wrAccesses 159353941 # TLB accesses on write requests (Count)
board.processor.cores4.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores4.core.mmu.itb.wrMisses 682 # TLB misses on write requests (Count)
board.processor.cores4.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores4.core.power_state.pwrStateResidencyTicks::ON 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores4.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.cores4.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.cores4.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.cores5.core.numCycles 279152939 # Number of cpu cycles simulated (Cycle)
board.processor.cores5.core.cpi 2.513101 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores5.core.ipc 0.397915 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores5.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores5.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores5.core.commitStats0.numInsts 111079071 # Number of instructions committed (thread level) (Count)
board.processor.cores5.core.commitStats0.numOps 214113878 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores5.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores5.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores5.core.commitStats0.cpi 2.513101 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores5.core.commitStats0.ipc 0.397915 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores5.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.cores5.core.commitStats0.numFpInsts 122148962 # Number of float instructions (Count)
board.processor.cores5.core.commitStats0.numIntInsts 132121064 # Number of integer instructions (Count)
board.processor.cores5.core.commitStats0.numLoadInsts 48488443 # Number of load instructions (Count)
board.processor.cores5.core.commitStats0.numStoreInsts 9806421 # Number of store instructions (Count)
board.processor.cores5.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores5.core.commitStats0.committedInstType::No_OpClass 1057142 0.49% 0.49% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::IntAlu 80617055 37.65% 38.15% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::IntMult 161224 0.08% 38.22% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::IntDiv 665 0.00% 38.22% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::FloatAdd 9489830 4.43% 42.65% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::FloatCmp 0 0.00% 42.65% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::FloatCvt 0 0.00% 42.65% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::FloatMult 0 0.00% 42.65% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 42.65% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::FloatDiv 0 0.00% 42.65% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::FloatMisc 0 0.00% 42.65% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 42.65% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdAdd 422704 0.20% 42.85% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 42.85% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdAlu 7742593 3.62% 46.47% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdCmp 0 0.00% 46.47% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdCvt 412076 0.19% 46.66% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdMisc 2365862 1.10% 47.76% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdMult 0 0.00% 47.76% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 47.76% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 47.76% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdShift 733647 0.34% 48.11% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 48.11% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdDiv 0 0.00% 48.11% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 48.11% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdFloatAdd 22720996 10.61% 58.72% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdFloatAlu 1517466 0.71% 59.43% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdFloatCmp 1419073 0.66% 60.09% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdFloatCvt 2710823 1.27% 61.36% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdFloatDiv 506193 0.24% 61.59% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 61.59% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdFloatMult 23900580 11.16% 72.75% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 72.75% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 72.75% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdFloatSqrt 41085 0.02% 72.77% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdAes 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::Matrix 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::MatrixMov 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::MatrixOP 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::MemRead 15531561 7.25% 80.03% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::MemWrite 2499920 1.17% 81.20% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::FloatMemRead 32956882 15.39% 96.59% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::FloatMemWrite 7306501 3.41% 100.00% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedInstType::total 214113878 # Class of committed instruction. (Count)
board.processor.cores5.core.commitStats0.committedControl::IsControl 12419807 # Class of control type instructions committed (Count)
board.processor.cores5.core.commitStats0.committedControl::IsDirectControl 11242646 # Class of control type instructions committed (Count)
board.processor.cores5.core.commitStats0.committedControl::IsIndirectControl 1177161 # Class of control type instructions committed (Count)
board.processor.cores5.core.commitStats0.committedControl::IsCondControl 10473462 # Class of control type instructions committed (Count)
board.processor.cores5.core.commitStats0.committedControl::IsUncondControl 1946345 # Class of control type instructions committed (Count)
board.processor.cores5.core.commitStats0.committedControl::IsCall 514205 # Class of control type instructions committed (Count)
board.processor.cores5.core.commitStats0.committedControl::IsReturn 514205 # Class of control type instructions committed (Count)
board.processor.cores5.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.cores5.core.exec_context.thread_0.numCallsReturns 1028410 # Number of times a function call or return occured (Count)
board.processor.cores5.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.cores5.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.cores5.core.exec_context.thread_0.numBusyCycles 279152939 # Number of busy cycles (Cycle)
board.processor.cores5.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.cores5.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.cores5.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.cores5.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores5.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.cores5.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.cores5.core.executeStats0.numStoreInsts 58294864 # Number of stores executed (Count)
board.processor.cores5.core.executeStats0.instRate 0 # Inst execution rate ((Count/Cycle))
board.processor.cores5.core.executeStats0.numFpAluAccesses 122148962 # Number of float alu accesses (Count)
board.processor.cores5.core.executeStats0.numFpRegReads 202479487 # Number of times the floating registers were read (Count)
board.processor.cores5.core.executeStats0.numFpRegWrites 112760087 # Number of times the floating registers were written (Count)
board.processor.cores5.core.executeStats0.numIntAluAccesses 132121064 # Number of integer alu accesses (Count)
board.processor.cores5.core.executeStats0.numIntRegReads 167356960 # Number of times the integer registers were read (Count)
board.processor.cores5.core.executeStats0.numIntRegWrites 67182594 # Number of times the integer registers were written (Count)
board.processor.cores5.core.executeStats0.numMemRefs 58294864 # Number of memory refs (Count)
board.processor.cores5.core.executeStats0.numMiscRegReads 86678565 # Number of times the Misc registers were read (Count)
board.processor.cores5.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores5.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores5.core.fetchStats0.numInsts 111079071 # Number of instructions fetched (thread level) (Count)
board.processor.cores5.core.fetchStats0.numOps 214113878 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores5.core.fetchStats0.fetchRate 0.397915 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores5.core.fetchStats0.numBranches 12419807 # Number of branches fetched (Count)
board.processor.cores5.core.fetchStats0.branchRate 0.044491 # Number of branch fetches per cycle (Ratio)
board.processor.cores5.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores5.core.interrupts.clk_domain.clock 8000 # Clock period in ticks (Tick)
board.processor.cores5.core.mmu.dtb.rdAccesses 49658045 # TLB accesses on read requests (Count)
board.processor.cores5.core.mmu.dtb.wrAccesses 9884908 # TLB accesses on write requests (Count)
board.processor.cores5.core.mmu.dtb.rdMisses 30891 # TLB misses on read requests (Count)
board.processor.cores5.core.mmu.dtb.wrMisses 6802 # TLB misses on write requests (Count)
board.processor.cores5.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores5.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.cores5.core.mmu.itb.wrAccesses 159804112 # TLB accesses on write requests (Count)
board.processor.cores5.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores5.core.mmu.itb.wrMisses 664 # TLB misses on write requests (Count)
board.processor.cores5.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores5.core.power_state.pwrStateResidencyTicks::ON 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores5.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.cores5.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.cores5.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.cores6.core.numCycles 279152937 # Number of cpu cycles simulated (Cycle)
board.processor.cores6.core.cpi 2.626733 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores6.core.ipc 0.380701 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores6.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores6.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores6.core.commitStats0.numInsts 106273823 # Number of instructions committed (thread level) (Count)
board.processor.cores6.core.commitStats0.numOps 203857807 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores6.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores6.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores6.core.commitStats0.cpi 2.626733 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores6.core.commitStats0.ipc 0.380701 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores6.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.cores6.core.commitStats0.numFpInsts 135843430 # Number of float instructions (Count)
board.processor.cores6.core.commitStats0.numIntInsts 113386851 # Number of integer instructions (Count)
board.processor.cores6.core.commitStats0.numLoadInsts 47255004 # Number of load instructions (Count)
board.processor.cores6.core.commitStats0.numStoreInsts 10162239 # Number of store instructions (Count)
board.processor.cores6.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores6.core.commitStats0.committedInstType::No_OpClass 900472 0.44% 0.44% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::IntAlu 63327442 31.06% 31.51% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::IntMult 178174 0.09% 31.59% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::IntDiv 665 0.00% 31.59% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::FloatAdd 10289377 5.05% 36.64% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::FloatCmp 0 0.00% 36.64% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::FloatCvt 0 0.00% 36.64% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::FloatMult 0 0.00% 36.64% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 36.64% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::FloatDiv 0 0.00% 36.64% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::FloatMisc 0 0.00% 36.64% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 36.64% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdAdd 435752 0.21% 36.86% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 36.86% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdAlu 8462837 4.15% 41.01% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdCmp 0 0.00% 41.01% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdCvt 441002 0.22% 41.22% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdMisc 2570846 1.26% 42.48% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdMult 0 0.00% 42.48% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 42.48% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 42.48% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdShift 810887 0.40% 42.88% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 42.88% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdDiv 0 0.00% 42.88% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 42.88% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdFloatAdd 25499096 12.51% 55.39% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdFloatAlu 1704690 0.84% 56.23% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdFloatCmp 1529404 0.75% 56.98% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdFloatCvt 2901319 1.42% 58.40% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdFloatDiv 548844 0.27% 58.67% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 58.67% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdFloatMult 26800211 13.15% 71.82% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 71.82% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 71.82% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdFloatSqrt 39546 0.02% 71.83% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 71.83% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 71.83% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 71.83% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 71.83% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 71.83% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdAes 0 0.00% 71.83% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 71.83% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 71.83% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 71.83% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 71.83% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 71.83% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 71.83% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 71.83% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 71.83% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::Matrix 0 0.00% 71.83% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::MatrixMov 0 0.00% 71.83% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::MatrixOP 0 0.00% 71.83% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::MemRead 10381841 5.09% 76.93% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::MemWrite 1981757 0.97% 77.90% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::FloatMemRead 36873163 18.09% 95.99% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::FloatMemWrite 8180482 4.01% 100.00% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedInstType::total 203857807 # Class of committed instruction. (Count)
board.processor.cores6.core.commitStats0.committedControl::IsControl 8837324 # Class of control type instructions committed (Count)
board.processor.cores6.core.commitStats0.committedControl::IsDirectControl 8050292 # Class of control type instructions committed (Count)
board.processor.cores6.core.commitStats0.committedControl::IsIndirectControl 787032 # Class of control type instructions committed (Count)
board.processor.cores6.core.commitStats0.committedControl::IsCondControl 7476912 # Class of control type instructions committed (Count)
board.processor.cores6.core.commitStats0.committedControl::IsUncondControl 1360412 # Class of control type instructions committed (Count)
board.processor.cores6.core.commitStats0.committedControl::IsCall 308384 # Class of control type instructions committed (Count)
board.processor.cores6.core.commitStats0.committedControl::IsReturn 308382 # Class of control type instructions committed (Count)
board.processor.cores6.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.cores6.core.exec_context.thread_0.numCallsReturns 616766 # Number of times a function call or return occured (Count)
board.processor.cores6.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.cores6.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.cores6.core.exec_context.thread_0.numBusyCycles 279152937 # Number of busy cycles (Cycle)
board.processor.cores6.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.cores6.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.cores6.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.cores6.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores6.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.cores6.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.cores6.core.executeStats0.numStoreInsts 57417243 # Number of stores executed (Count)
board.processor.cores6.core.executeStats0.instRate 0 # Inst execution rate ((Count/Cycle))
board.processor.cores6.core.executeStats0.numFpAluAccesses 135843430 # Number of float alu accesses (Count)
board.processor.cores6.core.executeStats0.numFpRegReads 225663249 # Number of times the floating registers were read (Count)
board.processor.cores6.core.executeStats0.numFpRegWrites 125442526 # Number of times the floating registers were written (Count)
board.processor.cores6.core.executeStats0.numIntAluAccesses 113386851 # Number of integer alu accesses (Count)
board.processor.cores6.core.executeStats0.numIntRegReads 153065142 # Number of times the integer registers were read (Count)
board.processor.cores6.core.executeStats0.numIntRegWrites 51075872 # Number of times the integer registers were written (Count)
board.processor.cores6.core.executeStats0.numMemRefs 57417243 # Number of memory refs (Count)
board.processor.cores6.core.executeStats0.numMiscRegReads 77924777 # Number of times the Misc registers were read (Count)
board.processor.cores6.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores6.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores6.core.fetchStats0.numInsts 106273823 # Number of instructions fetched (thread level) (Count)
board.processor.cores6.core.fetchStats0.numOps 203857807 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores6.core.fetchStats0.fetchRate 0.380701 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores6.core.fetchStats0.numBranches 8837324 # Number of branches fetched (Count)
board.processor.cores6.core.fetchStats0.branchRate 0.031658 # Number of branch fetches per cycle (Ratio)
board.processor.cores6.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores6.core.interrupts.clk_domain.clock 8000 # Clock period in ticks (Tick)
board.processor.cores6.core.mmu.dtb.rdAccesses 48586368 # TLB accesses on read requests (Count)
board.processor.cores6.core.mmu.dtb.wrAccesses 10249170 # TLB accesses on write requests (Count)
board.processor.cores6.core.mmu.dtb.rdMisses 35253 # TLB misses on read requests (Count)
board.processor.cores6.core.mmu.dtb.wrMisses 7662 # TLB misses on write requests (Count)
board.processor.cores6.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores6.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.cores6.core.mmu.itb.wrAccesses 153126807 # TLB accesses on write requests (Count)
board.processor.cores6.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores6.core.mmu.itb.wrMisses 642 # TLB misses on write requests (Count)
board.processor.cores6.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores6.core.power_state.pwrStateResidencyTicks::ON 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores6.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.cores6.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.cores6.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.processor.cores7.core.numCycles 279152892 # Number of cpu cycles simulated (Cycle)
board.processor.cores7.core.cpi 2.515791 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores7.core.ipc 0.397489 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores7.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores7.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores7.core.commitStats0.numInsts 110960278 # Number of instructions committed (thread level) (Count)
board.processor.cores7.core.commitStats0.numOps 213649582 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores7.core.commitStats0.numInstsNotNOP 0 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores7.core.commitStats0.numOpsNotNOP 0 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores7.core.commitStats0.cpi 2.515791 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores7.core.commitStats0.ipc 0.397489 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores7.core.commitStats0.numMemRefs 0 # Number of memory references committed (Count)
board.processor.cores7.core.commitStats0.numFpInsts 121403068 # Number of float instructions (Count)
board.processor.cores7.core.commitStats0.numIntInsts 132159520 # Number of integer instructions (Count)
board.processor.cores7.core.commitStats0.numLoadInsts 48425124 # Number of load instructions (Count)
board.processor.cores7.core.commitStats0.numStoreInsts 9744240 # Number of store instructions (Count)
board.processor.cores7.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores7.core.commitStats0.committedInstType::No_OpClass 1053527 0.49% 0.49% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::IntAlu 80754561 37.80% 38.29% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::IntMult 161104 0.08% 38.37% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::IntDiv 665 0.00% 38.37% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::FloatAdd 9379332 4.39% 42.76% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::FloatCmp 0 0.00% 42.76% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::FloatCvt 0 0.00% 42.76% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::FloatMult 0 0.00% 42.76% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 42.76% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::FloatDiv 0 0.00% 42.76% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::FloatMisc 0 0.00% 42.76% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 42.76% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdAdd 407346 0.19% 42.95% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 42.95% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdAlu 7676726 3.59% 46.54% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdCmp 0 0.00% 46.54% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdCvt 397492 0.19% 46.73% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdMisc 2332029 1.09% 47.82% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdMult 0 0.00% 47.82% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 47.82% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 47.82% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdShift 724902 0.34% 48.16% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 48.16% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdDiv 0 0.00% 48.16% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 48.16% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdFloatAdd 22641310 10.60% 58.75% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdFloatAlu 1513251 0.71% 59.46% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdFloatCmp 1413172 0.66% 60.12% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdFloatCvt 2660253 1.25% 61.37% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdFloatDiv 497008 0.23% 61.60% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 61.60% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdFloatMult 23826980 11.15% 72.75% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 72.75% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 72.75% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdFloatSqrt 40560 0.02% 72.77% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdAes 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::Matrix 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::MatrixMov 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::MatrixOP 0 0.00% 72.77% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::MemRead 15632897 7.32% 80.09% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::MemWrite 2485528 1.16% 81.25% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::FloatMemRead 32792227 15.35% 96.60% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::FloatMemWrite 7258712 3.40% 100.00% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedInstType::total 213649582 # Class of committed instruction. (Count)
board.processor.cores7.core.commitStats0.committedControl::IsControl 12446736 # Class of control type instructions committed (Count)
board.processor.cores7.core.commitStats0.committedControl::IsDirectControl 11271192 # Class of control type instructions committed (Count)
board.processor.cores7.core.commitStats0.committedControl::IsIndirectControl 1175544 # Class of control type instructions committed (Count)
board.processor.cores7.core.commitStats0.committedControl::IsCondControl 10512869 # Class of control type instructions committed (Count)
board.processor.cores7.core.commitStats0.committedControl::IsUncondControl 1933867 # Class of control type instructions committed (Count)
board.processor.cores7.core.commitStats0.committedControl::IsCall 512605 # Class of control type instructions committed (Count)
board.processor.cores7.core.commitStats0.committedControl::IsReturn 512605 # Class of control type instructions committed (Count)
board.processor.cores7.core.exec_context.thread_0.numMatAluAccesses 0 # Number of matrix alu accesses (Count)
board.processor.cores7.core.exec_context.thread_0.numCallsReturns 1025210 # Number of times a function call or return occured (Count)
board.processor.cores7.core.exec_context.thread_0.numMatInsts 0 # Number of matrix instructions (Count)
board.processor.cores7.core.exec_context.thread_0.numIdleCycles 0 # Number of idle cycles (Cycle)
board.processor.cores7.core.exec_context.thread_0.numBusyCycles 279152892 # Number of busy cycles (Cycle)
board.processor.cores7.core.exec_context.thread_0.notIdleFraction 1 # Percentage of non-idle cycles (Ratio)
board.processor.cores7.core.exec_context.thread_0.idleFraction 0 # Percentage of idle cycles (Ratio)
board.processor.cores7.core.executeStats0.numInsts 0 # Number of executed instructions (Count)
board.processor.cores7.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores7.core.executeStats0.numBranches 0 # Number of branches executed (Count)
board.processor.cores7.core.executeStats0.numLoadInsts 0 # Number of load instructions executed (Count)
board.processor.cores7.core.executeStats0.numStoreInsts 58169364 # Number of stores executed (Count)
board.processor.cores7.core.executeStats0.instRate 0 # Inst execution rate ((Count/Cycle))
board.processor.cores7.core.executeStats0.numFpAluAccesses 121403068 # Number of float alu accesses (Count)
board.processor.cores7.core.executeStats0.numFpRegReads 201396117 # Number of times the floating registers were read (Count)
board.processor.cores7.core.executeStats0.numFpRegWrites 112098690 # Number of times the floating registers were written (Count)
board.processor.cores7.core.executeStats0.numIntAluAccesses 132159520 # Number of integer alu accesses (Count)
board.processor.cores7.core.executeStats0.numIntRegReads 167563523 # Number of times the integer registers were read (Count)
board.processor.cores7.core.executeStats0.numIntRegWrites 67372936 # Number of times the integer registers were written (Count)
board.processor.cores7.core.executeStats0.numMemRefs 58169364 # Number of memory refs (Count)
board.processor.cores7.core.executeStats0.numMiscRegReads 86572277 # Number of times the Misc registers were read (Count)
board.processor.cores7.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores7.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores7.core.fetchStats0.numInsts 110960278 # Number of instructions fetched (thread level) (Count)
board.processor.cores7.core.fetchStats0.numOps 213649582 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores7.core.fetchStats0.fetchRate 0.397489 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores7.core.fetchStats0.numBranches 12446736 # Number of branches fetched (Count)
board.processor.cores7.core.fetchStats0.branchRate 0.044588 # Number of branch fetches per cycle (Ratio)
board.processor.cores7.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores7.core.interrupts.clk_domain.clock 8000 # Clock period in ticks (Tick)
board.processor.cores7.core.mmu.dtb.rdAccesses 49600410 # TLB accesses on read requests (Count)
board.processor.cores7.core.mmu.dtb.wrAccesses 9822717 # TLB accesses on write requests (Count)
board.processor.cores7.core.mmu.dtb.rdMisses 30228 # TLB misses on read requests (Count)
board.processor.cores7.core.mmu.dtb.wrMisses 6727 # TLB misses on write requests (Count)
board.processor.cores7.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores7.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.cores7.core.mmu.itb.wrAccesses 158789890 # TLB accesses on write requests (Count)
board.processor.cores7.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores7.core.mmu.itb.wrMisses 685 # TLB misses on write requests (Count)
board.processor.cores7.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores7.core.power_state.pwrStateResidencyTicks::ON 140053531500 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores7.core.thread_0.numInsts 0 # Number of Instructions committed (Count)
board.processor.cores7.core.thread_0.numOps 0 # Number of Ops committed (Count)
board.processor.cores7.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------