---------- Begin Simulation Statistics ----------
simSeconds 0.020000 # Number of seconds simulated (Second)
simTicks 20000000000 # Number of ticks simulated (Tick)
finalTick 20000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq 1000000000000 # The number of ticks per simulated second ((Tick/Second))
hostSeconds 243.66 # Real time elapsed on the host (Second)
hostTickRate 82080428 # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory 3735184 # Number of bytes of host memory used (Byte)
simInsts 45310492 # Number of instructions simulated (Count)
simOps 80086869 # Number of ops (including micro ops) simulated (Count)
hostInstRate 185955 # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate 328678 # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.apicbridge.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.bridge.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.dptw_cache.demandHits::processor.cores.core.mmu.dtb.walker 6991 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.dptw_cache.demandHits::total 6991 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.dptw_cache.overallHits::processor.cores.core.mmu.dtb.walker 6991 # number of overall hits (Count)
board.cache_hierarchy.clusters.dptw_cache.overallHits::total 6991 # number of overall hits (Count)
board.cache_hierarchy.clusters.dptw_cache.demandMisses::processor.cores.core.mmu.dtb.walker 299 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.dptw_cache.demandMisses::total 299 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.dptw_cache.overallMisses::processor.cores.core.mmu.dtb.walker 299 # number of overall misses (Count)
board.cache_hierarchy.clusters.dptw_cache.overallMisses::total 299 # number of overall misses (Count)
board.cache_hierarchy.clusters.dptw_cache.demandMissLatency::processor.cores.core.mmu.dtb.walker 1134198 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.demandMissLatency::total 1134198 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.overallMissLatency::processor.cores.core.mmu.dtb.walker 1134198 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.overallMissLatency::total 1134198 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.demandAccesses::processor.cores.core.mmu.dtb.walker 7290 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.dptw_cache.demandAccesses::total 7290 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.dptw_cache.overallAccesses::processor.cores.core.mmu.dtb.walker 7290 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.dptw_cache.overallAccesses::total 7290 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.dptw_cache.demandMissRate::processor.cores.core.mmu.dtb.walker 0.041015 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.demandMissRate::total 0.041015 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.overallMissRate::processor.cores.core.mmu.dtb.walker 0.041015 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.overallMissRate::total 0.041015 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.demandAvgMissLatency::processor.cores.core.mmu.dtb.walker 3793.304348 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.demandAvgMissLatency::total 3793.304348 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.overallAvgMissLatency::processor.cores.core.mmu.dtb.walker 3793.304348 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.overallAvgMissLatency::total 3793.304348 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.dptw_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.dptw_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.clusters.dptw_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.clusters.dptw_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.dptw_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.dptw_cache.writebacks::writebacks 2 # number of writebacks (Count)
board.cache_hierarchy.clusters.dptw_cache.writebacks::total 2 # number of writebacks (Count)
board.cache_hierarchy.clusters.dptw_cache.demandMshrMisses::processor.cores.core.mmu.dtb.walker 299 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.dptw_cache.demandMshrMisses::total 299 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.dptw_cache.overallMshrMisses::processor.cores.core.mmu.dtb.walker 299 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.dptw_cache.overallMshrMisses::total 299 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.dptw_cache.demandMshrMissLatency::processor.cores.core.mmu.dtb.walker 1034631 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.demandMshrMissLatency::total 1034631 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.overallMshrMissLatency::processor.cores.core.mmu.dtb.walker 1034631 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.overallMshrMissLatency::total 1034631 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.demandMshrMissRate::processor.cores.core.mmu.dtb.walker 0.041015 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.demandMshrMissRate::total 0.041015 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.overallMshrMissRate::processor.cores.core.mmu.dtb.walker 0.041015 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.overallMshrMissRate::total 0.041015 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.demandAvgMshrMissLatency::processor.cores.core.mmu.dtb.walker 3460.304348 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.demandAvgMshrMissLatency::total 3460.304348 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.overallAvgMshrMissLatency::processor.cores.core.mmu.dtb.walker 3460.304348 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.overallAvgMshrMissLatency::total 3460.304348 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.replacements 13 # number of replacements (Count)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.hits::processor.cores.core.mmu.dtb.walker 6991 # number of ReadReq hits (Count)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.hits::total 6991 # number of ReadReq hits (Count)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.misses::processor.cores.core.mmu.dtb.walker 299 # number of ReadReq misses (Count)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.misses::total 299 # number of ReadReq misses (Count)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.missLatency::processor.cores.core.mmu.dtb.walker 1134198 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.missLatency::total 1134198 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.accesses::processor.cores.core.mmu.dtb.walker 7290 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.accesses::total 7290 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.missRate::processor.cores.core.mmu.dtb.walker 0.041015 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.missRate::total 0.041015 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.avgMissLatency::processor.cores.core.mmu.dtb.walker 3793.304348 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.ReadReq.avgMissLatency::total 3793.304348 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.ReadReq.mshrMisses::processor.cores.core.mmu.dtb.walker 299 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.mshrMisses::total 299 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.mshrMissLatency::processor.cores.core.mmu.dtb.walker 1034631 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.mshrMissLatency::total 1034631 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.mshrMissRate::processor.cores.core.mmu.dtb.walker 0.041015 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.mshrMissRate::total 0.041015 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.dptw_cache.ReadReq.avgMshrMissLatency::processor.cores.core.mmu.dtb.walker 3460.304348 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.ReadReq.avgMshrMissLatency::total 3460.304348 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.dptw_cache.tags.tagsInUse 20.447111 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.clusters.dptw_cache.tags.totalRefs 7290 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.clusters.dptw_cache.tags.sampledRefs 299 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.clusters.dptw_cache.tags.avgRefs 24.381271 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.clusters.dptw_cache.tags.warmupTick 270396 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.clusters.dptw_cache.tags.occupancies::processor.cores.core.mmu.dtb.walker 20.447111 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.dptw_cache.tags.avgOccs::processor.cores.core.mmu.dtb.walker 0.159743 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.dptw_cache.tags.avgOccs::total 0.159743 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.dptw_cache.tags.occupanciesTaskId::1024 26 # Occupied blocks per task id (Count)
board.cache_hierarchy.clusters.dptw_cache.tags.ageTaskId_1024::3 15 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.dptw_cache.tags.ageTaskId_1024::4 11 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.dptw_cache.tags.ratioOccsTaskId::1024 0.203125 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.clusters.dptw_cache.tags.tagAccesses 29459 # Number of tag accesses (Count)
board.cache_hierarchy.clusters.dptw_cache.tags.dataAccesses 29459 # Number of data accesses (Count)
board.cache_hierarchy.clusters.dptw_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.iptw_cache.demandHits::processor.cores.core.mmu.itb.walker 148 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.iptw_cache.demandHits::total 148 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.iptw_cache.overallHits::processor.cores.core.mmu.itb.walker 148 # number of overall hits (Count)
board.cache_hierarchy.clusters.iptw_cache.overallHits::total 148 # number of overall hits (Count)
board.cache_hierarchy.clusters.iptw_cache.demandMisses::processor.cores.core.mmu.itb.walker 18 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.iptw_cache.demandMisses::total 18 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.iptw_cache.overallMisses::processor.cores.core.mmu.itb.walker 18 # number of overall misses (Count)
board.cache_hierarchy.clusters.iptw_cache.overallMisses::total 18 # number of overall misses (Count)
board.cache_hierarchy.clusters.iptw_cache.demandMissLatency::processor.cores.core.mmu.itb.walker 305694 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.demandMissLatency::total 305694 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.overallMissLatency::processor.cores.core.mmu.itb.walker 305694 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.overallMissLatency::total 305694 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.demandAccesses::processor.cores.core.mmu.itb.walker 166 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.iptw_cache.demandAccesses::total 166 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.iptw_cache.overallAccesses::processor.cores.core.mmu.itb.walker 166 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.iptw_cache.overallAccesses::total 166 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.iptw_cache.demandMissRate::processor.cores.core.mmu.itb.walker 0.108434 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.demandMissRate::total 0.108434 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.overallMissRate::processor.cores.core.mmu.itb.walker 0.108434 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.overallMissRate::total 0.108434 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.demandAvgMissLatency::processor.cores.core.mmu.itb.walker 16983 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.demandAvgMissLatency::total 16983 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.overallAvgMissLatency::processor.cores.core.mmu.itb.walker 16983 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.overallAvgMissLatency::total 16983 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.iptw_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.iptw_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.clusters.iptw_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.clusters.iptw_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.iptw_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.iptw_cache.demandMshrMisses::processor.cores.core.mmu.itb.walker 18 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.iptw_cache.demandMshrMisses::total 18 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.iptw_cache.overallMshrMisses::processor.cores.core.mmu.itb.walker 18 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.iptw_cache.overallMshrMisses::total 18 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.iptw_cache.demandMshrMissLatency::processor.cores.core.mmu.itb.walker 299700 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.demandMshrMissLatency::total 299700 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.overallMshrMissLatency::processor.cores.core.mmu.itb.walker 299700 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.overallMshrMissLatency::total 299700 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.demandMshrMissRate::processor.cores.core.mmu.itb.walker 0.108434 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.demandMshrMissRate::total 0.108434 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.overallMshrMissRate::processor.cores.core.mmu.itb.walker 0.108434 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.overallMshrMissRate::total 0.108434 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.demandAvgMshrMissLatency::processor.cores.core.mmu.itb.walker 16650 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.demandAvgMshrMissLatency::total 16650 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.overallAvgMshrMissLatency::processor.cores.core.mmu.itb.walker 16650 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.overallAvgMshrMissLatency::total 16650 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.replacements 0 # number of replacements (Count)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.hits::processor.cores.core.mmu.itb.walker 146 # number of ReadReq hits (Count)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.hits::total 146 # number of ReadReq hits (Count)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.misses::processor.cores.core.mmu.itb.walker 18 # number of ReadReq misses (Count)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.misses::total 18 # number of ReadReq misses (Count)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.missLatency::processor.cores.core.mmu.itb.walker 305694 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.missLatency::total 305694 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.accesses::processor.cores.core.mmu.itb.walker 164 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.accesses::total 164 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.missRate::processor.cores.core.mmu.itb.walker 0.109756 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.missRate::total 0.109756 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.avgMissLatency::processor.cores.core.mmu.itb.walker 16983 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.ReadReq.avgMissLatency::total 16983 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.ReadReq.mshrMisses::processor.cores.core.mmu.itb.walker 18 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.mshrMisses::total 18 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.mshrMissLatency::processor.cores.core.mmu.itb.walker 299700 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.mshrMissLatency::total 299700 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.mshrMissRate::processor.cores.core.mmu.itb.walker 0.109756 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.mshrMissRate::total 0.109756 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.iptw_cache.ReadReq.avgMshrMissLatency::processor.cores.core.mmu.itb.walker 16650 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.ReadReq.avgMshrMissLatency::total 16650 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.WriteReq.hits::processor.cores.core.mmu.itb.walker 2 # number of WriteReq hits (Count)
board.cache_hierarchy.clusters.iptw_cache.WriteReq.hits::total 2 # number of WriteReq hits (Count)
board.cache_hierarchy.clusters.iptw_cache.WriteReq.accesses::processor.cores.core.mmu.itb.walker 2 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.iptw_cache.WriteReq.accesses::total 2 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.iptw_cache.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.iptw_cache.tags.tagsInUse 11.531734 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.clusters.iptw_cache.tags.totalRefs 166 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.clusters.iptw_cache.tags.sampledRefs 18 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.clusters.iptw_cache.tags.avgRefs 9.222222 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.clusters.iptw_cache.tags.warmupTick 70596 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.clusters.iptw_cache.tags.occupancies::processor.cores.core.mmu.itb.walker 11.531734 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.iptw_cache.tags.avgOccs::processor.cores.core.mmu.itb.walker 0.090092 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.iptw_cache.tags.avgOccs::total 0.090092 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.iptw_cache.tags.occupanciesTaskId::1024 13 # Occupied blocks per task id (Count)
board.cache_hierarchy.clusters.iptw_cache.tags.ageTaskId_1024::3 2 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.iptw_cache.tags.ageTaskId_1024::4 11 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.iptw_cache.tags.ratioOccsTaskId::1024 0.101562 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.clusters.iptw_cache.tags.tagAccesses 682 # Number of tag accesses (Count)
board.cache_hierarchy.clusters.iptw_cache.tags.dataAccesses 682 # Number of data accesses (Count)
board.cache_hierarchy.clusters.iptw_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l1dcache.demandHits::processor.cores.core.data 13911686 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l1dcache.demandHits::total 13911686 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l1dcache.overallHits::processor.cores.core.data 13911686 # number of overall hits (Count)
board.cache_hierarchy.clusters.l1dcache.overallHits::total 13911686 # number of overall hits (Count)
board.cache_hierarchy.clusters.l1dcache.demandMisses::processor.cores.core.data 581356 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l1dcache.demandMisses::total 581356 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l1dcache.overallMisses::processor.cores.core.data 581356 # number of overall misses (Count)
board.cache_hierarchy.clusters.l1dcache.overallMisses::total 581356 # number of overall misses (Count)
board.cache_hierarchy.clusters.l1dcache.demandMissLatency::processor.cores.core.data 8122115421 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.demandMissLatency::total 8122115421 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.overallMissLatency::processor.cores.core.data 8122115421 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.overallMissLatency::total 8122115421 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.demandAccesses::processor.cores.core.data 14493042 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1dcache.demandAccesses::total 14493042 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1dcache.overallAccesses::processor.cores.core.data 14493042 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1dcache.overallAccesses::total 14493042 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1dcache.demandMissRate::processor.cores.core.data 0.040113 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.demandMissRate::total 0.040113 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.overallMissRate::processor.cores.core.data 0.040113 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.overallMissRate::total 0.040113 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.demandAvgMissLatency::processor.cores.core.data 13970.984080 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.demandAvgMissLatency::total 13970.984080 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.overallAvgMissLatency::processor.cores.core.data 13970.984080 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.overallAvgMissLatency::total 13970.984080 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.l1dcache.blockedCycles::no_targets 13 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.l1dcache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.clusters.l1dcache.blockedCauses::no_targets 1 # number of times access was blocked (Count)
board.cache_hierarchy.clusters.l1dcache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.l1dcache.avgBlocked::no_targets 13 # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.l1dcache.writebacks::writebacks 606779 # number of writebacks (Count)
board.cache_hierarchy.clusters.l1dcache.writebacks::total 606779 # number of writebacks (Count)
board.cache_hierarchy.clusters.l1dcache.demandMshrHits::processor.cores.core.data 531132 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.demandMshrHits::total 531132 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.overallMshrHits::processor.cores.core.data 531132 # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.overallMshrHits::total 531132 # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.demandMshrMisses::processor.cores.core.data 50224 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.demandMshrMisses::total 50224 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.overallMshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher 572726 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.overallMshrMisses::processor.cores.core.data 50224 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.overallMshrMisses::total 622950 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.overallMshrUncacheable::processor.cores.core.data 23758 # number of overall MSHR uncacheable misses (Count)
board.cache_hierarchy.clusters.l1dcache.overallMshrUncacheable::total 23758 # number of overall MSHR uncacheable misses (Count)
board.cache_hierarchy.clusters.l1dcache.demandMshrMissLatency::processor.cores.core.data 1879742043 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.demandMshrMissLatency::total 1879742043 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.overallMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 35411327298 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.overallMshrMissLatency::processor.cores.core.data 1879742043 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.overallMshrMissLatency::total 37291069341 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.overallMshrUncacheableLatency::processor.cores.core.data 4565373057 # number of overall MSHR uncacheable ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.overallMshrUncacheableLatency::total 4565373057 # number of overall MSHR uncacheable ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.demandMshrMissRate::processor.cores.core.data 0.003465 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.demandMshrMissRate::total 0.003465 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.overallMshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.overallMshrMissRate::processor.cores.core.data 0.003465 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.overallMshrMissRate::total 0.042983 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.demandAvgMshrMissLatency::processor.cores.core.data 37427.167151 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.demandAvgMshrMissLatency::total 37427.167151 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.overallAvgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 61829.439030 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.overallAvgMshrMissLatency::processor.cores.core.data 37427.167151 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.overallAvgMshrMissLatency::total 59862.058497 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.overallAvgMshrUncacheableLatency::processor.cores.core.data 192161.505893 # average overall mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.overallAvgMshrUncacheableLatency::total 192161.505893 # average overall mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.replacements 621803 # number of replacements (Count)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.mshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher 572726 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.mshrMisses::total 572726 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.mshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 35411327298 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.mshrMissLatency::total 35411327298 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.mshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.HardPFReq.avgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 61829.439030 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.HardPFReq.avgMshrMissLatency::total 61829.439030 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.hits::processor.cores.core.data 14792 # number of LockedRMWReadReq hits (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.hits::total 14792 # number of LockedRMWReadReq hits (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.misses::processor.cores.core.data 78 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.misses::total 78 # number of LockedRMWReadReq misses (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.missLatency::processor.cores.core.data 1381284 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.missLatency::total 1381284 # number of LockedRMWReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.accesses::processor.cores.core.data 14870 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.accesses::total 14870 # number of LockedRMWReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.missRate::processor.cores.core.data 0.005245 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.missRate::total 0.005245 # miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.avgMissLatency::processor.cores.core.data 17708.769231 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.avgMissLatency::total 17708.769231 # average LockedRMWReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.mshrMisses::processor.cores.core.data 78 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.mshrMisses::total 78 # number of LockedRMWReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.mshrMissLatency::processor.cores.core.data 42482142 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.mshrMissLatency::total 42482142 # number of LockedRMWReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.mshrMissRate::processor.cores.core.data 0.005245 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.mshrMissRate::total 0.005245 # mshr miss rate for LockedRMWReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.avgMshrMissLatency::processor.cores.core.data 544642.846154 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.LockedRMWReadReq.avgMshrMissLatency::total 544642.846154 # average LockedRMWReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.LockedRMWWriteReq.hits::processor.cores.core.data 14870 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWWriteReq.hits::total 14870 # number of LockedRMWWriteReq hits (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWWriteReq.accesses::processor.cores.core.data 14870 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1dcache.LockedRMWWriteReq.accesses::total 14870 # number of LockedRMWWriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.hits::processor.cores.core.data 5730718 # number of ReadReq hits (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.hits::total 5730718 # number of ReadReq hits (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.misses::processor.cores.core.data 89032 # number of ReadReq misses (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.misses::total 89032 # number of ReadReq misses (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.missLatency::processor.cores.core.data 1469560635 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.ReadReq.missLatency::total 1469560635 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.ReadReq.accesses::processor.cores.core.data 5819750 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.accesses::total 5819750 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.missRate::processor.cores.core.data 0.015298 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.ReadReq.missRate::total 0.015298 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.ReadReq.avgMissLatency::processor.cores.core.data 16505.982512 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.ReadReq.avgMissLatency::total 16505.982512 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrHits::processor.cores.core.data 51095 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrHits::total 51095 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrMisses::processor.cores.core.data 37937 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrMisses::total 37937 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrUncacheable::processor.cores.core.data 20852 # number of ReadReq MSHR uncacheable (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrUncacheable::total 20852 # number of ReadReq MSHR uncacheable (Count)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrMissLatency::processor.cores.core.data 638779914 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrMissLatency::total 638779914 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrUncacheableLatency::processor.cores.core.data 4565373057 # number of ReadReq MSHR uncacheable ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrUncacheableLatency::total 4565373057 # number of ReadReq MSHR uncacheable ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrMissRate::processor.cores.core.data 0.006519 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.ReadReq.mshrMissRate::total 0.006519 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.ReadReq.avgMshrMissLatency::processor.cores.core.data 16837.913225 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.ReadReq.avgMshrMissLatency::total 16837.913225 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.ReadReq.avgMshrUncacheableLatency::processor.cores.core.data 218941.734941 # average ReadReq mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.ReadReq.avgMshrUncacheableLatency::total 218941.734941 # average ReadReq mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.WriteReq.hits::processor.cores.core.data 8180968 # number of WriteReq hits (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.hits::total 8180968 # number of WriteReq hits (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.misses::processor.cores.core.data 492324 # number of WriteReq misses (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.misses::total 492324 # number of WriteReq misses (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.missLatency::processor.cores.core.data 6652554786 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.WriteReq.missLatency::total 6652554786 # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.WriteReq.accesses::processor.cores.core.data 8673292 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.accesses::total 8673292 # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.missRate::processor.cores.core.data 0.056763 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.WriteReq.missRate::total 0.056763 # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.WriteReq.avgMissLatency::processor.cores.core.data 13512.554306 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.WriteReq.avgMissLatency::total 13512.554306 # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrHits::processor.cores.core.data 480037 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrHits::total 480037 # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrMisses::processor.cores.core.data 12287 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrMisses::total 12287 # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrUncacheable::processor.cores.core.data 2906 # number of WriteReq MSHR uncacheable (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrUncacheable::total 2906 # number of WriteReq MSHR uncacheable (Count)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrMissLatency::processor.cores.core.data 1240962129 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrMissLatency::total 1240962129 # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrMissRate::processor.cores.core.data 0.001417 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.WriteReq.mshrMissRate::total 0.001417 # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.clusters.l1dcache.WriteReq.avgMshrMissLatency::processor.cores.core.data 100997.975828 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.WriteReq.avgMshrMissLatency::total 100997.975828 # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l1dcache.prefetcher.demandMshrMisses 50224 # demands not covered by prefetchs (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfIssued 2236135 # number of hwpf issued (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfUnused 634 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfUseful 87680 # number of useful prefetch (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfUsefulButMiss 140 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.accuracy 0.039211 # accuracy of the prefetcher (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.coverage 0.635805 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfHitInCache 181840 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfHitInMSHR 1481569 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfLate 1663409 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfIdentified 2254777 # number of prefetch candidates identified (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfBufferHit 14000 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfRemovedDemand 64 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfSpanPage 92123 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.pfUsefulSpanPage 4565 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.clusters.l1dcache.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l1dcache.tags.tagsInUse 255.942171 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.clusters.l1dcache.tags.totalRefs 14564498 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.clusters.l1dcache.tags.sampledRefs 622059 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.clusters.l1dcache.tags.avgRefs 23.413371 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.clusters.l1dcache.tags.warmupTick 395271 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.clusters.l1dcache.tags.occupancies::cache_hierarchy.clusters.l1dcache.prefetcher 153.622460 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l1dcache.tags.occupancies::processor.cores.core.data 102.319711 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l1dcache.tags.avgOccs::cache_hierarchy.clusters.l1dcache.prefetcher 0.600088 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l1dcache.tags.avgOccs::processor.cores.core.data 0.399686 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l1dcache.tags.avgOccs::total 0.999774 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l1dcache.tags.occupanciesTaskId::1022 250 # Occupied blocks per task id (Count)
board.cache_hierarchy.clusters.l1dcache.tags.occupanciesTaskId::1024 6 # Occupied blocks per task id (Count)
board.cache_hierarchy.clusters.l1dcache.tags.ageTaskId_1022::0 250 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l1dcache.tags.ageTaskId_1024::0 4 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l1dcache.tags.ageTaskId_1024::3 2 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l1dcache.tags.ratioOccsTaskId::1022 0.976562 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.clusters.l1dcache.tags.ratioOccsTaskId::1024 0.023438 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.clusters.l1dcache.tags.tagAccesses 116804315 # Number of tag accesses (Count)
board.cache_hierarchy.clusters.l1dcache.tags.dataAccesses 116804315 # Number of data accesses (Count)
board.cache_hierarchy.clusters.l1dcache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l1icache.demandHits::processor.cores.core.inst 9904276 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l1icache.demandHits::total 9904276 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l1icache.overallHits::processor.cores.core.inst 9904276 # number of overall hits (Count)
board.cache_hierarchy.clusters.l1icache.overallHits::total 9904276 # number of overall hits (Count)
board.cache_hierarchy.clusters.l1icache.demandMisses::processor.cores.core.inst 11457 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l1icache.demandMisses::total 11457 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l1icache.overallMisses::processor.cores.core.inst 11457 # number of overall misses (Count)
board.cache_hierarchy.clusters.l1icache.overallMisses::total 11457 # number of overall misses (Count)
board.cache_hierarchy.clusters.l1icache.demandMissLatency::processor.cores.core.inst 271980414 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.demandMissLatency::total 271980414 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.overallMissLatency::processor.cores.core.inst 271980414 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.overallMissLatency::total 271980414 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.demandAccesses::processor.cores.core.inst 9915733 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1icache.demandAccesses::total 9915733 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1icache.overallAccesses::processor.cores.core.inst 9915733 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1icache.overallAccesses::total 9915733 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l1icache.demandMissRate::processor.cores.core.inst 0.001155 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.demandMissRate::total 0.001155 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.overallMissRate::processor.cores.core.inst 0.001155 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.overallMissRate::total 0.001155 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.demandAvgMissLatency::processor.cores.core.inst 23739.234878 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.demandAvgMissLatency::total 23739.234878 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.overallAvgMissLatency::processor.cores.core.inst 23739.234878 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.overallAvgMissLatency::total 23739.234878 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.l1icache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.l1icache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.clusters.l1icache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.clusters.l1icache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.l1icache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.l1icache.writebacks::writebacks 203 # number of writebacks (Count)
board.cache_hierarchy.clusters.l1icache.writebacks::total 203 # number of writebacks (Count)
board.cache_hierarchy.clusters.l1icache.demandMshrHits::processor.cores.core.inst 1389 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l1icache.demandMshrHits::total 1389 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l1icache.overallMshrHits::processor.cores.core.inst 1389 # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l1icache.overallMshrHits::total 1389 # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l1icache.demandMshrMisses::processor.cores.core.inst 10068 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l1icache.demandMshrMisses::total 10068 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l1icache.overallMshrMisses::processor.cores.core.inst 10068 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l1icache.overallMshrMisses::total 10068 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l1icache.demandMshrMissLatency::processor.cores.core.inst 219746700 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.demandMshrMissLatency::total 219746700 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.overallMshrMissLatency::processor.cores.core.inst 219746700 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.overallMshrMissLatency::total 219746700 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.demandMshrMissRate::processor.cores.core.inst 0.001015 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.demandMshrMissRate::total 0.001015 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.overallMshrMissRate::processor.cores.core.inst 0.001015 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.overallMshrMissRate::total 0.001015 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.demandAvgMshrMissLatency::processor.cores.core.inst 21826.251490 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.demandAvgMshrMissLatency::total 21826.251490 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.overallAvgMshrMissLatency::processor.cores.core.inst 21826.251490 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.overallAvgMshrMissLatency::total 21826.251490 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.replacements 9794 # number of replacements (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.hits::processor.cores.core.inst 9904276 # number of ReadReq hits (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.hits::total 9904276 # number of ReadReq hits (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.misses::processor.cores.core.inst 11457 # number of ReadReq misses (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.misses::total 11457 # number of ReadReq misses (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.missLatency::processor.cores.core.inst 271980414 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.ReadReq.missLatency::total 271980414 # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.ReadReq.accesses::processor.cores.core.inst 9915733 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.accesses::total 9915733 # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.missRate::processor.cores.core.inst 0.001155 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.ReadReq.missRate::total 0.001155 # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.ReadReq.avgMissLatency::processor.cores.core.inst 23739.234878 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.ReadReq.avgMissLatency::total 23739.234878 # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrHits::processor.cores.core.inst 1389 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrHits::total 1389 # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrMisses::processor.cores.core.inst 10068 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrMisses::total 10068 # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrMissLatency::processor.cores.core.inst 219746700 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrMissLatency::total 219746700 # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrMissRate::processor.cores.core.inst 0.001015 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.ReadReq.mshrMissRate::total 0.001015 # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.clusters.l1icache.ReadReq.avgMshrMissLatency::processor.cores.core.inst 21826.251490 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.ReadReq.avgMshrMissLatency::total 21826.251490 # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l1icache.prefetcher.demandMshrMisses 10068 # demands not covered by prefetchs (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfIssued 0 # number of hwpf issued (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfUseful 0 # number of useful prefetch (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.accuracy nan # accuracy of the prefetcher (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.coverage 0 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfHitInCache 0 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfHitInMSHR 0 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfLate 0 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfIdentified 0 # number of prefetch candidates identified (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfRemovedDemand 0 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfSpanPage 0 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.pfUsefulSpanPage 0 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.clusters.l1icache.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l1icache.tags.tagsInUse 249.632839 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.clusters.l1icache.tags.totalRefs 9914344 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.clusters.l1icache.tags.sampledRefs 10068 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.clusters.l1icache.tags.avgRefs 984.738180 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.clusters.l1icache.tags.warmupTick 261072 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.clusters.l1icache.tags.occupancies::processor.cores.core.inst 249.632839 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l1icache.tags.avgOccs::processor.cores.core.inst 0.975128 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l1icache.tags.avgOccs::total 0.975128 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l1icache.tags.occupanciesTaskId::1024 256 # Occupied blocks per task id (Count)
board.cache_hierarchy.clusters.l1icache.tags.ageTaskId_1024::3 254 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l1icache.tags.ageTaskId_1024::4 2 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l1icache.tags.ratioOccsTaskId::1024 1 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.clusters.l1icache.tags.tagAccesses 79335932 # Number of tag accesses (Count)
board.cache_hierarchy.clusters.l1icache.tags.dataAccesses 79335932 # Number of data accesses (Count)
board.cache_hierarchy.clusters.l1icache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l2_bus.transDist::ReadReq 20852 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::ReadResp 641896 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::WriteReq 2906 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::WriteResp 2906 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::WritebackDirty 1170988 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::CleanEvict 39541 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::HardPFReq 665101 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::UpgradeReq 965 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::UpgradeResp 965 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::ReadExReq 11400 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::ReadExResp 11400 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.transDist::ReadSharedReq 621048 # Transaction distribution (Count)
board.cache_hierarchy.clusters.l2_bus.pktCount_board.cache_hierarchy.clusters.l1dcache.mem_side_port::board.cache_hierarchy.clusters.l2cache.cpu_side_port 1915365 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.clusters.l2_bus.pktCount_board.cache_hierarchy.clusters.l1icache.mem_side_port::board.cache_hierarchy.clusters.l2cache.cpu_side_port 29911 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.clusters.l2_bus.pktCount_board.cache_hierarchy.clusters.iptw_cache.mem_side_port::board.cache_hierarchy.clusters.l2cache.cpu_side_port 26 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.clusters.l2_bus.pktCount_board.cache_hierarchy.clusters.dptw_cache.mem_side_port::board.cache_hierarchy.clusters.l2cache.cpu_side_port 346 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.clusters.l2_bus.pktCount::total 1945648 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.clusters.l2_bus.pktSize_board.cache_hierarchy.clusters.l1dcache.mem_side_port::board.cache_hierarchy.clusters.l2cache.cpu_side_port 78669240 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.clusters.l2_bus.pktSize_board.cache_hierarchy.clusters.l1icache.mem_side_port::board.cache_hierarchy.clusters.l2cache.cpu_side_port 656128 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.clusters.l2_bus.pktSize_board.cache_hierarchy.clusters.iptw_cache.mem_side_port::board.cache_hierarchy.clusters.l2cache.cpu_side_port 512 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.clusters.l2_bus.pktSize_board.cache_hierarchy.clusters.dptw_cache.mem_side_port::board.cache_hierarchy.clusters.l2cache.cpu_side_port 2304 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.clusters.l2_bus.pktSize::total 79328184 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.clusters.l2_bus.snoops 1244320 # Total snoops (Count)
board.cache_hierarchy.clusters.l2_bus.snoopTraffic 36115328 # Total snoop traffic (Byte)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::samples 1901191 # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::mean 0.003033 # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::stdev 0.055634 # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::0 1895493 99.70% 99.70% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::1 5630 0.30% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::2 68 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::3 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::4 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::max_value 2 # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.snoopFanout::total 1901191 # Request fanout histogram (Count)
board.cache_hierarchy.clusters.l2_bus.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l2_bus.reqLayer0.occupancy 1004439353 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.clusters.l2_bus.reqLayer0.utilization 0.1 # Layer utilization (Ratio)
board.cache_hierarchy.clusters.l2_bus.respLayer0.occupancy 636614412 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.clusters.l2_bus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.clusters.l2_bus.respLayer1.occupancy 10060920 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.clusters.l2_bus.respLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.clusters.l2_bus.respLayer2.occupancy 18314 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.clusters.l2_bus.respLayer2.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.clusters.l2_bus.respLayer3.occupancy 298701 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.clusters.l2_bus.respLayer3.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.clusters.l2_bus.snoop_filter.totRequests 1265023 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.clusters.l2_bus.snoop_filter.hitSingleRequests 632304 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.clusters.l2_bus.snoop_filter.hitMultiRequests 1614 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.clusters.l2_bus.snoop_filter.totSnoops 4092 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.clusters.l2_bus.snoop_filter.hitSingleSnoops 4056 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.clusters.l2_bus.snoop_filter.hitMultiSnoops 36 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.clusters.l2cache.demandHits::cache_hierarchy.clusters.l1dcache.prefetcher 55223 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l2cache.demandHits::processor.cores.core.mmu.dtb.walker 12 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l2cache.demandHits::processor.cores.core.mmu.itb.walker 1 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l2cache.demandHits::processor.cores.core.inst 5890 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l2cache.demandHits::processor.cores.core.data 31848 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l2cache.demandHits::total 92974 # number of demand (read+write) hits (Count)
board.cache_hierarchy.clusters.l2cache.overallHits::cache_hierarchy.clusters.l1dcache.prefetcher 55223 # number of overall hits (Count)
board.cache_hierarchy.clusters.l2cache.overallHits::processor.cores.core.mmu.dtb.walker 12 # number of overall hits (Count)
board.cache_hierarchy.clusters.l2cache.overallHits::processor.cores.core.mmu.itb.walker 1 # number of overall hits (Count)
board.cache_hierarchy.clusters.l2cache.overallHits::processor.cores.core.inst 5890 # number of overall hits (Count)
board.cache_hierarchy.clusters.l2cache.overallHits::processor.cores.core.data 31848 # number of overall hits (Count)
board.cache_hierarchy.clusters.l2cache.overallHits::total 92974 # number of overall hits (Count)
board.cache_hierarchy.clusters.l2cache.demandMisses::cache_hierarchy.clusters.l1dcache.prefetcher 517501 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMisses::processor.cores.core.mmu.dtb.walker 22 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMisses::processor.cores.core.mmu.itb.walker 7 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMisses::processor.cores.core.inst 4159 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMisses::processor.cores.core.data 17487 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMisses::total 539176 # number of demand (read+write) misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMisses::cache_hierarchy.clusters.l1dcache.prefetcher 517501 # number of overall misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMisses::processor.cores.core.mmu.dtb.walker 22 # number of overall misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMisses::processor.cores.core.mmu.itb.walker 7 # number of overall misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMisses::processor.cores.core.inst 4159 # number of overall misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMisses::processor.cores.core.data 17487 # number of overall misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMisses::total 539176 # number of overall misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 34965191908 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMissLatency::processor.cores.core.mmu.dtb.walker 607725 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMissLatency::processor.cores.core.mmu.itb.walker 276390 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMissLatency::processor.cores.core.inst 191362779 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMissLatency::processor.cores.core.data 1725227379 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMissLatency::total 36882666181 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 34965191908 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMissLatency::processor.cores.core.mmu.dtb.walker 607725 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMissLatency::processor.cores.core.mmu.itb.walker 276390 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMissLatency::processor.cores.core.inst 191362779 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMissLatency::processor.cores.core.data 1725227379 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMissLatency::total 36882666181 # number of overall miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandAccesses::cache_hierarchy.clusters.l1dcache.prefetcher 572724 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.demandAccesses::processor.cores.core.mmu.dtb.walker 34 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.demandAccesses::processor.cores.core.mmu.itb.walker 8 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.demandAccesses::processor.cores.core.inst 10049 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.demandAccesses::processor.cores.core.data 49335 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.demandAccesses::total 632150 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.overallAccesses::cache_hierarchy.clusters.l1dcache.prefetcher 572724 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.overallAccesses::processor.cores.core.mmu.dtb.walker 34 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.overallAccesses::processor.cores.core.mmu.itb.walker 8 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.overallAccesses::processor.cores.core.inst 10049 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.overallAccesses::processor.cores.core.data 49335 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.overallAccesses::total 632150 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.clusters.l2cache.demandMissRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.903578 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMissRate::processor.cores.core.mmu.dtb.walker 0.647059 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMissRate::processor.cores.core.mmu.itb.walker 0.875000 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMissRate::processor.cores.core.inst 0.413872 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMissRate::processor.cores.core.data 0.354454 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMissRate::total 0.852924 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMissRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.903578 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMissRate::processor.cores.core.mmu.dtb.walker 0.647059 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMissRate::processor.cores.core.mmu.itb.walker 0.875000 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMissRate::processor.cores.core.inst 0.413872 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMissRate::processor.cores.core.data 0.354454 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMissRate::total 0.852924 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandAvgMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 67565.457667 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMissLatency::processor.cores.core.mmu.dtb.walker 27623.863636 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMissLatency::processor.cores.core.mmu.itb.walker 39484.285714 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMissLatency::processor.cores.core.inst 46011.728541 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMissLatency::processor.cores.core.data 98657.710242 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMissLatency::total 68405.615571 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 67565.457667 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMissLatency::processor.cores.core.mmu.dtb.walker 27623.863636 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMissLatency::processor.cores.core.mmu.itb.walker 39484.285714 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMissLatency::processor.cores.core.inst 46011.728541 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMissLatency::processor.cores.core.data 98657.710242 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMissLatency::total 68405.615571 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.l2cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.clusters.l2cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.clusters.l2cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.clusters.l2cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.l2cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.clusters.l2cache.writebacks::writebacks 563983 # number of writebacks (Count)
board.cache_hierarchy.clusters.l2cache.writebacks::total 563983 # number of writebacks (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrHits::cache_hierarchy.clusters.l1dcache.prefetcher 507496 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrHits::processor.cores.core.mmu.itb.walker 1 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrHits::processor.cores.core.data 33 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrHits::total 507530 # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrHits::cache_hierarchy.clusters.l1dcache.prefetcher 507496 # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrHits::processor.cores.core.mmu.itb.walker 1 # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrHits::processor.cores.core.data 33 # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrHits::total 507530 # number of overall MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher 10005 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrMisses::processor.cores.core.mmu.dtb.walker 22 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrMisses::processor.cores.core.mmu.itb.walker 6 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrMisses::processor.cores.core.inst 4159 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrMisses::processor.cores.core.data 17454 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrMisses::total 31646 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher 10005 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrMisses::cache_hierarchy.clusters.l2cache.prefetcher 551048 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrMisses::processor.cores.core.mmu.dtb.walker 22 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrMisses::processor.cores.core.mmu.itb.walker 6 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrMisses::processor.cores.core.inst 4159 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrMisses::processor.cores.core.data 17454 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrMisses::total 582694 # number of overall MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrUncacheable::processor.cores.core.data 23758 # number of overall MSHR uncacheable misses (Count)
board.cache_hierarchy.clusters.l2cache.overallMshrUncacheable::total 23758 # number of overall MSHR uncacheable misses (Count)
board.cache_hierarchy.clusters.l2cache.demandMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 1497248025 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMshrMissLatency::processor.cores.core.mmu.dtb.walker 600399 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMshrMissLatency::processor.cores.core.mmu.itb.walker 263403 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMshrMissLatency::processor.cores.core.inst 189977832 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMshrMissLatency::processor.cores.core.data 1718502777 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMshrMissLatency::total 3406592436 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 1497248025 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 62244379007 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrMissLatency::processor.cores.core.mmu.dtb.walker 600399 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrMissLatency::processor.cores.core.mmu.itb.walker 263403 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrMissLatency::processor.cores.core.inst 189977832 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrMissLatency::processor.cores.core.data 1718502777 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrMissLatency::total 65650971443 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrUncacheableLatency::processor.cores.core.data 4537597527 # number of overall MSHR uncacheable ticks (Tick)
board.cache_hierarchy.clusters.l2cache.overallMshrUncacheableLatency::total 4537597527 # number of overall MSHR uncacheable ticks (Tick)
board.cache_hierarchy.clusters.l2cache.demandMshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.017469 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMshrMissRate::processor.cores.core.mmu.dtb.walker 0.647059 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMshrMissRate::processor.cores.core.mmu.itb.walker 0.750000 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMshrMissRate::processor.cores.core.inst 0.413872 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMshrMissRate::processor.cores.core.data 0.353785 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandMshrMissRate::total 0.050061 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.017469 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMshrMissRate::cache_hierarchy.clusters.l2cache.prefetcher inf # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMshrMissRate::processor.cores.core.mmu.dtb.walker 0.647059 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMshrMissRate::processor.cores.core.mmu.itb.walker 0.750000 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMshrMissRate::processor.cores.core.inst 0.413872 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMshrMissRate::processor.cores.core.data 0.353785 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.overallMshrMissRate::total 0.921765 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.demandAvgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 149649.977511 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMshrMissLatency::processor.cores.core.mmu.dtb.walker 27290.863636 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMshrMissLatency::processor.cores.core.mmu.itb.walker 43900.500000 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMshrMissLatency::processor.cores.core.inst 45678.728541 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMshrMissLatency::processor.cores.core.data 98458.965108 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.demandAvgMshrMissLatency::total 107646.856980 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 149649.977511 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 112956.364975 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrMissLatency::processor.cores.core.mmu.dtb.walker 27290.863636 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrMissLatency::processor.cores.core.mmu.itb.walker 43900.500000 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrMissLatency::processor.cores.core.inst 45678.728541 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrMissLatency::processor.cores.core.data 98458.965108 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrMissLatency::total 112668.006609 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrUncacheableLatency::processor.cores.core.data 190992.403696 # average overall mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.overallAvgMshrUncacheableLatency::total 190992.403696 # average overall mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.replacements 578620 # number of replacements (Count)
board.cache_hierarchy.clusters.l2cache.CleanEvict.mshrMisses::writebacks 923 # number of CleanEvict MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.CleanEvict.mshrMisses::total 923 # number of CleanEvict MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.CleanEvict.mshrMissRate::writebacks inf # mshr miss rate for CleanEvict accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.CleanEvict.mshrMissRate::total inf # mshr miss rate for CleanEvict accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.HardPFReq.mshrMisses::cache_hierarchy.clusters.l2cache.prefetcher 551048 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.HardPFReq.mshrMisses::total 551048 # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.HardPFReq.mshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 62244379007 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.HardPFReq.mshrMissLatency::total 62244379007 # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.HardPFReq.mshrMissRate::cache_hierarchy.clusters.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.HardPFReq.mshrMissRate::total inf # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.HardPFReq.avgMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 112956.364975 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.HardPFReq.avgMshrMissLatency::total 112956.364975 # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadExReq.hits::processor.cores.core.data 1929 # number of ReadExReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.hits::total 1929 # number of ReadExReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.misses::processor.cores.core.data 9470 # number of ReadExReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.misses::total 9470 # number of ReadExReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.missLatency::processor.cores.core.data 1223075367 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadExReq.missLatency::total 1223075367 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadExReq.accesses::processor.cores.core.data 11399 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.accesses::total 11399 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.missRate::processor.cores.core.data 0.830775 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadExReq.missRate::total 0.830775 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadExReq.avgMissLatency::processor.cores.core.data 129152.625871 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadExReq.avgMissLatency::total 129152.625871 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadExReq.mshrMisses::processor.cores.core.data 9470 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.mshrMisses::total 9470 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadExReq.mshrMissLatency::processor.cores.core.data 1219921857 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadExReq.mshrMissLatency::total 1219921857 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadExReq.mshrMissRate::processor.cores.core.data 0.830775 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadExReq.mshrMissRate::total 0.830775 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadExReq.avgMshrMissLatency::processor.cores.core.data 128819.625871 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadExReq.avgMshrMissLatency::total 128819.625871 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadReq.mshrUncacheable::processor.cores.core.data 20852 # number of ReadReq MSHR uncacheable (Count)
board.cache_hierarchy.clusters.l2cache.ReadReq.mshrUncacheable::total 20852 # number of ReadReq MSHR uncacheable (Count)
board.cache_hierarchy.clusters.l2cache.ReadReq.mshrUncacheableLatency::processor.cores.core.data 4537597527 # number of ReadReq MSHR uncacheable ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadReq.mshrUncacheableLatency::total 4537597527 # number of ReadReq MSHR uncacheable ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadReq.avgMshrUncacheableLatency::processor.cores.core.data 217609.703002 # average ReadReq mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadReq.avgMshrUncacheableLatency::total 217609.703002 # average ReadReq mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.hits::cache_hierarchy.clusters.l1dcache.prefetcher 55223 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.hits::processor.cores.core.mmu.dtb.walker 12 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.hits::processor.cores.core.mmu.itb.walker 1 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.hits::processor.cores.core.inst 5890 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.hits::processor.cores.core.data 29919 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.hits::total 91045 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.misses::cache_hierarchy.clusters.l1dcache.prefetcher 517501 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.misses::processor.cores.core.mmu.dtb.walker 22 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.misses::processor.cores.core.mmu.itb.walker 7 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.misses::processor.cores.core.inst 4159 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.misses::processor.cores.core.data 8017 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.misses::total 529706 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missLatency::cache_hierarchy.clusters.l1dcache.prefetcher 34965191908 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missLatency::processor.cores.core.mmu.dtb.walker 607725 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missLatency::processor.cores.core.mmu.itb.walker 276390 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missLatency::processor.cores.core.inst 191362779 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missLatency::processor.cores.core.data 502152012 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missLatency::total 35659590814 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.accesses::cache_hierarchy.clusters.l1dcache.prefetcher 572724 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.accesses::processor.cores.core.mmu.dtb.walker 34 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.accesses::processor.cores.core.mmu.itb.walker 8 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.accesses::processor.cores.core.inst 10049 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.accesses::processor.cores.core.data 37936 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.accesses::total 620751 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.903578 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missRate::processor.cores.core.mmu.dtb.walker 0.647059 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missRate::processor.cores.core.mmu.itb.walker 0.875000 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missRate::processor.cores.core.inst 0.413872 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missRate::processor.cores.core.data 0.211330 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.missRate::total 0.853331 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 67565.457667 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMissLatency::processor.cores.core.mmu.dtb.walker 27623.863636 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMissLatency::processor.cores.core.mmu.itb.walker 39484.285714 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMissLatency::processor.cores.core.inst 46011.728541 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMissLatency::processor.cores.core.data 62635.900212 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMissLatency::total 67319.590139 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrHits::cache_hierarchy.clusters.l1dcache.prefetcher 507496 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrHits::processor.cores.core.mmu.itb.walker 1 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrHits::processor.cores.core.data 33 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrHits::total 507530 # number of ReadSharedReq MSHR hits (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher 10005 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMisses::processor.cores.core.mmu.dtb.walker 22 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMisses::processor.cores.core.mmu.itb.walker 6 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMisses::processor.cores.core.inst 4159 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMisses::processor.cores.core.data 7984 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMisses::total 22176 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 1497248025 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissLatency::processor.cores.core.mmu.dtb.walker 600399 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissLatency::processor.cores.core.mmu.itb.walker 263403 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissLatency::processor.cores.core.inst 189977832 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissLatency::processor.cores.core.data 498580920 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissLatency::total 2186670579 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.017469 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissRate::processor.cores.core.mmu.dtb.walker 0.647059 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissRate::processor.cores.core.mmu.itb.walker 0.750000 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissRate::processor.cores.core.inst 0.413872 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissRate::processor.cores.core.data 0.210460 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.mshrMissRate::total 0.035724 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 149649.977511 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.mmu.dtb.walker 27290.863636 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.mmu.itb.walker 43900.500000 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.inst 45678.728541 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.data 62447.510020 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.ReadSharedReq.avgMshrMissLatency::total 98605.275027 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.UpgradeReq.hits::processor.cores.core.data 951 # number of UpgradeReq hits (Count)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.hits::total 951 # number of UpgradeReq hits (Count)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.misses::processor.cores.core.data 12 # number of UpgradeReq misses (Count)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.misses::total 12 # number of UpgradeReq misses (Count)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.missLatency::processor.cores.core.data 105561 # number of UpgradeReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.missLatency::total 105561 # number of UpgradeReq miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.accesses::processor.cores.core.data 963 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.accesses::total 963 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.missRate::processor.cores.core.data 0.012461 # miss rate for UpgradeReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.missRate::total 0.012461 # miss rate for UpgradeReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.avgMissLatency::processor.cores.core.data 8796.750000 # average UpgradeReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.UpgradeReq.avgMissLatency::total 8796.750000 # average UpgradeReq miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.UpgradeReq.mshrMisses::processor.cores.core.data 12 # number of UpgradeReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.mshrMisses::total 12 # number of UpgradeReq MSHR misses (Count)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.mshrMissLatency::processor.cores.core.data 136530 # number of UpgradeReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.mshrMissLatency::total 136530 # number of UpgradeReq MSHR miss ticks (Tick)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.mshrMissRate::processor.cores.core.data 0.012461 # mshr miss rate for UpgradeReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.mshrMissRate::total 0.012461 # mshr miss rate for UpgradeReq accesses (Ratio)
board.cache_hierarchy.clusters.l2cache.UpgradeReq.avgMshrMissLatency::processor.cores.core.data 11377.500000 # average UpgradeReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.UpgradeReq.avgMshrMissLatency::total 11377.500000 # average UpgradeReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.WriteReq.mshrUncacheable::processor.cores.core.data 2906 # number of WriteReq MSHR uncacheable (Count)
board.cache_hierarchy.clusters.l2cache.WriteReq.mshrUncacheable::total 2906 # number of WriteReq MSHR uncacheable (Count)
board.cache_hierarchy.clusters.l2cache.WritebackDirty.hits::writebacks 606984 # number of WritebackDirty hits (Count)
board.cache_hierarchy.clusters.l2cache.WritebackDirty.hits::total 606984 # number of WritebackDirty hits (Count)
board.cache_hierarchy.clusters.l2cache.WritebackDirty.accesses::writebacks 606984 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.WritebackDirty.accesses::total 606984 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.clusters.l2cache.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l2cache.prefetcher.demandMshrMisses 31646 # demands not covered by prefetchs (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfIssued 2077220 # number of hwpf issued (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfUnused 715 # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfUseful 42799 # number of useful prefetch (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfUsefulButMiss 0 # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.accuracy 0.020604 # accuracy of the prefetcher (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.coverage 0.574908 # coverage brought by this prefetcher (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfHitInCache 66509 # number of prefetches hitting in cache (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfHitInMSHR 1459663 # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfHitInWB 0 # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfLate 1526172 # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfIdentified 2185222 # number of prefetch candidates identified (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfBufferHit 69283 # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfRemovedDemand 25048 # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfSpanPage 89394 # number of prefetches that crossed the page (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.pfUsefulSpanPage 1391 # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.clusters.l2cache.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.clusters.l2cache.tags.tagsInUse 4091.526648 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.clusters.l2cache.tags.totalRefs 1307279 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.clusters.l2cache.tags.sampledRefs 582716 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.clusters.l2cache.tags.avgRefs 2.243424 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.clusters.l2cache.tags.warmupTick 69930 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.clusters.l2cache.tags.occupancies::writebacks 3.179861 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l2cache.tags.occupancies::cache_hierarchy.clusters.l1dcache.prefetcher 116.456379 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l2cache.tags.occupancies::cache_hierarchy.clusters.l2cache.prefetcher 3294.392878 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l2cache.tags.occupancies::processor.cores.core.mmu.dtb.walker 0.636498 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l2cache.tags.occupancies::processor.cores.core.mmu.itb.walker 0.357089 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l2cache.tags.occupancies::processor.cores.core.inst 273.064097 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l2cache.tags.occupancies::processor.cores.core.data 403.439847 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::writebacks 0.000776 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::cache_hierarchy.clusters.l1dcache.prefetcher 0.028432 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::cache_hierarchy.clusters.l2cache.prefetcher 0.804295 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::processor.cores.core.mmu.dtb.walker 0.000155 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::processor.cores.core.mmu.itb.walker 0.000087 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::processor.cores.core.inst 0.066666 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::processor.cores.core.data 0.098496 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.avgOccs::total 0.998908 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.clusters.l2cache.tags.occupanciesTaskId::1022 4025 # Occupied blocks per task id (Count)
board.cache_hierarchy.clusters.l2cache.tags.occupanciesTaskId::1024 71 # Occupied blocks per task id (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1022::0 614 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1022::1 3411 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1024::0 10 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1024::1 53 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1024::2 1 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1024::3 5 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ageTaskId_1024::4 2 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.clusters.l2cache.tags.ratioOccsTaskId::1022 0.982666 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.clusters.l2cache.tags.ratioOccsTaskId::1024 0.017334 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.clusters.l2cache.tags.tagAccesses 20817852 # Number of tag accesses (Count)
board.cache_hierarchy.clusters.l2cache.tags.dataAccesses 20817852 # Number of data accesses (Count)
board.cache_hierarchy.clusters.l2cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iocache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iocache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iocache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.iocache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.iocache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iocache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iocache.replacements 0 # number of replacements (Count)
board.cache_hierarchy.iocache.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iocache.tags.tagsInUse 0 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iocache.tags.totalRefs 0 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iocache.tags.sampledRefs 0 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iocache.tags.avgRefs nan # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iocache.tags.warmupTick 0 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iocache.tags.tagAccesses 0 # Number of tag accesses (Count)
board.cache_hierarchy.iocache.tags.dataAccesses 0 # Number of data accesses (Count)
board.cache_hierarchy.iocache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l3_bus.transDist::ReadReq 20852 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::ReadResp 594067 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::WriteReq 2906 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::WriteResp 2906 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::WritebackDirty 995970 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::CleanEvict 26176 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::UpgradeReq 14 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::UpgradeResp 12 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::ReadExReq 9470 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::ReadExResp 9470 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.transDist::ReadSharedReq 573223 # Transaction distribution (Count)
board.cache_hierarchy.l3_bus.pktCount_board.cache_hierarchy.clusters.l2cache.mem_side_port::board.cache_hierarchy.l3_cache.cpu_side_port 1791229 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.l3_bus.pktSize_board.cache_hierarchy.clusters.l2cache.mem_side_port::board.cache_hierarchy.l3_cache.cpu_side_port 73410616 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.l3_bus.snoops 443839 # Total snoops (Count)
board.cache_hierarchy.l3_bus.snoopTraffic 27647168 # Total snoop traffic (Byte)
board.cache_hierarchy.l3_bus.snoopFanout::samples 1050302 # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::mean 0.000285 # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::stdev 0.016870 # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::0 1050003 99.97% 99.97% # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::1 299 0.03% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::max_value 1 # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.snoopFanout::total 1050302 # Request fanout histogram (Count)
board.cache_hierarchy.l3_bus.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l3_bus.reqLayer0.occupancy 912302821 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l3_bus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l3_bus.respLayer0.occupancy 596961441 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.l3_bus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.l3_bus.snoop_filter.totRequests 1161016 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.l3_bus.snoop_filter.hitSingleRequests 578351 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l3_bus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l3_bus.snoop_filter.totSnoops 299 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.l3_bus.snoop_filter.hitSingleSnoops 299 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.l3_bus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.l3_cache.demandHits::cache_hierarchy.clusters.l1dcache.prefetcher 274 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l3_cache.demandHits::cache_hierarchy.clusters.l2cache.prefetcher 4962 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l3_cache.demandHits::processor.cores.core.mmu.dtb.walker 16 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l3_cache.demandHits::processor.cores.core.mmu.itb.walker 2 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l3_cache.demandHits::processor.cores.core.inst 1259 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l3_cache.demandHits::processor.cores.core.data 1264 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l3_cache.demandHits::total 7777 # number of demand (read+write) hits (Count)
board.cache_hierarchy.l3_cache.overallHits::cache_hierarchy.clusters.l1dcache.prefetcher 274 # number of overall hits (Count)
board.cache_hierarchy.l3_cache.overallHits::cache_hierarchy.clusters.l2cache.prefetcher 4962 # number of overall hits (Count)
board.cache_hierarchy.l3_cache.overallHits::processor.cores.core.mmu.dtb.walker 16 # number of overall hits (Count)
board.cache_hierarchy.l3_cache.overallHits::processor.cores.core.mmu.itb.walker 2 # number of overall hits (Count)
board.cache_hierarchy.l3_cache.overallHits::processor.cores.core.inst 1259 # number of overall hits (Count)
board.cache_hierarchy.l3_cache.overallHits::processor.cores.core.data 1264 # number of overall hits (Count)
board.cache_hierarchy.l3_cache.overallHits::total 7777 # number of overall hits (Count)
board.cache_hierarchy.l3_cache.demandMisses::cache_hierarchy.clusters.l1dcache.prefetcher 12235 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l3_cache.demandMisses::cache_hierarchy.clusters.l2cache.prefetcher 543581 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l3_cache.demandMisses::processor.cores.core.mmu.dtb.walker 6 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l3_cache.demandMisses::processor.cores.core.mmu.itb.walker 4 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l3_cache.demandMisses::processor.cores.core.inst 2900 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l3_cache.demandMisses::processor.cores.core.data 16190 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l3_cache.demandMisses::total 574916 # number of demand (read+write) misses (Count)
board.cache_hierarchy.l3_cache.overallMisses::cache_hierarchy.clusters.l1dcache.prefetcher 12235 # number of overall misses (Count)
board.cache_hierarchy.l3_cache.overallMisses::cache_hierarchy.clusters.l2cache.prefetcher 543581 # number of overall misses (Count)
board.cache_hierarchy.l3_cache.overallMisses::processor.cores.core.mmu.dtb.walker 6 # number of overall misses (Count)
board.cache_hierarchy.l3_cache.overallMisses::processor.cores.core.mmu.itb.walker 4 # number of overall misses (Count)
board.cache_hierarchy.l3_cache.overallMisses::processor.cores.core.inst 2900 # number of overall misses (Count)
board.cache_hierarchy.l3_cache.overallMisses::processor.cores.core.data 16190 # number of overall misses (Count)
board.cache_hierarchy.l3_cache.overallMisses::total 574916 # number of overall misses (Count)
board.cache_hierarchy.l3_cache.demandMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 1453423651 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 61985356470 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMissLatency::processor.cores.core.mmu.dtb.walker 399600 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMissLatency::processor.cores.core.mmu.itb.walker 224775 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMissLatency::processor.cores.core.inst 164517651 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMissLatency::processor.cores.core.data 1639394298 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMissLatency::total 65243316445 # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 1453423651 # number of overall miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 61985356470 # number of overall miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMissLatency::processor.cores.core.mmu.dtb.walker 399600 # number of overall miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMissLatency::processor.cores.core.mmu.itb.walker 224775 # number of overall miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMissLatency::processor.cores.core.inst 164517651 # number of overall miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMissLatency::processor.cores.core.data 1639394298 # number of overall miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMissLatency::total 65243316445 # number of overall miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandAccesses::cache_hierarchy.clusters.l1dcache.prefetcher 12509 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.demandAccesses::cache_hierarchy.clusters.l2cache.prefetcher 548543 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.demandAccesses::processor.cores.core.mmu.dtb.walker 22 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.demandAccesses::processor.cores.core.mmu.itb.walker 6 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.demandAccesses::processor.cores.core.inst 4159 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.demandAccesses::processor.cores.core.data 17454 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.demandAccesses::total 582693 # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.overallAccesses::cache_hierarchy.clusters.l1dcache.prefetcher 12509 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.overallAccesses::cache_hierarchy.clusters.l2cache.prefetcher 548543 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.overallAccesses::processor.cores.core.mmu.dtb.walker 22 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.overallAccesses::processor.cores.core.mmu.itb.walker 6 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.overallAccesses::processor.cores.core.inst 4159 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.overallAccesses::processor.cores.core.data 17454 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.overallAccesses::total 582693 # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l3_cache.demandMissRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.978096 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMissRate::cache_hierarchy.clusters.l2cache.prefetcher 0.990954 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMissRate::processor.cores.core.mmu.dtb.walker 0.272727 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMissRate::processor.cores.core.mmu.itb.walker 0.666667 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMissRate::processor.cores.core.inst 0.697283 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMissRate::processor.cores.core.data 0.927581 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMissRate::total 0.986653 # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMissRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.978096 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMissRate::cache_hierarchy.clusters.l2cache.prefetcher 0.990954 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMissRate::processor.cores.core.mmu.dtb.walker 0.272727 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMissRate::processor.cores.core.mmu.itb.walker 0.666667 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMissRate::processor.cores.core.inst 0.697283 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMissRate::processor.cores.core.data 0.927581 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMissRate::total 0.986653 # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.demandAvgMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 118792.288598 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 114031.499390 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMissLatency::processor.cores.core.mmu.dtb.walker 66600 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMissLatency::processor.cores.core.mmu.itb.walker 56193.750000 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMissLatency::processor.cores.core.inst 56730.224483 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMissLatency::processor.cores.core.data 101259.684867 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMissLatency::total 113483.215713 # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 118792.288598 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 114031.499390 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMissLatency::processor.cores.core.mmu.dtb.walker 66600 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMissLatency::processor.cores.core.mmu.itb.walker 56193.750000 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMissLatency::processor.cores.core.inst 56730.224483 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMissLatency::processor.cores.core.data 101259.684867 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMissLatency::total 113483.215713 # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.blockedCycles::no_mshrs 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l3_cache.blockedCycles::no_targets 0 # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l3_cache.blockedCauses::no_mshrs 0 # number of times access was blocked (Count)
board.cache_hierarchy.l3_cache.blockedCauses::no_targets 0 # number of times access was blocked (Count)
board.cache_hierarchy.l3_cache.avgBlocked::no_mshrs nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l3_cache.avgBlocked::no_targets nan # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l3_cache.writebacks::writebacks 431987 # number of writebacks (Count)
board.cache_hierarchy.l3_cache.writebacks::total 431987 # number of writebacks (Count)
board.cache_hierarchy.l3_cache.demandMshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher 12235 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l3_cache.demandMshrMisses::cache_hierarchy.clusters.l2cache.prefetcher 543581 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l3_cache.demandMshrMisses::processor.cores.core.mmu.dtb.walker 6 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l3_cache.demandMshrMisses::processor.cores.core.mmu.itb.walker 4 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l3_cache.demandMshrMisses::processor.cores.core.inst 2900 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l3_cache.demandMshrMisses::processor.cores.core.data 16190 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l3_cache.demandMshrMisses::total 574916 # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher 12235 # number of overall MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrMisses::cache_hierarchy.clusters.l2cache.prefetcher 543581 # number of overall MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrMisses::processor.cores.core.mmu.dtb.walker 6 # number of overall MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrMisses::processor.cores.core.mmu.itb.walker 4 # number of overall MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrMisses::processor.cores.core.inst 2900 # number of overall MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrMisses::processor.cores.core.data 16190 # number of overall MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrMisses::total 574916 # number of overall MSHR misses (Count)
board.cache_hierarchy.l3_cache.overallMshrUncacheable::processor.cores.core.data 23758 # number of overall MSHR uncacheable misses (Count)
board.cache_hierarchy.l3_cache.overallMshrUncacheable::total 23758 # number of overall MSHR uncacheable misses (Count)
board.cache_hierarchy.l3_cache.demandMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 1449349396 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 61804346661 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMshrMissLatency::processor.cores.core.mmu.dtb.walker 397602 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMshrMissLatency::processor.cores.core.mmu.itb.walker 223443 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMshrMissLatency::processor.cores.core.inst 163551951 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMshrMissLatency::processor.cores.core.data 1634003028 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.demandMshrMissLatency::total 65051872081 # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 1449349396 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 61804346661 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrMissLatency::processor.cores.core.mmu.dtb.walker 397602 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrMissLatency::processor.cores.core.mmu.itb.walker 223443 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrMissLatency::processor.cores.core.inst 163551951 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrMissLatency::processor.cores.core.data 1634003028 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrMissLatency::total 65051872081 # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrUncacheableLatency::processor.cores.core.data 4440385503 # number of overall MSHR uncacheable ticks (Tick)
board.cache_hierarchy.l3_cache.overallMshrUncacheableLatency::total 4440385503 # number of overall MSHR uncacheable ticks (Tick)
board.cache_hierarchy.l3_cache.demandMshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.978096 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMshrMissRate::cache_hierarchy.clusters.l2cache.prefetcher 0.990954 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMshrMissRate::processor.cores.core.mmu.dtb.walker 0.272727 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMshrMissRate::processor.cores.core.mmu.itb.walker 0.666667 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMshrMissRate::processor.cores.core.inst 0.697283 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMshrMissRate::processor.cores.core.data 0.927581 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.demandMshrMissRate::total 0.986653 # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.978096 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMshrMissRate::cache_hierarchy.clusters.l2cache.prefetcher 0.990954 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMshrMissRate::processor.cores.core.mmu.dtb.walker 0.272727 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMshrMissRate::processor.cores.core.mmu.itb.walker 0.666667 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMshrMissRate::processor.cores.core.inst 0.697283 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMshrMissRate::processor.cores.core.data 0.927581 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.overallMshrMissRate::total 0.986653 # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l3_cache.demandAvgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 118459.288598 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 113698.504291 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMshrMissLatency::processor.cores.core.mmu.dtb.walker 66267 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMshrMissLatency::processor.cores.core.mmu.itb.walker 55860.750000 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMshrMissLatency::processor.cores.core.inst 56397.224483 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMshrMissLatency::processor.cores.core.data 100926.684867 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.demandAvgMshrMissLatency::total 113150.220347 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 118459.288598 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 113698.504291 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrMissLatency::processor.cores.core.mmu.dtb.walker 66267 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrMissLatency::processor.cores.core.mmu.itb.walker 55860.750000 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrMissLatency::processor.cores.core.inst 56397.224483 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrMissLatency::processor.cores.core.data 100926.684867 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrMissLatency::total 113150.220347 # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrUncacheableLatency::processor.cores.core.data 186900.644120 # average overall mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.l3_cache.overallAvgMshrUncacheableLatency::total 186900.644120 # average overall mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.l3_cache.replacements 443837 # number of replacements (Count)
board.cache_hierarchy.l3_cache.CleanEvict.mshrMisses::writebacks 2 # number of CleanEvict MSHR misses (Count)
board.cache_hierarchy.l3_cache.CleanEvict.mshrMisses::total 2 # number of CleanEvict MSHR misses (Count)
board.cache_hierarchy.l3_cache.CleanEvict.mshrMissRate::writebacks inf # mshr miss rate for CleanEvict accesses (Ratio)
board.cache_hierarchy.l3_cache.CleanEvict.mshrMissRate::total inf # mshr miss rate for CleanEvict accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadExReq.hits::processor.cores.core.data 351 # number of ReadExReq hits (Count)
board.cache_hierarchy.l3_cache.ReadExReq.hits::total 351 # number of ReadExReq hits (Count)
board.cache_hierarchy.l3_cache.ReadExReq.misses::processor.cores.core.data 9119 # number of ReadExReq misses (Count)
board.cache_hierarchy.l3_cache.ReadExReq.misses::total 9119 # number of ReadExReq misses (Count)
board.cache_hierarchy.l3_cache.ReadExReq.missLatency::processor.cores.core.data 1179465021 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadExReq.missLatency::total 1179465021 # number of ReadExReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadExReq.accesses::processor.cores.core.data 9470 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadExReq.accesses::total 9470 # number of ReadExReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadExReq.missRate::processor.cores.core.data 0.962936 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadExReq.missRate::total 0.962936 # miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadExReq.avgMissLatency::processor.cores.core.data 129341.487115 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadExReq.avgMissLatency::total 129341.487115 # average ReadExReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadExReq.mshrMisses::processor.cores.core.data 9119 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadExReq.mshrMisses::total 9119 # number of ReadExReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadExReq.mshrMissLatency::processor.cores.core.data 1176428394 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadExReq.mshrMissLatency::total 1176428394 # number of ReadExReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadExReq.mshrMissRate::processor.cores.core.data 0.962936 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadExReq.mshrMissRate::total 0.962936 # mshr miss rate for ReadExReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadExReq.avgMshrMissLatency::processor.cores.core.data 129008.487115 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadExReq.avgMshrMissLatency::total 129008.487115 # average ReadExReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadReq.mshrUncacheable::processor.cores.core.data 20852 # number of ReadReq MSHR uncacheable (Count)
board.cache_hierarchy.l3_cache.ReadReq.mshrUncacheable::total 20852 # number of ReadReq MSHR uncacheable (Count)
board.cache_hierarchy.l3_cache.ReadReq.mshrUncacheableLatency::processor.cores.core.data 4440385503 # number of ReadReq MSHR uncacheable ticks (Tick)
board.cache_hierarchy.l3_cache.ReadReq.mshrUncacheableLatency::total 4440385503 # number of ReadReq MSHR uncacheable ticks (Tick)
board.cache_hierarchy.l3_cache.ReadReq.avgMshrUncacheableLatency::processor.cores.core.data 212947.703002 # average ReadReq mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadReq.avgMshrUncacheableLatency::total 212947.703002 # average ReadReq mshr uncacheable latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.hits::cache_hierarchy.clusters.l1dcache.prefetcher 274 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.hits::cache_hierarchy.clusters.l2cache.prefetcher 4962 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.hits::processor.cores.core.mmu.dtb.walker 16 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.hits::processor.cores.core.mmu.itb.walker 2 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.hits::processor.cores.core.inst 1259 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.hits::processor.cores.core.data 913 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.hits::total 7426 # number of ReadSharedReq hits (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.misses::cache_hierarchy.clusters.l1dcache.prefetcher 12235 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.misses::cache_hierarchy.clusters.l2cache.prefetcher 543581 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.misses::processor.cores.core.mmu.dtb.walker 6 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.misses::processor.cores.core.mmu.itb.walker 4 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.misses::processor.cores.core.inst 2900 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.misses::processor.cores.core.data 7071 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.misses::total 565797 # number of ReadSharedReq misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.missLatency::cache_hierarchy.clusters.l1dcache.prefetcher 1453423651 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.missLatency::cache_hierarchy.clusters.l2cache.prefetcher 61985356470 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.missLatency::processor.cores.core.mmu.dtb.walker 399600 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.missLatency::processor.cores.core.mmu.itb.walker 224775 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.missLatency::processor.cores.core.inst 164517651 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.missLatency::processor.cores.core.data 459929277 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.missLatency::total 64063851424 # number of ReadSharedReq miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.accesses::cache_hierarchy.clusters.l1dcache.prefetcher 12509 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.accesses::cache_hierarchy.clusters.l2cache.prefetcher 548543 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.accesses::processor.cores.core.mmu.dtb.walker 22 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.accesses::processor.cores.core.mmu.itb.walker 6 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.accesses::processor.cores.core.inst 4159 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.accesses::processor.cores.core.data 7984 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.accesses::total 573223 # number of ReadSharedReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.missRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.978096 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.missRate::cache_hierarchy.clusters.l2cache.prefetcher 0.990954 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.missRate::processor.cores.core.mmu.dtb.walker 0.272727 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.missRate::processor.cores.core.mmu.itb.walker 0.666667 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.missRate::processor.cores.core.inst 0.697283 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.missRate::processor.cores.core.data 0.885646 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.missRate::total 0.987045 # miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 118792.288598 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 114031.499390 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMissLatency::processor.cores.core.mmu.dtb.walker 66600 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMissLatency::processor.cores.core.mmu.itb.walker 56193.750000 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMissLatency::processor.cores.core.inst 56730.224483 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMissLatency::processor.cores.core.data 65044.445906 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMissLatency::total 113227.626559 # average ReadSharedReq miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMisses::cache_hierarchy.clusters.l1dcache.prefetcher 12235 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMisses::cache_hierarchy.clusters.l2cache.prefetcher 543581 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMisses::processor.cores.core.mmu.dtb.walker 6 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMisses::processor.cores.core.mmu.itb.walker 4 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMisses::processor.cores.core.inst 2900 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMisses::processor.cores.core.data 7071 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMisses::total 565797 # number of ReadSharedReq MSHR misses (Count)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 1449349396 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 61804346661 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissLatency::processor.cores.core.mmu.dtb.walker 397602 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissLatency::processor.cores.core.mmu.itb.walker 223443 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissLatency::processor.cores.core.inst 163551951 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissLatency::processor.cores.core.data 457574634 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissLatency::total 63875443687 # number of ReadSharedReq MSHR miss ticks (Tick)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissRate::cache_hierarchy.clusters.l1dcache.prefetcher 0.978096 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissRate::cache_hierarchy.clusters.l2cache.prefetcher 0.990954 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissRate::processor.cores.core.mmu.dtb.walker 0.272727 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissRate::processor.cores.core.mmu.itb.walker 0.666667 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissRate::processor.cores.core.inst 0.697283 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissRate::processor.cores.core.data 0.885646 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.mshrMissRate::total 0.987045 # mshr miss rate for ReadSharedReq accesses (Ratio)
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.clusters.l1dcache.prefetcher 118459.288598 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMshrMissLatency::cache_hierarchy.clusters.l2cache.prefetcher 113698.504291 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.mmu.dtb.walker 66267 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.mmu.itb.walker 55860.750000 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.inst 56397.224483 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMshrMissLatency::processor.cores.core.data 64711.445906 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.ReadSharedReq.avgMshrMissLatency::total 112894.631267 # average ReadSharedReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l3_cache.UpgradeReq.hits::processor.cores.core.data 12 # number of UpgradeReq hits (Count)
board.cache_hierarchy.l3_cache.UpgradeReq.hits::total 12 # number of UpgradeReq hits (Count)
board.cache_hierarchy.l3_cache.UpgradeReq.accesses::processor.cores.core.data 12 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.UpgradeReq.accesses::total 12 # number of UpgradeReq accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.WriteReq.mshrUncacheable::processor.cores.core.data 2906 # number of WriteReq MSHR uncacheable (Count)
board.cache_hierarchy.l3_cache.WriteReq.mshrUncacheable::total 2906 # number of WriteReq MSHR uncacheable (Count)
board.cache_hierarchy.l3_cache.WritebackDirty.hits::writebacks 563983 # number of WritebackDirty hits (Count)
board.cache_hierarchy.l3_cache.WritebackDirty.hits::total 563983 # number of WritebackDirty hits (Count)
board.cache_hierarchy.l3_cache.WritebackDirty.accesses::writebacks 563983 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.WritebackDirty.accesses::total 563983 # number of WritebackDirty accesses(hits+misses) (Count)
board.cache_hierarchy.l3_cache.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l3_cache.tags.tagsInUse 106103.596001 # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l3_cache.tags.totalRefs 1161004 # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l3_cache.tags.sampledRefs 574909 # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l3_cache.tags.avgRefs 2.019457 # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l3_cache.tags.warmupTick 69264 # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l3_cache.tags.occupancies::writebacks 0.101073 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l3_cache.tags.occupancies::cache_hierarchy.clusters.l1dcache.prefetcher 4099.493521 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l3_cache.tags.occupancies::cache_hierarchy.clusters.l2cache.prefetcher 96038.104788 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l3_cache.tags.occupancies::processor.cores.core.mmu.dtb.walker 3.333852 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l3_cache.tags.occupancies::processor.cores.core.mmu.itb.walker 2.500537 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l3_cache.tags.occupancies::processor.cores.core.inst 982.165208 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l3_cache.tags.occupancies::processor.cores.core.data 4977.897022 # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::writebacks 0.000001 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::cache_hierarchy.clusters.l1dcache.prefetcher 0.031277 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::cache_hierarchy.clusters.l2cache.prefetcher 0.732713 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::processor.cores.core.mmu.dtb.walker 0.000025 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::processor.cores.core.mmu.itb.walker 0.000019 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::processor.cores.core.inst 0.007493 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::processor.cores.core.data 0.037978 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.avgOccs::total 0.809506 # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l3_cache.tags.occupanciesTaskId::1022 129023 # Occupied blocks per task id (Count)
board.cache_hierarchy.l3_cache.tags.occupanciesTaskId::1024 2049 # Occupied blocks per task id (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1022::0 613 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1022::1 5470 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1022::2 54524 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1022::3 68416 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1024::0 10 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1024::1 87 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1024::2 865 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ageTaskId_1024::3 1087 # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l3_cache.tags.ratioOccsTaskId::1022 0.984367 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l3_cache.tags.ratioOccsTaskId::1024 0.015633 # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l3_cache.tags.tagAccesses 19151133 # Number of tag accesses (Count)
board.cache_hierarchy.l3_cache.tags.dataAccesses 19151133 # Number of data accesses (Count)
board.cache_hierarchy.l3_cache.tags.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.transDist::ReadReq 20852 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadResp 586641 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WriteReq 2906 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WriteResp 2906 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WritebackDirty 431987 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::CleanEvict 11574 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::UpgradeReq 2 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq 9119 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp 9119 # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq 565795 # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l3_cache.mem_side_port::board.bridge.cpu_side_port 47512 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l3_cache.mem_side_port::board.memory.mem_ctrl.port 1593385 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l3_cache.mem_side_port::board.processor.cores.core.interrupts.pio 4 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l3_cache.mem_side_port::total 1640901 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total 1640901 # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l3_cache.mem_side_port::board.bridge.cpu_side_port 23856 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l3_cache.mem_side_port::board.memory.mem_ctrl.port 64441280 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l3_cache.mem_side_port::board.processor.cores.core.interrupts.pio 8 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l3_cache.mem_side_port::total 64465144 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total 64465144 # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops 2 # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic 0 # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples 598674 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows 0 0.00% 0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0 598674 100.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::2 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows 0 0.00% 100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value 0 # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total 598674 # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy 8878446 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.reqLayer1.occupancy 485494877 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer1.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.reqLayer2.occupancy 666 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer2.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer2.occupancy 496547619 # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer2.utilization 0.0 # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests 1018477 # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests 443563 # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops 0 # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock 333 # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage 1 # Voltage in Volts (Volt)
board.iobus.transDist::ReadReq 20850 # Transaction distribution (Count)
board.iobus.transDist::ReadResp 20850 # Transaction distribution (Count)
board.iobus.transDist::WriteReq 2906 # Transaction distribution (Count)
board.iobus.transDist::WriteResp 2906 # Transaction distribution (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.south_bridge.pit.pio 35846 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.south_bridge.speaker.pio 4 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.com_1.pio 11594 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::board.pc.pci_host.pio 68 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount_board.bridge.mem_side_port::total 47512 # Packet count per connected requestor and responder (Count)
board.iobus.pktCount::total 47512 # Packet count per connected requestor and responder (Count)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.south_bridge.pit.pio 17923 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.south_bridge.speaker.pio 2 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.com_1.pio 5797 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::board.pc.pci_host.pio 134 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize_board.bridge.mem_side_port::total 23856 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.pktSize::total 23856 # Cumulative packet size per connected requestor and responder (Byte)
board.iobus.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.iobus.reqLayer10.occupancy 2896767 # Layer occupancy (ticks) (Tick)
board.iobus.reqLayer10.utilization 0.0 # Layer utilization (Ratio)
board.iobus.reqLayer15.occupancy 11322 # Layer occupancy (ticks) (Tick)
board.iobus.reqLayer15.utilization 0.0 # Layer utilization (Ratio)
board.iobus.reqLayer7.occupancy 5969358 # Layer occupancy (ticks) (Tick)
board.iobus.reqLayer7.utilization 0.0 # Layer utilization (Ratio)
board.iobus.reqLayer8.occupancy 999 # Layer occupancy (ticks) (Tick)
board.iobus.reqLayer8.utilization 0.0 # Layer utilization (Ratio)
board.iobus.respLayer0.occupancy 20381337 # Layer occupancy (ticks) (Tick)
board.iobus.respLayer0.utilization 0.0 # Layer utilization (Ratio)
board.memory.mem_ctrl.avgPriority_writebacks::samples 431987.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_cache_hierarchy.clusters.l1dcache.prefetcher::samples 12235.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_cache_hierarchy.clusters.l2cache.prefetcher::samples 543577.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.mmu.dtb.walker::samples 6.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.mmu.itb.walker::samples 4.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.inst::samples 2900.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.data::samples 16190.00 # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.priorityMinLatency 0.000000017492 # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl.priorityMaxLatency 0.011839300920 # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl.numReadWriteTurnArounds 26968 # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl.numWriteReadTurnArounds 26968 # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl.numStayReadState 1164199 # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl.numStayWriteState 406384 # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl.readReqs 574914 # Number of read requests accepted (Count)
board.memory.mem_ctrl.writeReqs 431987 # Number of write requests accepted (Count)
board.memory.mem_ctrl.readBursts 574914 # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl.writeBursts 431987 # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl.servicedByWrQ 2 # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl.mergedWrBursts 0 # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl.avgRdQLen 3.58 # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.avgWrQLen 31.19 # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::6 574914 # Read request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::6 431987 # Write request sizes (log2) (Count)
board.memory.mem_ctrl.rdQLenPdf::0 27858 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::1 69883 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::2 69034 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::3 173728 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::4 52565 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::5 50524 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::6 44769 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::7 50884 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::8 33775 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::9 417 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::10 427 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::11 464 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::12 330 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::13 117 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::14 83 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::15 27 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::16 22 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::17 5 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::32 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::33 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::34 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::35 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::36 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::37 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::38 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::39 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::40 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::41 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::42 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::43 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::44 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::45 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::46 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::47 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::48 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::49 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::50 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::51 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::52 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::53 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::54 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::55 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::56 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::57 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::58 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::59 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::60 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::61 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::62 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::63 0 # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::17 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::18 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::19 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::20 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::21 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::22 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::23 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::24 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::25 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::26 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::27 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::28 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::29 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::30 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::31 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::32 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::33 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::34 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::35 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::36 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::37 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::38 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::39 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::40 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::41 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::42 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::43 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::44 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::45 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::46 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::47 15 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::48 27 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::49 509 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::50 2134 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::51 3661 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::52 4303 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::53 8929 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::54 15669 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::55 26189 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::56 50519 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::57 51686 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::58 37343 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::59 37561 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::60 40433 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::61 36442 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::62 52492 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::63 33223 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::64 28261 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::65 994 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::66 800 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::67 403 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::68 218 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::69 86 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::70 33 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::71 9 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::72 1 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::73 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::74 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::75 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::76 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::77 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::78 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::79 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::80 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::81 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::82 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::83 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::84 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::85 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::86 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::87 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::88 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::89 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::90 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::91 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::92 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::93 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::94 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::95 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::96 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::97 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::98 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::99 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::100 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::101 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::102 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::103 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::104 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::105 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::106 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::107 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::108 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::109 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::110 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::111 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::112 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::113 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::114 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::115 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::116 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::117 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::118 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::119 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::120 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::121 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::122 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::123 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::124 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::125 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::126 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::127 0 # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdPerTurnAround::samples 26968 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::mean 21.317747 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::gmean 16.120321 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::stdev 646.712946 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::0-2047 26967 100.00% 100.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::104448-106495 1 0.00% 100.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::total 26968 # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.wrPerTurnAround::samples 26968 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::mean 16.016316 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::gmean 16.014590 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::stdev 0.258129 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::16 26821 99.45% 99.45% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::17 30 0.11% 99.57% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::18 46 0.17% 99.74% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::19 17 0.06% 99.80% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::20 29 0.11% 99.91% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::21 10 0.04% 99.94% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::22 12 0.04% 99.99% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::23 1 0.00% 99.99% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::27 2 0.01% 100.00% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::total 26968 # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.bytesReadWrQ 128 # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl.bytesReadSys 36794496 # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl.bytesWrittenSys 27647168 # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl.avgRdBWSys 1839724800.00000000 # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.avgWrBWSys 1382358400.00000000 # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.totGap 19999986321 # Total gap between requests (Tick)
board.memory.mem_ctrl.avgGap 19862.91 # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl.requestorReadBytes::cache_hierarchy.clusters.l1dcache.prefetcher 783040 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::cache_hierarchy.clusters.l2cache.prefetcher 34788928 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.mmu.dtb.walker 384 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.mmu.itb.walker 256 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.inst 185600 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.data 1036160 # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorWriteBytes::writebacks 27643392 # Per-requestor bytes write to memory (Byte)
board.memory.mem_ctrl.requestorReadRate::cache_hierarchy.clusters.l1dcache.prefetcher 39152000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::cache_hierarchy.clusters.l2cache.prefetcher 1739446400.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.mmu.dtb.walker 19200.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.mmu.itb.walker 12800.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.inst 9280000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.data 51808000.000000000000 # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorWriteRate::writebacks 1382169600.000000000000 # Per-requestor bytes write to memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadAccesses::cache_hierarchy.clusters.l1dcache.prefetcher 12235 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::cache_hierarchy.clusters.l2cache.prefetcher 543579 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.mmu.dtb.walker 6 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.mmu.itb.walker 4 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.inst 2900 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.data 16190 # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorWriteAccesses::writebacks 431987 # Per-requestor write serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadTotalLat::cache_hierarchy.clusters.l1dcache.prefetcher 1074099832 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::cache_hierarchy.clusters.l2cache.prefetcher 44945685186 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.mmu.dtb.walker 214801 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.mmu.itb.walker 101459 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.inst 75136195 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.data 1139962650 # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorWriteTotalLat::writebacks 625039619340 # Per-requestor write total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadAvgLat::cache_hierarchy.clusters.l1dcache.prefetcher 87789.12 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::cache_hierarchy.clusters.l2cache.prefetcher 82684.73 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.mmu.dtb.walker 35800.17 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.mmu.itb.walker 25364.75 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.inst 25909.03 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.data 70411.53 # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorWriteAvgLat::writebacks 1446894.51 # Per-requestor write average memory access latency ((Tick/Count))
board.memory.mem_ctrl.dram.bytesRead::cache_hierarchy.clusters.l1dcache.prefetcher 783040 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::cache_hierarchy.clusters.l2cache.prefetcher 34788736 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.mmu.dtb.walker 384 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.mmu.itb.walker 256 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.inst 185600 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.data 1036160 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::total 36794176 # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::processor.cores.core.inst 185600 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::total 185600 # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesWritten::writebacks 27647168 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl.dram.bytesWritten::total 27647168 # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl.dram.numReads::cache_hierarchy.clusters.l1dcache.prefetcher 12235 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::cache_hierarchy.clusters.l2cache.prefetcher 543574 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.mmu.dtb.walker 6 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.mmu.itb.walker 4 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.inst 2900 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.data 16190 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::total 574909 # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numWrites::writebacks 431987 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numWrites::total 431987 # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.bwRead::cache_hierarchy.clusters.l1dcache.prefetcher 39152000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::cache_hierarchy.clusters.l2cache.prefetcher 1739436800 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.mmu.dtb.walker 19200 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.mmu.itb.walker 12800 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.inst 9280000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.data 51808000 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::total 1839708800 # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::processor.cores.core.inst 9280000 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::total 9280000 # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwWrite::writebacks 1382358400 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwWrite::total 1382358400 # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::writebacks 1382358400 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::cache_hierarchy.clusters.l1dcache.prefetcher 39152000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::cache_hierarchy.clusters.l2cache.prefetcher 1739436800 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.mmu.dtb.walker 19200 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.mmu.itb.walker 12800 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.inst 9280000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.data 51808000 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::total 3222067200 # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.readBursts 574912 # Number of DRAM read bursts (Count)
board.memory.mem_ctrl.dram.writeBursts 431928 # Number of DRAM write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::0 17926 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::1 18027 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::2 17993 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::3 17925 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::4 17747 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::5 17705 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::6 17820 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::7 17810 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::8 17850 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::9 17845 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::10 17904 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::11 17889 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::12 17737 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::13 17753 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::14 18033 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::15 18158 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::16 18144 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::17 18146 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::18 17927 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::19 17862 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::20 17960 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::21 18063 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::22 18265 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::23 18282 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::24 18069 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::25 18112 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::26 18046 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::27 18022 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::28 18043 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::29 18164 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::30 17967 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::31 17718 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::0 13274 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::1 13435 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::2 13361 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::3 13221 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::4 13141 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::5 13163 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::6 13315 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::7 13283 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::8 13389 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::9 13355 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::10 13366 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::11 13399 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::12 13323 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::13 13328 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::14 13598 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::15 13697 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::16 13799 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::17 13811 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::18 13601 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::19 13536 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::20 13623 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::21 13737 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::22 13828 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::23 13869 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::24 13676 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::25 13584 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::26 13577 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::27 13609 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::28 13670 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::29 13714 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::30 13395 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::31 13251 # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.totQLat 37178839419 # Total ticks spent queuing (Tick)
board.memory.mem_ctrl.dram.totBusLat 1915606784 # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl.dram.totMemAccLat 47235200123 # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl.dram.avgQLat 64668.75 # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgBusLat 3332.00 # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgMemAccLat 82160.75 # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.readRowHits 526289 # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl.dram.writeRowHits 386113 # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl.dram.readRowHitRate 91.54 # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl.dram.writeRowHitRate 89.39 # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl.dram.bytesPerActivate::samples 94434 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::mean 682.343393 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::gmean 543.240860 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::stdev 345.434522 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::0-127 5840 6.18% 6.18% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::128-255 7903 8.37% 14.55% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::256-383 8239 8.72% 23.28% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::384-511 8764 9.28% 32.56% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::512-639 6871 7.28% 39.83% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::640-767 10880 11.52% 51.36% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::768-895 4088 4.33% 55.68% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::896-1023 2979 3.15% 58.84% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::1024-1151 38870 41.16% 100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::total 94434 # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.dramBytesRead 36794368 # Total bytes read (Byte)
board.memory.mem_ctrl.dram.dramBytesWritten 27643392 # Total bytes written (Byte)
board.memory.mem_ctrl.dram.avgRdBW 1839.718400 # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.avgWrBW 1382.169600 # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.peakBW 19207.00 # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl.dram.busUtil 16.77 # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl.dram.busUtilRead 9.58 # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl.dram.busUtilWrite 7.20 # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl.dram.pageHitRate 90.62 # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl.dram.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl.dram.rank0.actEnergy 73232975.088000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preEnergy 129278861.762400 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.readEnergy 784804720.492800 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.writeEnergy 504007596.288001 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.refreshEnergy 1735597051.372696 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actBackEnergy 3300801818.932773 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preBackEnergy 4249273914.278311 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.totalEnergy 10776996938.215254 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.averagePower 538.849847 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::IDLE 12910219547 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::REF 898800000 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT 6190980453 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.actEnergy 74031375.600000 # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preEnergy 130688345.743200 # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.readEnergy 792120041.193602 # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.writeEnergy 514934743.680000 # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.refreshEnergy 1735597051.372696 # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actBackEnergy 3320429348.779171 # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preBackEnergy 4235723944.435114 # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.totalEnergy 10803524850.804058 # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.averagePower 540.176243 # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::IDLE 12868472359 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::REF 898800000 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::SREF 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::PRE_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT 6232727641 # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT_PDN 0 # Time in different power states (Tick)
board.memory.mem_ctrl.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.bad_addr.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.com_1.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.default_bus.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.empty_isa.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.fake_com_2.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.fake_com_3.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.fake_com_4.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.fake_floppy.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.pci_host.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.cmos.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.dma1.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.ide.disks.IdeDisk.dmaReadFullPages 0 # Number of full page size DMA reads (not PRD). (Count)
board.pc.south_bridge.ide.disks.IdeDisk.dmaReadBytes 0 # Number of bytes transfered via DMA reads (not PRD). (Byte)
board.pc.south_bridge.ide.disks.IdeDisk.dmaReadTxs 0 # Number of DMA read transactions (not PRD). (Count)
board.pc.south_bridge.ide.disks.IdeDisk.dmaWriteFullPages 0 # Number of full page size DMA writes. (Count)
board.pc.south_bridge.ide.disks.IdeDisk.dmaWriteBytes 0 # Number of bytes transfered via DMA writes. (Byte)
board.pc.south_bridge.ide.disks.IdeDisk.dmaWriteTxs 0 # Number of DMA write transactions. (Count)
board.pc.south_bridge.ide.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.io_apic.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.keyboard.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.pic1.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.pic2.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.pit.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.pc.south_bridge.speaker.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles 60060061 # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.cpi 1.325522 # CPI: cycles per instruction (core level) ((Cycle/Count))
board.processor.cores.core.ipc 0.754420 # IPC: instructions per cycle (core level) ((Count/Cycle))
board.processor.cores.core.numWorkItemsStarted 0 # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted 0 # Number of work items this cpu completed (Count)
board.processor.cores.core.instsAdded 95727798 # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.cores.core.nonSpecInstsAdded 202225 # Number of non-speculative instructions added to the IQ (Count)
board.processor.cores.core.instsIssued 92364838 # Number of instructions issued (Count)
board.processor.cores.core.squashedInstsIssued 1721596 # Number of squashed instructions issued (Count)
board.processor.cores.core.squashedInstsExamined 15843119 # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
board.processor.cores.core.squashedOperandsExamined 9638195 # Number of squashed operands that are examined and possibly removed from graph (Count)
board.processor.cores.core.squashedNonSpecRemoved 51223 # Number of squashed non-spec instructions that were removed (Count)
board.processor.cores.core.numIssuedDist::samples 59758539 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::mean 1.545634 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::stdev 2.546021 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::underflows 0 0.00% 0.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::0 39962202 66.87% 66.87% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::1 2730586 4.57% 71.44% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::2 2242498 3.75% 75.19% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::3 1385547 2.32% 77.51% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::4 1321190 2.21% 79.72% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::5 3035976 5.08% 84.80% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::6 4755991 7.96% 92.76% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::7 2604363 4.36% 97.12% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::8 1720186 2.88% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::overflows 0 0.00% 100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::min_value 0 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::max_value 8 # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::total 59758539 # Number of insts issued each cycle (Count)
board.processor.cores.core.statFuBusy::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntAlu 2424689 80.12% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntMult 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntDiv 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatAdd 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCmp 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCvt 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMult 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMultAcc 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatDiv 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMisc 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatSqrt 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAdd 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAddAcc 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAlu 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCmp 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCvt 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMisc 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMult 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMultAcc 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMatMultAcc 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShift 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShiftAcc 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdDiv 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSqrt 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAdd 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAlu 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCmp 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCvt 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatDiv 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMisc 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMult 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMultAcc 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMatMultAcc 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatSqrt 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAdd 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAlu 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceCmp 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceAdd 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceCmp 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAes 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAesMix 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash2 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash2 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma2 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma3 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdPredAlu 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::Matrix 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MatrixMov 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MatrixOP 0 0.00% 80.12% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemRead 169948 5.62% 85.74% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemWrite 431496 14.26% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IprAccess 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideMaskLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideMaskStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStridedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStridedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdIndexedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdIndexedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdWholeRegisterLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdWholeRegisterStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStrideSegmentedLoad 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdStrideSegmentedStore 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatExt 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdConfig 0 0.00% 100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statIssuedInstType_0::No_OpClass 4779304 5.17% 5.17% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntAlu 71373506 77.27% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntMult 382 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntDiv 799 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatAdd 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCmp 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCvt 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMult 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMultAcc 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatDiv 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMisc 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatSqrt 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAdd 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAddAcc 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAlu 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCmp 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCvt 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMisc 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMult 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMultAcc 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMatMultAcc 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShift 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShiftAcc 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdDiv 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSqrt 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAdd 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAlu 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCmp 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCvt 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatDiv 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMisc 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMult 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMultAcc 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMatMultAcc 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatSqrt 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAdd 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAlu 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceCmp 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceAdd 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceCmp 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAes 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAesMix 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash2 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash2 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma2 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma3 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdPredAlu 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::Matrix 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MatrixMov 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MatrixOP 0 0.00% 82.45% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemRead 7317989 7.92% 90.37% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemWrite 8892858 9.63% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemRead 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemWrite 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IprAccess 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::InstPrefetch 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStridedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStrideSegmentedLoad 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdStrideSegmentedStore 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatExt 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdConfig 0 0.00% 100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::total 92364838 # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.issueRate 1.537875 # Inst issue rate ((Count/Cycle))
board.processor.cores.core.fuBusy 3026133 # FU busy when requested (Count)
board.processor.cores.core.fuBusyRate 0.032763 # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.cores.core.intInstQueueReads 238175407 # Number of integer instruction queue reads (Count)
board.processor.cores.core.intInstQueueWrites 99161811 # Number of integer instruction queue writes (Count)
board.processor.cores.core.intInstQueueWakeupAccesses 86960789 # Number of integer instruction queue wakeup accesses (Count)
board.processor.cores.core.fpInstQueueReads 11060531 # Number of floating instruction queue reads (Count)
board.processor.cores.core.fpInstQueueWrites 12627894 # Number of floating instruction queue writes (Count)
board.processor.cores.core.fpInstQueueWakeupAccesses 0 # Number of floating instruction queue wakeup accesses (Count)
board.processor.cores.core.vecInstQueueReads 0 # Number of vector instruction queue reads (Count)
board.processor.cores.core.vecInstQueueWrites 0 # Number of vector instruction queue writes (Count)
board.processor.cores.core.vecInstQueueWakeupAccesses 0 # Number of vector instruction queue wakeup accesses (Count)
board.processor.cores.core.intAluAccesses 90611667 # Number of integer alu accesses (Count)
board.processor.cores.core.fpAluAccesses 0 # Number of floating point alu accesses (Count)
board.processor.cores.core.vecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.numRecvResp 14546539 # Number of received responses (Count)
board.processor.cores.core.numRecvRespBytes 100681245 # Number of received response bytes (Byte)
board.processor.cores.core.recvRespAvgBW 1.68 # Average bandwidth of received responses ((Byte/Cycle))
board.processor.cores.core.recvRespAvgSize 6.92 # Average packet size per received response ((Byte/Count))
board.processor.cores.core.recvRespAvgRate 0.24 # Average rate of received responses per cycle ((Count/Cycle))
board.processor.cores.core.recvRespAvgRetryRate 0.00 # Average retry rate per received response ((Count/Count))
board.processor.cores.core.numSendRetryResp 0 # Number of retry responses sent (Count)
board.processor.cores.core.numSquashedInsts 1632053 # Number of squashed instructions skipped in execute (Count)
board.processor.cores.core.numSwp 0 # Number of swp insts executed (Count)
board.processor.cores.core.timesIdled 3106 # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
board.processor.cores.core.idleCycles 301522 # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
board.processor.cores.core.MemDepUnit__0.insertedLoads 7533481 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.insertedStores 8983980 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingLoads 612919 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingStores 277000 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__1.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__2.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__3.insertedLoads 0 # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.insertedStores 0 # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingLoads 0 # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingStores 0 # Number of conflicting stores. (Count)
board.processor.cores.core.branchPred.lookups_0::NoBranch 822608 6.47% 6.47% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::Return 1660036 13.05% 19.52% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallDirect 1682948 13.23% 32.75% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::CallIndirect 27771 0.22% 32.97% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectCond 6277038 49.35% 82.32% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::DirectUncond 2248636 17.68% 100.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectCond 0 0.00% 100.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::IndirectUncond 2 0.00% 100.00% # Number of BP lookups (Count)
board.processor.cores.core.branchPred.lookups_0::total 12719039 # Number of BP lookups (Count)
board.processor.cores.core.branchPred.squashes_0::NoBranch 816849 25.62% 25.62% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::Return 213171 6.69% 32.30% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallDirect 263047 8.25% 40.55% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::CallIndirect 801 0.03% 40.58% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectCond 1408551 44.18% 84.75% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::DirectUncond 486146 15.25% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectCond 0 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::IndirectUncond 1 0.00% 100.00% # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.squashes_0::total 3188566 # Number of branches that got squashed (completely removed) as an earlier branch was mispredicted. (Count)
board.processor.cores.core.branchPred.corrected_0::NoBranch 359020 35.61% 35.61% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::Return 358880 35.60% 71.21% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallDirect 19996 1.98% 73.20% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::CallIndirect 394 0.04% 73.23% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectCond 267940 26.58% 99.81% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::DirectUncond 1885 0.19% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectCond 0 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::IndirectUncond 1 0.00% 100.00% # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.corrected_0::total 1008116 # Number of branches that got corrected but not yet commited. Branches get corrected by decode or after execute. Also a branch misprediction can be detected out-of-order. Therefore, a corrected branch might not end up beeing committed in case an even earlier branch was mispredicted (Count)
board.processor.cores.core.branchPred.earlyResteers_0::NoBranch 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::Return 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallDirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::CallIndirect 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::DirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectCond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::IndirectUncond 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.earlyResteers_0::total 0 # Number of branches that got redirected after decode. (Count)
board.processor.cores.core.branchPred.committed_0::NoBranch 5759 0.06% 0.06% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::Return 1446865 15.18% 15.24% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::CallDirect 1419901 14.90% 30.14% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::CallIndirect 26970 0.28% 30.42% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::DirectCond 4868479 51.08% 81.51% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::DirectUncond 1762490 18.49% 100.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::IndirectCond 0 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::IndirectUncond 1 0.00% 100.00% # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.committed_0::total 9530465 # Number of branches finally committed (Count)
board.processor.cores.core.branchPred.mispredicted_0::NoBranch 5759 1.11% 1.11% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::Return 349105 67.32% 68.43% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallDirect 18096 3.49% 71.92% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::CallIndirect 370 0.07% 71.99% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectCond 143854 27.74% 99.73% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::DirectUncond 1377 0.27% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectCond 0 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::IndirectUncond 1 0.00% 100.00% # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredicted_0::total 518562 # Number of committed branches that were mispredicted. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::NoBranch 5759 4.05% 4.05% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::Return 2 0.00% 4.05% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::CallDirect 1 0.00% 4.05% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::CallIndirect 0 0.00% 4.05% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::DirectCond 136353 95.95% 100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::DirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::IndirectCond 0 0.00% 100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::IndirectUncond 0 0.00% 100.00% # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToPredictor_0::total 142115 # Number of committed branches that were mispredicted by the predictor. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::NoBranch 0 0.00% 0.00% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::Return 349103 92.74% 92.74% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::CallDirect 18095 4.81% 97.54% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::CallIndirect 370 0.10% 97.64% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::DirectCond 7501 1.99% 99.63% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::DirectUncond 1377 0.37% 100.00% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::IndirectCond 0 0.00% 100.00% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::IndirectUncond 1 0.00% 100.00% # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.mispredictDueToBTBMiss_0::total 376447 # Number of committed branches that were mispredicted because of a BTB miss. (Count)
board.processor.cores.core.branchPred.targetProvider_0::NoTarget 4884068 38.40% 38.40% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::BTB 6148203 48.34% 86.74% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::RAS 1659990 13.05% 99.79% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::Indirect 26778 0.21% 100.00% # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetProvider_0::total 12719039 # The component providing the target for taken branches (Count)
board.processor.cores.core.branchPred.targetWrong_0::NoBranch 77635 15.23% 15.23% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::Return 73246 14.37% 29.60% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallDirect 358878 70.40% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::CallIndirect 3 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::DirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectCond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::IndirectUncond 0 0.00% 100.00% # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.targetWrong_0::total 509762 # Number of branches where the target was incorrect or not available at prediction time. (Count)
board.processor.cores.core.branchPred.condPredicted 6981256 # Number of conditional branches predicted (Count)
board.processor.cores.core.branchPred.condPredictedTaken 2155927 # Number of conditional branches predicted as taken (Count)
board.processor.cores.core.branchPred.condIncorrect 1008116 # Number of conditional branches incorrect (Count)
board.processor.cores.core.branchPred.predTakenBTBMiss 34214 # Number of branches predicted taken but missed in BTB (Count)
board.processor.cores.core.branchPred.BTBLookups 12719039 # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.BTBUpdates 222111 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.BTBHits 8467477 # Number of BTB hits (Count)
board.processor.cores.core.branchPred.BTBHitRatio 0.665732 # BTB Hit Ratio (Ratio)
board.processor.cores.core.branchPred.BTBMispredicted 35247 # Number BTB mispredictions. No target found or target wrong (Count)
board.processor.cores.core.branchPred.indirectLookups 27772 # Number of indirect predictor lookups. (Count)
board.processor.cores.core.branchPred.indirectHits 26778 # Number of indirect target hits. (Count)
board.processor.cores.core.branchPred.indirectMisses 994 # Number of indirect misses. (Count)
board.processor.cores.core.branchPred.indirectMispredicted 0 # Number of mispredicted indirect branches. (Count)
board.processor.cores.core.branchPred.btb.lookups::NoBranch 822608 6.47% 6.47% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::Return 1660036 13.05% 19.52% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallDirect 1682948 13.23% 32.75% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::CallIndirect 27771 0.22% 32.97% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectCond 6277038 49.35% 82.32% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::DirectUncond 2248636 17.68% 100.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectCond 0 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::IndirectUncond 2 0.00% 100.00% # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.lookups::total 12719039 # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.btb.misses::NoBranch 23126 0.54% 0.54% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::Return 1659996 39.04% 39.59% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallDirect 21320 0.50% 40.09% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::CallIndirect 27771 0.65% 40.74% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectCond 2516416 59.19% 99.93% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::DirectUncond 2931 0.07% 100.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectCond 0 0.00% 100.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::IndirectUncond 2 0.00% 100.00% # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.misses::total 4251562 # Number of BTB misses (Count)
board.processor.cores.core.branchPred.btb.updates::NoBranch 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::Return 0 0.00% 0.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallDirect 19996 9.00% 9.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::CallIndirect 0 0.00% 9.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectCond 200230 90.15% 99.15% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::DirectUncond 1885 0.85% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectCond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::IndirectUncond 0 0.00% 100.00% # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.updates::total 222111 # Number of BTB updates (Count)
board.processor.cores.core.branchPred.btb.mispredict::NoBranch 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::Return 0 0.00% 0.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallDirect 19996 9.00% 9.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::CallIndirect 0 0.00% 9.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectCond 200230 90.15% 99.15% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::DirectUncond 1885 0.85% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectCond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::IndirectUncond 0 0.00% 100.00% # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.mispredict::total 222111 # Number of BTB mispredictions. No target found or target wrong. (Count)
board.processor.cores.core.branchPred.btb.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.branchPred.indirectBranchPred.lookups 27772 # Number of lookups (Count)
board.processor.cores.core.branchPred.indirectBranchPred.hits 26778 # Number of hits of a tag (Count)
board.processor.cores.core.branchPred.indirectBranchPred.misses 994 # Number of misses (Count)
board.processor.cores.core.branchPred.indirectBranchPred.targetRecords 395 # Number of targets that where recorded/installed in the cache (Count)
board.processor.cores.core.branchPred.indirectBranchPred.indirectRecords 28168 # Number of indirect branches/calls recorded in the indirect hist (Count)
board.processor.cores.core.branchPred.indirectBranchPred.speculativeOverflows 2 # Number of times more than the allowed capacity for speculative branches/calls where in flight and destroy the path history (Count)
board.processor.cores.core.branchPred.ras.pushes 1923890 # Number of times a PC was pushed onto the RAS (Count)
board.processor.cores.core.branchPred.ras.pops 1923884 # Number of times a PC was poped from the RAS (Count)
board.processor.cores.core.branchPred.ras.squashes 477019 # Number of times the stack operation was squashed due to wrong speculation. (Count)
board.processor.cores.core.branchPred.ras.used 1446865 # Number of times the RAS is the provider (Count)
board.processor.cores.core.branchPred.ras.correct 1097760 # Number of times the RAS is the provider and the prediction is correct (Count)
board.processor.cores.core.branchPred.ras.incorrect 349105 # Number of times the RAS is the provider and the prediction is wrong (Count)
board.processor.cores.core.commit.commitSquashedInsts 15843095 # The number of squashed insts skipped by commit (Count)
board.processor.cores.core.commit.commitNonSpecStalls 151002 # The number of times commit has been forced to stall to communicate backwards (Count)
board.processor.cores.core.commit.branchMispredicts 929651 # The number of times a branch was mispredicted (Count)
board.processor.cores.core.commit.numCommittedDist::samples 56957521 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::mean 1.406081 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::stdev 2.539265 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::underflows 0 0.00% 0.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::0 38343796 67.32% 67.32% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::1 3723941 6.54% 73.86% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::2 2597845 4.56% 78.42% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::3 3032981 5.32% 83.74% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::4 1299919 2.28% 86.03% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::5 1312787 2.30% 88.33% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::6 1226244 2.15% 90.48% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::7 412844 0.72% 91.21% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::8 5007164 8.79% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::overflows 0 0.00% 100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::min_value 0 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::max_value 8 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::total 56957521 # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.amos 0 # Number of atomic instructions committed (Count)
board.processor.cores.core.commit.membars 77320 # Number of memory barriers committed (Count)
board.processor.cores.core.commit.functionCalls 1446871 # Number of function calls committed. (Count)
board.processor.cores.core.commit.committedInstType_0::No_OpClass 24092 0.03% 0.03% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntAlu 64776763 80.88% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntMult 343 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntDiv 769 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatAdd 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCmp 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCvt 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMult 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMultAcc 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatDiv 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMisc 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatSqrt 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAdd 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAddAcc 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAlu 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCmp 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCvt 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMisc 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMult 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMultAcc 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMatMultAcc 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShift 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShiftAcc 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdDiv 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSqrt 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAdd 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAlu 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCmp 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCvt 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatDiv 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMisc 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMult 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMultAcc 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMatMultAcc 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatSqrt 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAdd 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAlu 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceCmp 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceAdd 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceCmp 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAes 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAesMix 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash2 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash2 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma2 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma3 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdPredAlu 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::Matrix 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MatrixMov 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MatrixOP 0 0.00% 80.91% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemRead 6594476 8.23% 89.15% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemWrite 8690426 10.85% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IprAccess 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdConfig 0 0.00% 100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::total 80086869 # Class of committed instruction (Count)
board.processor.cores.core.commit.commitEligibleSamples 5007164 # number cycles where commit BW limit reached (Cycle)
board.processor.cores.core.commitStats0.numInsts 45310492 # Number of instructions committed (thread level) (Count)
board.processor.cores.core.commitStats0.numOps 80086869 # Number of ops (including micro ops) committed (thread level) (Count)
board.processor.cores.core.commitStats0.numInstsNotNOP 45310492 # Number of instructions committed excluding NOPs or prefetches (Count)
board.processor.cores.core.commitStats0.numOpsNotNOP 80086869 # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores.core.commitStats0.cpi 1.325522 # CPI: cycles per instruction (thread level) ((Cycle/Count))
board.processor.cores.core.commitStats0.ipc 0.754420 # IPC: instructions per cycle (thread level) ((Count/Cycle))
board.processor.cores.core.commitStats0.numMemRefs 15284902 # Number of memory references committed (Count)
board.processor.cores.core.commitStats0.numFpInsts 0 # Number of float instructions (Count)
board.processor.cores.core.commitStats0.numIntInsts 75603432 # Number of integer instructions (Count)
board.processor.cores.core.commitStats0.numLoadInsts 6594476 # Number of load instructions (Count)
board.processor.cores.core.commitStats0.numStoreInsts 8690426 # Number of store instructions (Count)
board.processor.cores.core.commitStats0.numVecInsts 0 # Number of vector instructions (Count)
board.processor.cores.core.commitStats0.committedInstType::No_OpClass 24092 0.03% 0.03% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntAlu 64776763 80.88% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntMult 343 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IntDiv 769 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatAdd 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCmp 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatCvt 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMult 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMultAcc 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatDiv 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMisc 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatSqrt 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAdd 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAddAcc 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAlu 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCmp 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdCvt 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMisc 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMult 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMultAcc 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdMatMultAcc 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShift 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShiftAcc 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdDiv 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSqrt 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAdd 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatAlu 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCmp 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatCvt 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatDiv 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMisc 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMult 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMultAcc 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatMatMultAcc 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatSqrt 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAdd 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceAlu 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdReduceCmp 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceAdd 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatReduceCmp 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAes 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdAesMix 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha1Hash2 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdSha256Hash2 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma2 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdShaSigma3 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdPredAlu 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::Matrix 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixMov 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MatrixOP 0 0.00% 80.91% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemRead 6594476 8.23% 89.15% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::MemWrite 8690426 10.85% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemRead 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::IprAccess 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::InstPrefetch 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideMaskStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStridedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdIndexedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdWholeRegisterStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdUnitStrideSegmentedFaultOnlyFirstLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedLoad 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdStrideSegmentedStore 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdFloatExt 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::SimdConfig 0 0.00% 100.00% # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedInstType::total 80086869 # Class of committed instruction. (Count)
board.processor.cores.core.commitStats0.committedControl::IsControl 9530465 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsDirectControl 8050870 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsIndirectControl 1473836 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCondControl 4868479 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsUncondControl 4661979 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsCall 1446871 # Class of control type instructions committed (Count)
board.processor.cores.core.commitStats0.committedControl::IsReturn 1446865 # Class of control type instructions committed (Count)
board.processor.cores.core.decode.idleCycles 2705001 # Number of cycles decode is idle (Cycle)
board.processor.cores.core.decode.blockedCycles 40530332 # Number of cycles decode is blocked (Cycle)
board.processor.cores.core.decode.runCycles 13309712 # Number of cycles decode is running (Cycle)
board.processor.cores.core.decode.unblockCycles 2266088 # Number of cycles decode is unblocking (Cycle)
board.processor.cores.core.decode.squashCycles 947406 # Number of cycles decode is squashing (Cycle)
board.processor.cores.core.decode.branchResolved 5581060 # Number of times decode resolved a branch (Count)
board.processor.cores.core.decode.branchMispred 83119 # Number of times decode detected a branch misprediction (Count)
board.processor.cores.core.decode.decodedInsts 106429199 # Number of instructions handled by decode (Count)
board.processor.cores.core.decode.squashedInsts 469186 # Number of squashed instructions handled by decode (Count)
board.processor.cores.core.executeStats0.numInsts 90726037 # Number of executed instructions (Count)
board.processor.cores.core.executeStats0.numNop 0 # Number of nop insts executed (Count)
board.processor.cores.core.executeStats0.numBranches 10838438 # Number of branches executed (Count)
board.processor.cores.core.executeStats0.numLoadInsts 7210697 # Number of load instructions executed (Count)
board.processor.cores.core.executeStats0.numStoreInsts 8821033 # Number of stores executed (Count)
board.processor.cores.core.executeStats0.instRate 1.510588 # Inst execution rate ((Count/Cycle))
board.processor.cores.core.executeStats0.numCCRegReads 36766365 # Number of times the CC registers were read (Count)
board.processor.cores.core.executeStats0.numCCRegWrites 29260198 # Number of times the CC registers were written (Count)
board.processor.cores.core.executeStats0.numFpRegWrites 0 # Number of times the floating registers were written (Count)
board.processor.cores.core.executeStats0.numIntRegReads 93323825 # Number of times the integer registers were read (Count)
board.processor.cores.core.executeStats0.numIntRegWrites 57185556 # Number of times the integer registers were written (Count)
board.processor.cores.core.executeStats0.numMemRefs 16031730 # Number of memory refs (Count)
board.processor.cores.core.executeStats0.numMiscRegReads 36597042 # Number of times the Misc registers were read (Count)
board.processor.cores.core.executeStats0.numMiscRegWrites 58095 # Number of times the Misc registers were written (Count)
board.processor.cores.core.executeStats0.numVecAluAccesses 0 # Number of vector alu accesses (Count)
board.processor.cores.core.executeStats0.numDiscardedOps 0 # Number of ops (including micro ops) which were discarded before commit (Count)
board.processor.cores.core.fetch.predictedBranches 7834971 # Number of branches that fetch has predicted taken (Count)
board.processor.cores.core.fetch.cycles 58048905 # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.cores.core.fetch.squashCycles 2051742 # Number of cycles fetch has spent squashing (Cycle)
board.processor.cores.core.fetch.tlbCycles 400 # Number of cycles fetch has spent waiting for tlb (Cycle)
board.processor.cores.core.fetch.pendingTrapStallCycles 5 # Number of stall cycles due to pending traps (Cycle)
board.processor.cores.core.fetch.cacheLines 9915733 # Number of cache lines fetched (Count)
board.processor.cores.core.fetch.icacheSquashes 3260 # Number of outstanding Icache misses that were squashed (Count)
board.processor.cores.core.fetch.tlbSquashes 10 # Number of outstanding ITLB misses that were squashed (Count)
board.processor.cores.core.fetch.nisnDist::samples 59758539 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::mean 1.934308 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::stdev 3.089520 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::0 39799435 66.60% 66.60% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::1 1192468 2.00% 68.60% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::2 1575010 2.64% 71.23% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::3 2690238 4.50% 75.73% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::4 1097903 1.84% 77.57% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::5 1960750 3.28% 80.85% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::6 876583 1.47% 82.32% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::7 805878 1.35% 83.67% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::8 9760274 16.33% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::min_value 0 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::max_value 8 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::total 59758539 # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetchStats0.numInsts 51108720 # Number of instructions fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.numOps 0 # Number of ops (including micro ops) fetched (thread level) (Count)
board.processor.cores.core.fetchStats0.fetchRate 0.850960 # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores.core.fetchStats0.numBranches 12719039 # Number of branches fetched (Count)
board.processor.cores.core.fetchStats0.branchRate 0.211772 # Number of branch fetches per cycle (Ratio)
board.processor.cores.core.fetchStats0.icacheStallCycles 683358 # ICache total stall cycles (Cycle)
board.processor.cores.core.fetchStats0.numFetchSuspends 0 # Number of times Execute suspended instruction fetching (Count)
board.processor.cores.core.iew.idleCycles 0 # Number of cycles IEW is idle (Cycle)
board.processor.cores.core.iew.squashCycles 947406 # Number of cycles IEW is squashing (Cycle)
board.processor.cores.core.iew.blockCycles 1900701 # Number of cycles IEW is blocking (Cycle)
board.processor.cores.core.iew.unblockCycles 370662 # Number of cycles IEW is unblocking (Cycle)
board.processor.cores.core.iew.dispatchedInsts 95930023 # Number of instructions dispatched to IQ (Count)
board.processor.cores.core.iew.dispSquashedInsts 4710 # Number of squashed instructions skipped by dispatch (Count)
board.processor.cores.core.iew.dispLoadInsts 7533481 # Number of dispatched load instructions (Count)
board.processor.cores.core.iew.dispStoreInsts 8983980 # Number of dispatched store instructions (Count)
board.processor.cores.core.iew.dispNonSpecInsts 123197 # Number of dispatched non-speculative instructions (Count)
board.processor.cores.core.iew.iqFullEvents 1619 # Number of times the IQ has become full, causing a stall (Count)
board.processor.cores.core.iew.lsqFullEvents 368347 # Number of times the LSQ has become full, causing a stall (Count)
board.processor.cores.core.iew.memOrderViolationEvents 19236 # Number of memory order violations (Count)
board.processor.cores.core.iew.predictedTakenIncorrect 447300 # Number of branches that were predicted taken incorrectly (Count)
board.processor.cores.core.iew.predictedNotTakenIncorrect 636308 # Number of branches that were predicted not taken incorrectly (Count)
board.processor.cores.core.iew.branchMispredicts 1083608 # Number of branch mispredicts detected at execute (Count)
board.processor.cores.core.iew.instsToCommit 90669926 # Cumulative count of insts sent to commit (Count)
board.processor.cores.core.iew.writebackCount 86960789 # Cumulative count of insts written-back (Count)
board.processor.cores.core.iew.producerInst 52797968 # Number of instructions producing a value (Count)
board.processor.cores.core.iew.consumerInst 81555270 # Number of instructions consuming a value (Count)
board.processor.cores.core.iew.wbRate 1.447897 # Insts written-back per cycle ((Count/Cycle))
board.processor.cores.core.iew.wbFanout 0.647389 # Average fanout of values written-back ((Count/Count))
board.processor.cores.core.interrupts.clk_domain.clock 5328 # Clock period in ticks (Tick)
board.processor.cores.core.lsq0.forwLoads 1354709 # Number of loads that had data forwarded from stores (Count)
board.processor.cores.core.lsq0.squashedLoads 939004 # Number of loads squashed (Count)
board.processor.cores.core.lsq0.ignoredResponses 56 # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.cores.core.lsq0.memOrderViolation 19236 # Number of memory ordering violations (Count)
board.processor.cores.core.lsq0.squashedStores 293545 # Number of stores squashed (Count)
board.processor.cores.core.lsq0.rescheduledLoads 523 # Number of loads that were rescheduled (Count)
board.processor.cores.core.lsq0.blockedByCache 1 # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.cores.core.lsq0.loadToUse::samples 6594476 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::mean 4.892010 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::stdev 38.783096 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::0-9 6493520 98.47% 98.47% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::10-19 55028 0.83% 99.30% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::20-29 2015 0.03% 99.33% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::30-39 3458 0.05% 99.39% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::40-49 1170 0.02% 99.40% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::50-59 441 0.01% 99.41% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::60-69 1041 0.02% 99.43% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::70-79 3038 0.05% 99.47% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::80-89 1500 0.02% 99.50% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::90-99 487 0.01% 99.50% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::100-109 540 0.01% 99.51% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::110-119 338 0.01% 99.52% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::120-129 282 0.00% 99.52% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::130-139 432 0.01% 99.53% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::140-149 128 0.00% 99.53% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::150-159 214 0.00% 99.53% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::160-169 3592 0.05% 99.59% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::170-179 357 0.01% 99.59% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::180-189 157 0.00% 99.59% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::190-199 108 0.00% 99.60% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::200-209 2084 0.03% 99.63% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::210-219 111 0.00% 99.63% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::220-229 90 0.00% 99.63% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::230-239 80 0.00% 99.63% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::240-249 937 0.01% 99.65% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::250-259 178 0.00% 99.65% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::260-269 56 0.00% 99.65% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::270-279 51 0.00% 99.65% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::280-289 271 0.00% 99.65% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::290-299 773 0.01% 99.67% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::overflows 21999 0.33% 100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::min_value 2 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::max_value 1394 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::total 6594476 # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.addedLoadsAndStores 16517461 # Number of loads and stores written to the Load Store Queue (Count)
board.processor.cores.core.mmu.dtb.rdAccesses 7196292 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrAccesses 8819096 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.dtb.rdMisses 6427 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrMisses 318 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.rdAccesses 0 # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.itb.wrAccesses 9915797 # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.itb.rdMisses 0 # TLB misses on read requests (Count)
board.processor.cores.core.mmu.itb.wrMisses 55 # TLB misses on write requests (Count)
board.processor.cores.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON 20000000000 # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.rename.squashCycles 947406 # Number of cycles rename is squashing (Cycle)
board.processor.cores.core.rename.idleCycles 3856492 # Number of cycles rename is idle (Cycle)
board.processor.cores.core.rename.blockCycles 3146889 # Number of cycles rename is blocking (Cycle)
board.processor.cores.core.rename.serializeStallCycles 16582475 # count of cycles rename stalled for serializing inst (Cycle)
board.processor.cores.core.rename.runCycles 14399064 # Number of cycles rename is running (Cycle)
board.processor.cores.core.rename.unblockCycles 20826213 # Number of cycles rename is unblocking (Cycle)
board.processor.cores.core.rename.renamedInsts 102324287 # Number of instructions processed by rename (Count)
board.processor.cores.core.rename.ROBFullEvents 36023 # Number of times rename has blocked due to ROB full (Count)
board.processor.cores.core.rename.IQFullEvents 183085 # Number of times rename has blocked due to IQ full (Count)
board.processor.cores.core.rename.LQFullEvents 5272 # Number of times rename has blocked due to LQ full (Count)
board.processor.cores.core.rename.SQFullEvents 20253006 # Number of times rename has blocked due to SQ full (Count)
board.processor.cores.core.rename.renamedOperands 143053061 # Number of destination operands rename has renamed (Count)
board.processor.cores.core.rename.lookups 279157421 # Number of register rename lookups that rename has made (Count)
board.processor.cores.core.rename.intLookups 98200539 # Number of integer rename lookups (Count)
board.processor.cores.core.rename.committedMaps 126130695 # Number of HB maps that are committed (Count)
board.processor.cores.core.rename.undoneMaps 16922300 # Number of HB maps that are undone due to squashing (Count)
board.processor.cores.core.rename.serializing 108246 # count of serializing insts renamed (Count)
board.processor.cores.core.rename.tempSerializing 104911 # count of temporary serializing insts renamed (Count)
board.processor.cores.core.rename.skidInsts 8964948 # count of insts added to the skid buffer (Count)
board.processor.cores.core.rename.intReturned 52460919 # count of registers freed and written back to integer free list (Count)
board.processor.cores.core.rob.reads 147874473 # The number of ROB reads (Count)
board.processor.cores.core.rob.writes 195057199 # The number of ROB writes (Count)
board.processor.cores.core.thread_0.numInsts 45310492 # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps 80086869 # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs 0 # Number of Memory References (Count)
board.workload.inst.arm 0 # number of arm instructions executed (Count)
board.workload.inst.quiesce 0 # number of quiesce instructions executed (Count)
---------- End Simulation Statistics ----------